UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`Case IPR2015-00158
`Patent 7,296,121 B2
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`SONY CORPORATION, SONY ELECTRONICS INC.,
`SONY MOBILE COMMUNICATIONS AB, and
`SONY MOBILE COMMUNICATIONS (USA) INC.
`Petitioners,
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`v.
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`MEMORY INTEGRITY, LLC,
`Patent Owner.
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`PETITIONERS’ OPPOSITION TO PATENT OWNER MOTION TO
`AMEND PURSUANT TO 37 C.F.R. § 42.23
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`Case IPR2015-00158
`Patent 7,296,121 B2
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`
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`
`
`SONY CORPORATION, SONY ELECTRONICS INC.,
`SONY MOBILE COMMUNICATIONS AB, and
`SONY MOBILE COMMUNICATIONS (USA) INC.
`Petitioners,
`
`v.
`
`MEMORY INTEGRITY, LLC,
`Patent Owner.
`
`
`
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`
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`PETITIONERS’ OPPOSITION TO PATENT OWNER MOTION TO
`AMEND PURSUANT TO 37 C.F.R. § 42.23
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`TABLE OF CONTENTS
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`Introduction ..................................................................................................... 1
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`Page
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`I.
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`II. MI’s Motion to Amend Fails to Comply with C.F.R. § 42.20(c) .................... 1
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`III. Substitute Claims 29-34 Are Not Enabled and Lack Written Description
`Support ............................................................................................................. 5
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`IV. Substitute Claims 29-34 Are Not Patentable Over the Prior Art .................... 6
`
`A.
`
`The Combination of the Culler Book, Laudon, and Smith Renders
`Claims 29-34 Obvious ........................................................................... 7
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`
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`1.
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`Claims 29-34 ............................................................................. 11
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`CONCLUSION .............................................................................................. 25
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`i
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`V.
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`LIST OF EXHIBITS
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`Exhibit Name
`Ex. No.
`Sony-1001 U.S. Patent No. 7,296,121 (“the ’121 Patent”)
`Sony-1002 File History for U.S. Pat. App. No. 10/966,161
`Sony-1003 U.S. Patent No. 7,003,633 (“the ’633 Patent”)
`Sony-1004 Comparison of ’121 Patent and ’633 Patent Specifications
`Sony-1005 U.S. Patent No. 7,698,509 to Koster (“Koster”)
`Jeffrey Kuskin, et al., The Stanford FLASH Multiprocessor,
`Sony-1006
`PROCEEDINGS ON THE 21ST ANNUAL INTERNATIONAL SYMPOSIUM ON
`COMPUTER ARCHITECTURE, IEEE (1994) (“Kuskin”)
`Sony-1007 S. Park et al., Verification of Cache Coherence Protocols by
`Aggregation of Distributed Transactions, Theory of Computing
`Systems 31 (1998) (“Park”)
`Sony-1008 U.S. Patent No. 6,088,769 to Luick (“Luick”)
`Sony-1009 U.S. Pat. Pub. 2002/0073261 (“Kosaraju”)
`Sony-1010 AUTHORITATIVE DICTIONARY OF IEEE STANDARDS TERMS (2000)
`Sony-1011
`Jeffrey L. Hilbert, APPLICATION SPECIFIC INTEGRATED CIRCUIT (ASIC)
`TECHNOLOGY (Academic Press 1991)
`Sony-1012 Ronald Sass, Andrew G. Schmidt, EMBEDDED SYSTEMS DESIGN WITH
`PLATFORM FPGAS: PRINCIPLES AND PRACTICES (Morgan Kaufmann
`2010)
`Sony-1013 Expert Declaration of Daniel J. Sorin
`Sony-1014 Curriculum Vitae of Daniel J. Sorin
`Sony-1015 Supplemental Expert Declaration of Daniel J. Sorin
`Sony-1016 Deposition Transcript of Vojin Oklobdzija (November 23–24, 2015)
`Sony-1017 David E. Culler et al., Parallel Computer Architecture: A
`Hardware/software Approach (1st Ed.) (1998)
`James Laudon and Daniel Lenoski, Proceedings of the 24th Annual
`International Symposium on Computer Architecture, “The SGI Origin:
`A ccNUMA Highly Scalable Server” (1997)
`
`Sony-1018
`
`ii
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`
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`Exhibit Name
`Ex. No.
`Sony-1019 Michael John Sebastian Smith, APPLICATION-SPECIFIC INTEGRATED
`CIRCUITS (1997) (“Smith”)
`Sony-1020 Motion to Amend Opposition Declaration of Dr. Robert Horst
`
`iii
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`
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`I.
`
`Introduction
`Petitioners submit this Opposition to Memory Integrity’s (“MI”) Motion to
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`Amend (“MTA”) (Paper 18). The MTA should be denied for three primary
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`reasons. First, MI failed to meet its burden of proof under 37 C.F.R. § 42.20(c) by
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`failing to identify how the features in the proposed substitute claims are
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`distinguished from the prior art of record. Second, the substitute claims are not
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`enabled. Third, the prior art combination discussed below render the substitute
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`claims obvious.
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`II. MI’s Motion to Amend Fails to Comply with 37 C.F.R. § 42.20(c)
`MI “has the burden of proof to establish that it is entitled to the requested
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`relief.” See 37 C.F.R. § 42.20(c). Section 42.20(c) “places the burden on the
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`patent owner to show a patentable distinction of each proposed substitute claim
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`over the prior art.” Idle Free Sys., Inc. v. Bergstrom, Inc., Case IPR2012-00027,
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`slip op. at 7 (PTAB June 11, 2013) (Paper 26); Microsoft Corp. v. Proxyconn, Inc.,
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`No. 2014-1542, 2015 WL 3747257, at *13-14 (Fed. Cir. June 16, 2015) (affirming
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`denial where patent owner failed to establish the patentability over the prior art of
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`record).
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`Here, MI failed to meet the burden imposed by § 42.20(c) for at least three
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`reasons. First, MI argues that, “all of the substitute claims find support in the ‘347
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`Application, [thus] the Koster reference is not prior art to any of the proposed
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`substitute claims.” MTA, p. 22. MI provides no discussion comparing Koster’s
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`1
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`
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`teachings to the “proposed new limitations.” However, claims 19-24 are not
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`entitled to the ’347 Application’s priority date. Because MI did not establish
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`patentability of the substitute claims over Koster, MI has not met its burden under
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`Section 42.20(c).
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`More specifically, in identifying support for the limitations of original
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`claims 19-24, MI relies entirely upon disclosure in “the ’893 App.” MTA, pp. 6-8.
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`However, Section 1.57(c) requires “essential material” to be incorporated by
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`reference “to a U.S. patent …, which … does not itself incorporate such essential
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`material by reference.” 37 C.F.R. § 1.57(c); see also 37 C.F.R. § 42.121(b)(1)
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`(must identify support in the original disclosure of the patent). However, here, the
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`’893 App is incorporated by reference into U.S. Application No. 10/157,388,
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`which is incorporated by reference into the ’347 App, which is incorporated by
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`reference into the ’161 App (the ’121 Patent’s application). See MTA, p. 6.
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`In other words, the relied upon essential material that is said to support
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`claims 19-24 is only present in an application that requires multiple incorporation
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`by references before finding its way into the ’161 App. For example, claim 19
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`recites “[a]t least one computer-readable medium having data structures stored
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`therein representative of the probe filtering unit of claim 16.” Neither, the ’347
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`App nor the ’388 App contain any description of this feature, or any of the other
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`features recited in claims 20-24. Therefore, claims 29-24 (and the corresponding
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`2
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`
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`substitute claims) are only entitled to a priority date no earlier than the filing date
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`of the ’161 App (Oct. 15, 2004). As such, Koster is eligible as prior art for
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`substitute claims 29-34, and MI was required by 37 C.F.R. § 42.20(c) to explain
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`why the claims are patentable over the Koster reference, which it did not.
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`Accordingly, for at least substitute claims 29-34, the MTA is deficient.
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`Second, the MTA fails to satisfy the Section 42.20(c) burden because it fails
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`to even mention, much less explain, why the claims are patentable over the
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`description of the SGI Origin system, set forth in the Culler reference (Ex. 1017)
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`on pp. 596 to 622. Further, MI did not identify that the Pong and Koster references
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`(Exs. 2040 and 1005) disclosed the newly proposed coherent and non-coherent
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`interface limitation in the substitute claims. See Ex. 1016 at 89:6-15 (MI’s expert
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`admitting that a probe filtering unit with a path to main memory is a non-coherent
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`interface); compare Pong Ex. 2040 at FIG. 1 and Koster Ex. 1005 at FIG. 4 (both
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`illustrating a path from controller to main memory). Further, with respect to the
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`other new limitation in the substitute claims, MESI states were well known in the
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`art. See Ex. 1016, 68:4-19. See Corning Optical Comm. RF, LLC v. PPC
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`Broadband, Inc., Case IPR2014-00441, Paper 19 at 4 (PTAB Oct. 30, 2014)
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`(patent owner must identify whether the new limitations were known anywhere).
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`Third, the MTA fails to satisfy Section 42.20(c) because MI’s expert
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`declaration is deficient. As explained in Idle Free, a “showing of patentable
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`3
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`
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`distinction can rely on declaration testimony of a technical expert about the
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`significance and usefulness of the feature(s) added by the proposed substitute claim
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`. . . .” Idle Free, slip op. at 7. However, MI’s expert makes no effort whatsoever
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`to testify regarding the significance and usefulness of the features added by the
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`proposed substitute claims.
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`These failures are emblematic of the fact that MI’s expert only spent about
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`5-10 hours reviewing the hundreds of prior art references of record (Ex. 1016,
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`21:1-23; 23:19 to 24:3), a review time per reference that does not meet the 37
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`C.F.R. § 42.20(c) burden in this case. Further, MI’s expert’s “patentabil[ity]”
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`opinion (Ex. 2019, ¶ 8) is completely unsupported as he failed to identify the legal
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`standard he used in forming this opinion.
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`MI was aware and familiar with the teachings of these references; Pong and
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`Koster are discussed in the IPR2015-00158, -00159 and -00163 Petitions and both
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`MI and its expert cited to the Culler book. Ex. 2016, ¶¶ 28, 90, 93. As will be
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`established in Section IV infra, the Culler Book in combination with Laudon and
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`Smith not only teaches the features of the original claims 19-24, it also teaches the
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`“proposed new features” added to each of substitute claims 29-34. Indeed, these
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`references clearly contradict MI’s argument that, “[a]mong . . . the prior art known
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`to MI, coherent protocol interfaces and non-coherent protocol interfaces are
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`generally not taught in the art.” MTA, p. 22; see, e.g., Ex. 1017, pp. 604, 607 (note
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`4
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`3), 610, 614 (discussing additional support for “noncoherent operations such as
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`uncached memory operations, I/O operations, and special synchronization
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`support”). In the pages that follow, the Culler book is applied to the amended
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`claims, but without even resolving whether arguments can be made in attempting
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`to distinguish the Culler book, we note that the failure of MI to even attempt to
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`distinguish it demonstrates that MI’s MTA does not meet the requirements of 37
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`C.F.R. § 42.20(c) and should be denied.
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`III. Substitute Claims 29-34 Are Not Enabled and Lack Written Description
`MI drafted “[e]ach of proposed substitute claims 29-34 . . . by first
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`converting the respective original claim 19-24 to independent form, and then
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`adding the same proposed new limitations….” MTA, p. 2. One of these
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`“proposed new limitations” is “wherein said probe filtering unit is coupled to a
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`coherent protocol interface and a non-coherent protocol interface.” Id. In support
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`of this limitation, MI cites only to FIG. 3, two lines from column 11, and seven
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`lines from column 13. MTA, pp. 9-10. However, this disclosure simply illustrates
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`the broad proposition that the cache coherence controller “can also include other
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`interfaces such as a non-coherent protocol interface 311 for communicating with
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`I/O devices.” Ex. 1001, 8:8-11. As such, MI’s support simply identifies where the
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`non-coherent protocol interface is located, but provides no details for how it is
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`implemented.
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`5
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`MI’s expert could not fix these §112 problems during his deposition. Dr.
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`Oklobdzija agreed that “one of ordinary skill would not have already had in their
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`knowledge how to build a system with a cache coherent interface and a non-cache
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`coherent interface.” Ex. 1016, 90:5-17. He then identified various ’121 figures,
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`that illustrated simple boxes labeled with the terms “coherent interface” and “non-
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`coherent interface” as providing enabling disclosure. Id. at 91:13-92:15.
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`However, he finally admitted that “the details [of how to have a system with both a
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`coherent interface and non-coherent interface] are not provided in the [’121] patent
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`… it is left to someone, you know, with the ordinary skill in the art to – to figure
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`out.” Id. at 95:14-96:10. Given these admissions, a POSITA would not be able to
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`make and use a system with the new limitation of “wherein said probe filtering unit
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`is coupled to a coherent protocol interface and a non-coherent protocol interface,”
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`nor to conclude that the inventor had possession of the claimed invention, as the
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`implementation details are not provided in the ’121 patent and are also not within
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`the knowledge of a POSITA.
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`IV. Substitute Claims 29-34 Are Not Patentable Over the Prior Art
`According to MI, proposed substitute claims 29-34 recite the same features
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`as respective original claims 19-24, but have been re-written in independent form,
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`to include the same “proposed new limitations.” MTA, p. 2. MI treats these
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`“proposed new limitations” in two parts:
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`6
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`
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`1. wherein said states comprise cache coherency states of a cache
`coherence protocol, and wherein said cache coherence protocol
`includes at least a modified state, an exclusive state, a shared state,
`and an invalid state, and
`2. wherein said probe filtering unit is coupled to a coherent protocol
`interface and a non-coherent protocol interface
`See, e.g., MTA, pp. 8-9.
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`As to the first feature, MI’s expert admitted that cache coherence protocols
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`that implement modified, exclusive, shared, and invalid states (i.e., the MESI
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`states) were well known in the art at the time of the ’121 Patent. See Ex. 1016,
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`68:4-19. Indeed, at least the disclosure of the Origin system in the Culler and
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`Laudon references, is an example of a system that implemented a protocol that
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`used the MESI states. See Ex. 1017, p. 598. As to the second feature, there were a
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`number of references that disclosed a probe filtering unit with both a coherent and
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`non-coherent protocol interface, including the Culler and Laudon.
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`A. The Combination of the Culler Book, Laudon, and Smith Renders
`Claims 29-34 Obvious
`The Culler Book includes a case study of the SGI Origin architecture. See
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`Ex. 1017, p. 596. Similarly, Laudon is titled “The SGI Origin: A ccNUMA Highly
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`Scalable Server” and describes the same SGI Origin architecture as described in
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`the Culler Book’s case study. Ex. 1018, p. 1. Both the Culler Book and Laudon
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`share similar system diagrams, particularly with regard to the Hub chip, which acts
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`7
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`as the probe filtering unit in the SGI Origin architecture and is shown nearly
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`identically in FIG. 8.21 of the Culler Book and FIG. 6 of Laudon. See Ex. 1017, p.
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`616; Ex. 1018, p. 245. Accordingly, it would have been obvious to a POSITA to
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`combine the teachings of the Culler Book and Laudon, as the combination of these
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`references would have provided a more complete and confirmatory teaching of the
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`SGI Origin architecture. Ex. 1020, ¶ 2.
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`The Culler Book describes that “[t]he Origin system is composed of a
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`number of processing nodes connected by switch-based interconnection network.”
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`Ex. 1017, p. 597. “The interconnection network has a hypercube topology,” which
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`is one form of the “scalable point-to-point interconnection network[s]” on which
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`the directory-based coherence protocols of Chapter 8 of the Culler Book are based.
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`Id., pp. 553, 596-597, 613; see Ex. 1020, ¶ 3 see also Ex. 1016, 132:24-134:1
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`(admitting that a switch-based network is a “point-to-point architecture”).
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`According to one implementation within the Culler Book, “[e]very processing
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`node contains two MIPS R10000 processors, each with first- and second-level
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`caches, a fraction of the total main memory of the machine, an I/O interface, and a
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`single-chip communication assist or cache coherence controller, called the Hub,
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`that implements the coherence protocol.” Ex. 1017, p. 597. Another of the Culler
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`Book implementations suggests a single processor for each node. Id., p. 597 (“for
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`simplicity that each node contains only one processor”). Similarly, Laudon
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`8
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`describes that “[e]ach node consists of one or two R10000 processors.” Ex. 1018,
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`p. 241 (emphasis added). Accordingly, it would have been obvious to a POSITA
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`to implement an SGI Origin machine in which each of multiple nodes has only a
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`single processor, and the following section applies such a configuration to claims
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`29-34.
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`The caches of an SGI Origin machine “use[] the same MESI states as used
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`in Chapter 5” of the Culler Book, which are “modified (M) or dirty, exclusive-
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`clean (E), shared (S), and invalid (I).” Ex. 1017, pp. 598, 299. In the directory
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`referenced by the Hub chip, these MESI states are represented by one of seven
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`directory states. Id. at 598. For example, the “shared” directory state indicates
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`“zero or more read-only cached copies whose whereabouts are indicated by [a]
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`presence vector.” Id. In this “shared” directory state, the presence vector
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`represents the processors within which a memory line is stored in the shared (S)
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`cache state and the processors within which a memory line has the not-present state
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`or the invalid (I) state. Ex. 1020, ¶ 5. On the other hand, “[a]n exclusive directory
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`state means the block may be in either dirty or (clean) exclusive state in the cache
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`(i.e., either the M or E states of the MESI protocol.” Ex. 1017, p, 598. Thus, the
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`information in the directory referenced by the Hub chip are representative of each
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`of the four MESI states. Ex. 1020, ¶ 5.
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`Each of the SGI Origin processors support “accesses that are under the
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`9
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`
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`control of the coherence protocol.” Ex. 1017, p. 607, n. 3. In addition, each
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`“processor also supports memory operations that are not visible to the coherence
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`protocol, called noncoherent memory operations, for which the system does not
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`guarantee any ordering.” Id. These noncoherent operations include “unchached
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`memory operations, I/O operations, and special synchronization support.” Id. at
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`604. For example, a processor can use uncached references to a special I/O
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`address space to “reference any physical I/O device in the machine.” Id. at 614;
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`Ex. 1020, ¶ 6.
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`Moreover, “[a]ll cache misses, whether to local or remote memory, go
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`through the Hub (which implements the coherence protocol), as do all uncached
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`operations.” Ex. 1017, pp. 612-613. In other words, both a processor and a Hub in
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`the SGI Origin architecture are capable of communicating coherent messages (e.g.,
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`cache misses) and noncoherent messages (e.g., uncached I/O operations) to other
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`components in the machine (e.g., each other), meaning that each contains a
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`“coherent protocol interface” and a “non-coherent protocol interface,” by MI’s
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`own construction of these terms. See MTA, p. 16; see also Ex. 1020, ¶¶ 6-7.
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`Accordingly, each Hub in the SGI Origin architecture is “coupled to a coherent
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`protocol interface and a non-coherent protocol interface,” as recited in the
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`proposed substitute claims, either because the Hub itself includes a coherent
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`protocol interface and a non-coherent protocol interface or because the Hub is
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`10
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`coupled to a processor that includes a coherent protocol interface and a non-
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`coherent protocol interface.
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`The following is an explanation of how a combination of the Culler Book
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`and Laudon render substitute claim 29 obvious. This explanation focuses on the
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`SGI Origin architecture’s handling of read requests where the requested memory
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`lines are in the “owned” directory state and the local, home, and owner nodes are
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`all separate from each other. As will be explained, the Hub chip of the home node
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`is the claimed “probe filtering unit,” the processors are the claimed “processing
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`nodes,” and the read requests are “probes corresponding to memory lines.”
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`1.
`
`Claims 29-34
`The proposed combination of the Culler Book and Laudon discloses “[a]
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`probe filtering unit for use in a computer system comprising a plurality of
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`processing nodes interconnected by a first point-to-point architecture,” as recited
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`in claim 29. See Ex. 1020, ¶¶ 2-3. The Culler Book describes that “[t]he Origin
`
`system is composed of a number of processing nodes connected by switch-based
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`interconnection network.” Ex. 1017, p. 597. “The interconnection network has a
`
`hypercube topology,” which is one form of the “scalable point-to-point
`
`interconnection network[s]” on which the directory-based coherence protocols of
`
`Chapter 8 of the Culler Book are based. Id., pp. 553, 597, 613; see Ex. 1020, ¶ 3
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`see also Ex. 1016, 132:24-134:1 (admitting that a switch-based network is a
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`11
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`“point-to-point architecture”).
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`According to Laudon, “[e]ach node consists of one or two R10000
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`processors,” and the Culler Book even “assumes for simplicity that each node
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`contains only one processor” when discussing the cache coherence protocol. Ex.
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`1018, p. 241 (emphasis added); Ex. 1017, p. 597. Moreover, an SGI Origin system
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`may contain “up to 512 nodes.” Ex. 1017, p. 612. The proposed Culler and
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`Lauden combination is a system having four nodes, each containing a single
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`processor. However, the proposed combination would be equally applicable for
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`systems containing more than four nodes. The following is an adaptation of FIG.
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`8.15 of the Culler Book that illustrates the proposed combination and annotates the
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`relevant components. See Ex. 1020, ¶ 4.
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`The proposed combination of the Culler Book and Laudon discloses “each
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`processing node having a cache memory associated therewith,” as recited in claim
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`12
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`
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`29. See Ex. 1020 ¶ 5. As described in the Culler Book, each of the processors in
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`the SGI Origin architecture is associated with “first- and second-level caches.” Ex.
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`1017, pp. 597, 612.
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`The proposed Culler Book and Laudon combination includes a “probe
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`filtering unit being operable to receive probes corresponding to memory lines from
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`the processing nodes and to transmit the probes only to selected ones of the
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`processing nodes with reference to probe filtering information representative of
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`states associated with selected ones of the cache memories,” as recited in claim 29.
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`See Ex. 1020, ¶¶ 8-19. As described below, the home node Hub chip performs the
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`recited functionality of a probe filtering unit with regard to at least read requests.
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`The following adaptation of Culler Book FIG. 8.15 illustrates the communication
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`of read requests A and B in the implementation of the SGI Origin system of the
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`proposed combination. See Ex. 1020, ¶ 8.
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`Probes Correspond to
`Memory Lines
`(i.e., Read Requests)
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`Selected Ones of the
`Processing Nodes
`(i.e., Owners)
`
`Probe Filtering Unit
`(i.e., Home Hub)
`
`Request A
`Request B
`
`13
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`Specifically, the home node Hub chip receives read requests for data blocks
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`from a local processing node. The received read requests are “probes
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`corresponding to memory lines from the processing nodes,” as recited in claim 29.
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`The Hub chip looks up a directory entry corresponding to the address of the data
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`block of the read request and forwards the read request depending on the state of
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`the data block. The directory look up and forwarding of the read request are
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`“transmit[ing] the probes only to selected ones of the processing nodes with
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`reference to probe filtering information representative of states associated with
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`selected ones of the cache memories,” as recited in claim 29.
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`“The Hub chip is the heart of the machine.” Ex. 1017, p. 612. The Hub chip
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`“implements the coherence protocol.” Id. The Hub chip “must . . . coordinate the
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`activities and dependences of all the different types of transactions that flow
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`through it from different components and implement the necessary pathways and
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`control.” Id., p. 614. “The Hub is divided into four major interfaces, one for each
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`type of external entity that it connects together: the processor interface or PI, the
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`memory/directory interface or MI, the network interface or NI, and the I/O
`
`interface or II (see Figure 8.21).” Id., p. 615; Ex. 1020, ¶ 9.
`
`Each of the interfaces of the Hub chip “communicate with one another
`
`through an on-chip crossbar switch.” Ex. 1017, p. 615. “A key property of the
`
`design is for each interface to shield its external entity from the details of other
`
`14
`
`
`
`
`interfaces and entities (and vice versa).” Id. One example of this shielding is
`
`performed, during read requests, where the directory interface “treats a cache at the
`
`home just like any other cache; the only difference is that a ‘message’ between a
`
`home directory and a cache at home does not translate to a network transaction.”
`
`Id., p. 599. As a consequence, the processor and its associated cache in the home
`
`node will not receive a read request sent to the home node’s Hub chip, unless the
`
`memory directory interface of the Hub chip determines that the cache of the
`
`processor in the home node owns the requested cache line. Ex. 1020, ¶ 10.
`
`The following is an explanation of how a read request issued by a processor
`
`in a local/requesting node for a memory line associated with a separate home node
`
`flows through the proposed SGI Origin system when the requested memory line is
`
`owned in the Modified (M) or Exclusive (E) state by a processor in a separate
`
`owner node. Id., ¶ 11. According to the Culler Book, when “a processor issues a
`
`read that misses in its cache hierarchy . . . [, t]he address of the miss is examined
`
`by the local Hub to determine the home node, and a read request transaction is sent
`
`to the home node to look up the directory entry.” Ex. 1017, p. 599. This is
`
`illustrated in the following annotation of Culler Book FIG. 8.21, where “A” is the
`
`read request. Ex. 1020, ¶ 11. This message flow corresponds to the yellow and
`
`purple arrows from the local/requesting process to the Hub chip of the home node
`
`in the above adaptation of FIG. 8.15 of the Culler Book. Ex. 1020, ¶ 11.
`
`15
`
`
`
`
`
`
`According to the Culler Book, “[a]t the home, the data for the block is
`
`accessed speculatively in parallel with looking up the directory entry.” Ex. 1017,
`
`p. 599. The memory/directory interface of the Hub chip of the home node contains
`
`a directory interface, which “contains the logic and tables that determine what
`
`protocol actions to take and hence implement the coherence protocol.” Id., p. 617.
`
`The directory stores directory information, including states, for each memory block
`
`stored in the memory of the node. See Id., pp. 598, 609; Ex. 1020, ¶¶ 12-13.
`
`“At the directory, a block may be in one of seven states” including
`
`“unowned, or no cached copies in the system; shared, that is, zero or more read-
`
`only cached copies whose whereabouts are indicated by the presence vector; and
`
`exclusive, or one read-write cached copy in the system . . . .” Ex. 1017, p. 598
`
`(emphasis in original). “An exclusive directory state means the block may be in
`
`16
`
`
`
`
`either dirty or (clean) exclusive state in the cache (i.e., either the M or E states of
`
`the MESI protocol).” Id. When a request memory block is in the exclusive
`
`directory state (i.e., either the M or E states of the MESI protocol) and the home is
`
`not the owner of the block, “the valid data for the block must be obtained from the
`
`owner and must find its way to the requestor as well as to the home (since the state
`
`will change to shared).” Ex. 1017, p. 599; Ex. 1020, ¶ 14.
`
`“The Origin protocol uses reply forwarding; the request is forwarded to the
`
`owner, which replies directly to the requestor, sending a revision message to the
`
`home” node. Ex. 1017, p. 599. In other words, the same request that was received
`
`by the home node Hub chip is forwarded to the owner processor. Ex. 1020, ¶ 15.
`
`Importantly, in the example described here where the requested memory line is
`
`owned by a processor in a different node, neither the processor in the home node
`
`nor its associated cache receive the read request, because the Hub chip interface
`
`shields its external entity from the details of other interfaces and entities. Id.
`
`Moreover, according to the Culler Book, “[i]f a block is in an exclusive state
`
`(i.e., modified or exclusive) in a processor cache, then the rest of the directory
`
`entry is not a bit vector with one bit turned on; rather, it contains an explicit pointer
`
`to the specific processor (not node). This means that interventions forwarded from
`
`the home are targeted to a specific processor.” Ex. 1017., p. 609. The
`
`memory/directory interface of the home Hub chip uses this pointer to address the
`
`17
`
`
`
`
`read request to the owner node, and the network interface of the home Hub chip
`
`uses the address to forward the read request only to the specifically addressed
`
`processor. See Id., pp. 617-18; see also Ex. 1020, ¶ 16.
`
`The handling of a read request by the home node Hub chip is illustrated in
`
`the following annotation of FIG. 8.21 of the Culler book, where “A-in” is the read
`
`request received by the home hub over the interconnection network from the local
`
`processor of the local node, “A-out” illustrates that “the request is forwarded to the
`
`owner” across the interconnection network by the home hub, and “Spec” is the
`
`result of the speculative memory read that is returned by the home hub across the
`
`interconnection network to the Hub chip of the local node. Ex. 1020, ¶ 17. In the
`
`annotated Culler FIG. 8.15 above, this message flow corresponds to the yellow and
`
`purple arrows from the home node Hub chip to the processor indicated in the
`
`directory information to be the owner of the memory line. Id.
`
`18
`
`
`
`
`A‐in
`
`A‐out
`
`Spec
`
`
`
`Remote Home Hub
`
`Does not
`receive request
`
`
`
`According to the Culler book, when the owner processor receives the
`
`request, the Hub chip associated with the owner ensures that a reply is sent to the
`
`local requesting processor and a revision message is sent to the home node Hub
`
`chip so that it can update the directory state information. See Ex. 1017, pp. 599-
`
`600, 617-18; see also Ex. 1020, ¶ 18. Because a read request in the Origin system
`
`elicits a response from the owner processor to maintain cache coherency (e.g., the
`
`reply by the owner processor causes a revision message to be sent to the home), the
`
`read request is a probe.
`
`As described above, the memory/directory interface of the home node’s Hub
`
`chip determines the owner processor with reference to the directory information
`
`stored in the directory and forwards the read request only to that owner processor.
`
`19
`
`
`
`
`Ex. 1020, ¶ 19. Accordingly, the Hub chip of the home node (probe filtering unit)
`
`is operable to receive read requests (i.e., probes corresponding to memory lines)
`
`from any of the processors of the system (i.e., the processing nodes) and to
`
`transmit the read requests only to selected ones of the processors that own the
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`requested data (i.e., only to selected ones of the processing nodes) with reference
`
`to directory information (i.e., probe filtering information) representative of states
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`associated with selected ones of the cache memories. Id.
`
`The proposed combination of the Culler Book and Laudon discloses that
`
`“said states comprise cache coherency states of a cache coherence protocol, and
`
`wherein said cache coherence protocol includes at least a modified state, an
`
`exclusive state, a shared state, and an invalid state,” as recited in claim 29. See
`
`Ex. 1020, ¶ 5. The caches of an SGI Origin machine “use[] the same MESI states
`
`as used in Chapter 5” of the Culler Book, which are “modified (M) or dirty,
`
`exclusive-clean (E), shared (S), and invalid (I).” Ex. 1017, pp. 598, 299. In the
`
`directory referenced by the Hub chip, these MESI states are represented by one of
`
`seven directory states. Ex. 1017, p. 598. For example, the “shared” directory state
`
`indicates “zero or more read-only cached copies whose whereabouts are indicated
`
`by [a] presence bit vector.” Id. In this “shared” directory state, the presence bit
`
`vector represents in which processors a memory line is stored in the shared (S)
`
`cache state and in which processors a memory line is in the not-present state or the
`
`20
`
`
`
`
`invalid (I) state. Ex. 1020, ¶ 5. On the other hand, “[a]n exclusive directory state
`
`means the block may be in either dirty or (clean) exclusive state in the cache (i.e.,
`
`either the M or E states of the MESI protocol).” Ex. 1017, p, 598. In other words,
`
`a requested block that is in the M state of the MESI protocol in a processor’s cache
`
`is represented in the directory by the exclusive directory state, and a requested
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`block that is in the E state of the MESI protocol in a processor’s cache is also
`
`represented in the directory by the exclusive directory state. Ex. 1020, ¶ 5.
`
`Thus, the information in the directory referenced
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