UNITED STATES PATENT AND TRADEMARK OFFICE
`
`__________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`__________________________________________________________________
`
`SONY CORPORATION; SONY MOBILE COMMUNICATIONS AB; SONY
`MOBILE COMMUNICATIONS (USA) INC; AND SONY ELECTRONICS INC.
`Petitioners
`
`
`Patent No. 7,296,121
`Issue Date: Nov. 13, 2007
`Title: REDUCING PROBE TRAFFIC IN MULTIPROCESSOR SYSTEMS
`__________________________________________________________________
`
`PETITION FOR INTER PARTES REVIEW
`
`OF U.S. PATENT NO. 7,296,121
`
`No. IPR2015-00158
`
`__________________________________________________________________
`
`
`
`

`

`Petition for Inter Partes Review of U.S. Pat. No. 7,296,121
`
`Table of Contents
`
`
`I.  Mandatory Notices (37 C.F.R. § 42.8) ....................................................... 1 
`II.  Grounds for Standing (37 C.F.R. § 42.104(a)) .......................................... 2 
`III. 
`Identification of Challenge (37 C.F.R. § 42.104(b)(1)-(3)) and Relief
`Requested (37 C.F.R. § 42.22(a)(1)) ......................................................... 2 
`A. 
`Background of the ’121 Patent ....................................................................... 2 
`B. 
`Prosecution History of the ’121 Patent ......................................................... 4 
`C. 
`Priority Date of the ’121 Patent ...................................................................... 4 
`D. 
`Patents and Printed Publications Relied On ................................................. 7 
`E. 
`Statutory Grounds for Challenge .................................................................13 
`F. 
`Claim Construction .........................................................................................13 
`IV.  How the Challenged Claims Are Unpatentable (37 C.F.R. §
`42.104(b)(4)-(5)). ...................................................................................... 19 
`A. 
`Koster Anticipates Claims 1-3, 8, 11-12, 14-16 and 25 Under 35
`U.S.C. § 102(e). ................................................................................................19 
`Koster Alone Renders Claims 17-18 and 24 Obvious Under
`35 U.S.C. § 103(a). ..........................................................................................24 
`Koster in view of Kuskin Renders Claims 19-23 Obvious Under
`35 U.S.C. § 103(a). ..........................................................................................25 
`D.  Koster in view of Kuskin and Park Renders Claims 15 and 25
`Obvious Under 35 U.S.C. § 103(a). ..............................................................29 
`Luick in view of Kosaraju Renders Claims 1-3, 8, 11-12, 14-18,
`and 24-25 Obvious Under 35 U.S.C. § 103(a). ...........................................31 
`Luick in view of Kosaraju and Kuskin Renders Claims 19-23
`Obvious Under 35 U.S.C. § 103(a). ..............................................................40 
`Luick in view of Kosaraju, Kuskin, and Park Renders Claims 15
`and 25 Obvious Under 35 U.S.C. § 103(a). ................................................42 
`The Grounds Based on Koster (A, B, C, and D) are Not
`Redundant Over the Grounds Based on Luick in view of
`Kosaraju (E, F, and G). ..................................................................................44 
`
`B. 
`
`C. 
`
`E. 
`
`F. 
`
`G. 
`
`H. 
`
`
`
`i
`
`

`

`Petition for Inter Partes Review of U.S. Pat. No. 7,296,121
`
`I. 
`
`The Grounds Based on Kuskin and Park (D and G) are Not
`Redundant Over the Grounds Without Kuskin and Park (A and
`E). ......................................................................................................................46 
`Conclusion .............................................................................................. 47 
`V. 
`VI.  Appendix: Abridged Claim Charts ......................................................... 48 
`A. 
`Koster ...............................................................................................................48 
`B. 
`Kuskin ...............................................................................................................51 
`C. 
`Park ...................................................................................................................52 
`D. 
`Luick .................................................................................................................53 
`E. 
`Kosaraju ............................................................................................................59 
`
`
`
`
`
`
`
`
`
`ii
`
`

`

`Petition for Inter Partes Review of U.S. Pat. No. 7,296,121
`
`List of Exhibits
`
`Sony-1007
`
`Exhibit Name
`Ex. No.
`Sony-1001 U.S. Patent No. 7,296,121 (“the ’121 Patent”)
`Sony-1002
`File History for U.S. Pat. App. No. 10/966,161
`Sony-1003 U.S. Patent No. 7,003,633 (“the ’633 Patent”)
`Sony-1004 Comparison of ’121 Patent and ’633 Patent Specifications
`Sony-1005 U.S. Patent No. 7,698,509 to Koster (“Koster”)
`Jeffrey Kuskin, et al., The Stanford FLASH Multiprocessor, PROCEEDINGS
`Sony-1006
`ON THE 21ST ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER
`ARCHITECTURE, IEEE (1994) (“Kuskin”)
`S. Park et al., Verification of Cache Coherence Protocols by Aggregation of
`Distributed Transactions, Theory of Computing Systems 31 (1998) (“Park”)
`Sony-1008 U.S. Patent No. 6,088,769 to Luick (“Luick”)
`Sony-1009 U.S. Pat. Pub. 2002/0073261 (“Kosaraju”)
`Sony-1010 AUTHORITATIVE DICTIONARY OF IEEE STANDARDS TERMS (2000)
`Sony-1011
`Jeffrey L. Hilbert, APPLICATION SPECIFIC INTEGRATED CIRCUIT (ASIC)
`TECHNOLOGY (Academic Press 1991)
`Ronald Sass, Andrew G. Schmidt, EMBEDDED SYSTEMS DESIGN WITH
`PLATFORM FPGAS: PRINCIPLES AND PRACTICES (Morgan Kaufmann
`2010)
`Sony-1013 Expert Declaration of Daniel J. Sorin
`Sony-1014 Curriculum Vitae of Daniel J. Sorin
`
`
`Sony-1012
`
`
`
`iii
`
`

`

`Petition for Inter Partes Review of U.S. Pat. No. 7,296,121
`
`I. Mandatory Notices (37 C.F.R. § 42.8)
`Real Party-in-Interest: Sony Corporation; Sony Electronics Inc.; Sony Mobile
`
`Communications AB; and Sony Mobile Communications (USA) Inc. (“Sony” or
`
`“Petitioners”).
`
`Related Matters: Memory Integrity LLC initiated lawsuits against twenty one
`
`companies in the United States District Court for the District of Delaware, alleging
`
`infringement of U.S. Patent No. 7,296,121. Nineteen cases remain pending.
`
`Accordingly, the following pending matters may affect or be affected by the decision
`
`in this proceeding: 13-cv-01795-GMS (D. Del.); 13-cv-01796-GMS (D. Del.); 13-cv-
`
`01797-GMS (D. Del.); 13-cv-01798-GMS (D. Del.); 13-cv-01799-GMS (D. Del.); 13-
`
`cv-01800-GMS (D. Del.); 13-cv-1801-GMS (D. Del.); 13-cv-01802-GMS (D. Del.);
`
`13-cv-01803-GMS (D. Del.); 13-cv-01804-GMS (D. Del.); 13-cv-1805-GMS (D. Del.);
`
`13-cv-1806-GMS (D. Del.); 13-cv-1807-GMS (D. Del.); 13-cv-1808-GMS (D. Del.);
`
`13-cv-1809-GMS (D. Del.); 13-cv-1810-GMS (D. Del.); 13-cv-1811-GMS (D. Del.);
`
`13-cv-1983-GMS (D. Del.); and 13-cv-1984-GMS (D. Del.).
`
`Lead Counsel:
`
`Lewis V. Popovski, Reg. No. 37,423.
`
`Backup Counsel: Zaed M. Billah, Reg. No. 71,418; Michael Sander, Reg. No. 71,667.
`
`E-Service:
`
`MemoryIntegrityv.Sony10760-225@kenyon.com.
`
`Delivery:
`
`Kenyon & Kenyon LLP, One Broadway, New York, NY 10004.
`
`Telephone:
`
`212-425-7200
`
`Facsimile:
`
`212-425-5288
`
`
`
`1
`
`

`

`Petition for Inter Partes Review of U.S. Pat. No. 7,296,121
`
`II. Grounds for Standing (37 C.F.R. § 42.104(a))
`Petitioners certify that the patent for which review is sought, U.S. Patent No.
`
`7,296,121 (“the ’121 Patent,” Sony-1001), is available for inter partes review and that
`
`Petitioners are not estopped from requesting an inter partes review challenging the
`
`patent claims on the grounds identified in this Petition. Petitioners submit that,
`
`pursuant to 35 U.S.C. § 315(b), they are not barred from filing this Petition because
`
`Petitioners (including any privies) were not served with a complaint asserting
`
`infringement of the ’121 Patent more than one year prior to the filing of this Petition.
`
`III.
`
`Identification of Challenge (37 C.F.R. § 42.104(b)(1)-(3)) and Relief
`Requested (37 C.F.R. § 42.22(a)(1))
`
` Petitioners challenge claims 1-3, 8, 11-12, and 14-25 of the ’121 Patent under
`
`35 U.S.C. §§ 102 and 103, and cancellation of those claims is requested.
`
`Background of the ’121 Patent
`
`A.
`The ’121 Patent states that the invention relates to increasing the efficiency of
`
`memory transactions in a point-to-point multiple processor computer system. See
`
`’121 Patent at 2:46-59. Conventional multiple processor computer systems have
`
`processors coupled to system memory. See ’121 Patent at 1:27-30. To optimize
`
`access to system memory, individual processors are typically designed to work with a
`
`cache memory, which is loaded with data that the processor frequently accesses. See
`
`id. at 1:30-34. However, when multiple copies of the same data co-exist within
`
`multiple processors’ cache memories, cache coherency problems can arise. See id. at
`
`
`
`2
`
`

`

`Petition for Inter Partes Review of U.S. Pat. No. 7,296,121
`
`1:35-38. For example, a frequently accessed block of data may be loaded into the
`
`cache memory of two different processors. Id. at 1:38-40. If one processor writes a
`
`data value to its own cache memory, it will not be reflected in other processors’ cache
`
`memory, which gives rise to a problem called cache coherency. Id. at 1:40-45. One
`
`method of maintaining cache coherency is to broadcast every request for data,
`
`referred to as a “probe,” to every processor node in the multiple processor computer
`
`system. See id. 5:56-61. In this way, state information associated with various memory
`
`lines within the cache may be maintained. See id. at 5:61-64.
`
`In reference to Figure 18 (reproduced below), the ’121 Patent describes a cache
`
`coherency system as applied to a point-to-point multiprocessor architecture, where
`
`“multiple processors [are] directly connected to each other through point-to-point
`
`links.” Id. 4:38-40, Fig. 18; see also id. at 26:58-30:37.
`
`Fig. 18 of the ’121 Patent
`
`
`
`
`
`3
`
`

`

`Petition for Inter Partes Review of U.S. Pat. No. 7,296,121
`
`The ‘’121 Patent explains that when a processor node sends a probe in order to
`
`request data, the probe is sent only to a “probe filtering unit” or PFU “rather than on
`
`all of the node interfaces.” See id. at 28:8-14. If the PFU determines that data is not
`
`cached anywhere in the system, the PFU responds to the probe accordingly. See id. at
`
`28:39-42. No traffic or query is sent to any of the other nodes. See id. If the PFU
`
`determines the data may be cached in another processor node, the PFU sends a probe
`
`only on links corresponding to the nodes that may contain the cache line. See id. at
`
`28:50-53. The “outgoing probe is the same as the incoming probe, except that it is
`
`modified to identify the PFU as the target, i.e., the source of the probe.” See id. at
`
`28:53-55. The node that receives the modified probe looks up the cache line and
`
`returns the response to the PFU. See id. at 28:59-61. The PFU then uses the
`
`responses to update its own directory and responds to the node from which the
`
`original request originated. See id. at 28:61-67.
`
`In this way, the ’121 Patent explains, the PFU “allows a multi-processor system to
`
`scale better because it reduces or eliminates unnecessary probes that go to nodes that
`
`are known not to be caching the desired data.” See id. at 30:20-23.
`
`Prosecution History of the ’121 Patent
`
`B.
`The ’121 Patent issued without a single rejection. See Sony-1002.
`
`Priority Date of the ’121 Patent
`
`C.
`“[T]o gain the benefit of the filing date of an earlier application under 35 U.S.C.
`
`§ 120, each application in the chain leading back to the earlier application must
`
`
`
`4
`
`

`

`Petition for Inter Partes Review of U.S. Pat. No. 7,296,121
`
`comply with the written description requirement of 35 U.S.C. § 112.” Zenon Envtl.,
`
`Inc. v. U.S. Filter Corp., 506 F.3d 1370, 1378 (Fed. Cir. 2007) (quoting Lockwood v. Am.
`
`Airlines, Inc., 107 F.3d 1565, 1571 (Fed. Cir. 1997)). To satisfy the written description
`
`requirement, the specification must convey with reasonable clarity to one of skill in
`
`the art that the applicant was in possession of the claimed invention as of the filing
`
`date being sought. See, e.g., Synthes USA, LLC v. Spinal Kinetics, Inc., 734 F.3d 1332,
`
`1341 (Fed. Cir. 2013) (quoting Ariad Pharm., Inc. v. Eli Lilly & Co., 598 F.3d 1336,
`
`1351 (Fed. Cir. 2010)). All of the claim limitations must be disclosed in the
`
`specification, either expressly or inherently; it is insufficient for a limitation to be
`
`obvious in view of what is described. See Lockwood, 107 F.3d at 1571-72 (“Entitlement
`
`to a filing date does not extend to subject matter which is not disclosed, but would be
`
`obvious over what is expressly disclosed. It extends only to that which is disclosed.”);
`
`see also PowerOasis, Inc. v. T-Mobile USA, Inc., 522 F.3d 1299, 1306 (Fed. Cir. 2008).
`
`Claims 1-3, 8, 11-12, and 14-25 are entitled to a priority date no earlier than
`
`October 15, 2004, which is the filing date of the application for the ’121 Patent. The
`
`’121 Patent is a continuation-in-part of U.S. Pat. App. 10/288,347, filed November 4,
`
`2002, now U.S. Pat. No. 7,003,633 (“the ’633 Patent,” Sony-1003). The ’121 Patent’s
`
`specification adds a significant amount of new material to the disclosure of the ’633
`
`Patent. See Comparison of ’121 Patent and ’633 Patent Specifications, Sony-1004.
`
`In particular, claims 1-3, 8, 11-12, and 14-25 of the ’121 Patent are not entitled to
`
`the priority date of the ’633 Patent because the ’633 Patent does not describe any of
`
`
`
`5
`
`

`

`Petition for Inter Partes Review of U.S. Pat. No. 7,296,121
`
`the numerous limitations related to the claimed “probe filtering unit” and its
`
`functionality. See ’121 Patent at independent claims 1, 16, 25. Indeed, the term
`
`“probe filtering unit” does not appear anywhere in the specification of the ’633
`
`Patent. Instead, the entirety of the disclosure pertaining to the “probe filtering unit”
`
`was first introduced in the specification of the ’121 Patent.
`
`As the ’121 Patent explains:
`
`A probe filtering unit is operable to receive probes corresponding to memory
`lines from the processing nodes and to transmit the probes only to selected ones
`of the processing nodes with reference to probe filtering information.
`See id. at 2:52-56. This description, and any discussion of a “unit” that performs
`
`probe filtering, is absent from the ’633 Patent. Further, the only diagram showing a
`
`multiprocessor architecture using a “probe filtering unit” is Figure 18 of the ’121
`
`Patent, which is likewise absent from the ’633 Patent.
`
`Moreover, it should be noted that while the ’633 Patent does include some
`
`discussion of “probe filtering information” (but not a “probe filtering unit”), the
`
`definition of “probe filtering information” changed between the ’633 Patent and the
`
`’121 Patent such that the definition in the ’633 Patent is admittedly unrelated to the
`
`claims of the ’121 Patent. Specifically, the ’633 Patent expressly defines the term
`
`“probe filtering information” as “[a]ny criterion that can be used to reduce the
`
`number of clusters probed from a home cluster.” ’633 Patent at 14:20-22. However,
`
`in the ’121 Patent, the definition of the term “probe filtering information” was
`
`
`
`6
`
`

`

`Petition for Inter Partes Review of U.S. Pat. No. 7,296,121
`
`changed into “[a]ny criterion that can be used to reduce the number of clusters or
`
`nodes probed from a home cluster.” ’121 Patent at 14:50-52. Thus, Patent Owner
`
`intentionally broadened the term “probe filtering information” in the ’121 Patent to
`
`include the filtering of probes transmitted to nodes as opposed to the filtering of
`
`probes transmitted to clusters. The specification of the ’121 Patent added many
`
`changes to support this additional concept relating to the application of probe filtering
`
`techniques to nodes. See, e.g., Sony-1004 at 8, 15, 17, 18, 22-35. This distinction is
`
`consistent with the fact that all the claims of the ’633 Patent use the term “probe filter
`
`information” only with regard to clusters and not nodes. See ’633 Patent at claims 1,
`
`26, 33. In contrast, all the claims of the ’121 Patent use the term “probe filtering
`
`information” in the context of nodes as opposed to clusters. See ’121 Patent at claims
`
`1, 16, 25.
`
`Accordingly, because the specification of the ’121 Patent does not describe, either
`
`expressly or inherently, the claimed “probe filtering unit” limitations, the priority date
`
`of claims 1-3, 8, 11-12, and 14-25 of the ’121 Patent is the ’121 Patent’s filing date of
`
`Oct. 15, 2004.
`
`Patents and Printed Publications Relied On
`
`D.
`Petitioners rely on the following patents and printed publications:
`
`1. Sony-1005: U.S. Pat. No. 7,698,509 (“Koster”)
`
`Koster was filed on July 13, 2004 and is prior art under 35 U.S.C. § 102(e). Koster
`
`discloses a cache-coherency architecture that is identical to what is described and
`
`
`
`7
`
`

`

`Petition for Inter Partes Review of U.S. Pat. No. 7,296,121
`
`claimed in the ’121 Patent. Koster describes a point-to-point multiprocessing
`
`architecture with a “snoop filter,” which sends requests for data to only those
`
`microprocessors having copies of the requested data. See Koster at 6:7-18, 6:57-7:14.
`
`The snoop filter uses its “shadow tag memory” to maintain a list of the
`
`microprocessor nodes storing the requested data. Id. at 6:7-18. In relation to Fig. 9
`
`(depicted below), the snoop filter 192 forwards a data Request A only to
`
`microprocessor 188, and in response, microprocessor 188 returns Response B back to
`
`the requesting microprocessor 182 through the snoop filter 192. Id. at 7:6-16. Using
`
`the snoop filter as disclosed in Koster, “relays of broadcasts for requested data and
`
`responses thereto may be reduced, thereby reducing the overall bandwidth
`
`consumption of a particular system.” Id. at 7:66-8:3.
`
`Accordingly, the “snoop filter” concept in Koster is the same as the PFU concept
`
`of the ’121 Patent.
`
`Koster, Fig. 9
`
`8
`
`
`
`
`
`

`

`Petition for Inter Partes Review of U.S. Pat. No. 7,296,121
`
`2. Sony-1006: Jeffrey Kuskin, et al., The Stanford FLASH Multiprocessor,
`PROCEEDINGS ON THE 21ST ANNUAL INTERNATIONAL SYMPOSIUM ON
`COMPUTER ARCHITECTURE, IEEE (1994) (“Kuskin”)
`
`Kuskin published in 1994 and is prior art to the ’121 Patent under 35 U.S.C.
`
`§ 102(b). Kuskin discloses a programmable FLASH microprocessor that includes a
`
`chip called MAGIC, which in turn implements a cache coherency architecture.
`
`Kuskin at 302 (“The MAGIC chip handles all communication both within the node
`
`and among nodes, using hardwired data paths for efficient data movement and a
`
`programmable processor optimized for executing protocol operations.”). Kuskin
`
`explains that in the prior art, software based cache coherency systems had “high
`
`software overhead,” whereas the MAGIC microprocessor “includes a programmable
`
`processor for flexibility,” as well as “hardwired data movement logic.” Id. at 302-303
`
`(“The MAGIC chip . . . [includes] a programmable protocol processor”). Kuskin,
`
`accordingly, discloses a computer readable medium implementing a cache coherency
`
`architecture.
`
`3. Sony-1007: S. Park et al., Verification of Cache Coherence Protocols by
`Aggregation of Distributed Transactions, Theory of Computing Systems
`31 (1998) (“Park”)
`
`Park published in 1998 and is prior art to the ’121 Patent under 35 U.S.C. § 102(b).
`
`Park includes a description of the Stanford FLASH cache coherency protocol. Park
`
`at § 4. Park describes the Stanford FLASH protocol as having a “delayed” mode for
`
`nodes requesting read/write access to a memory line. Park at 362. In the delayed
`
`mode, the requesting node issues a request to a “home” node, and the home node
`
`
`
`9
`
`

`

`Petition for Inter Partes Review of U.S. Pat. No. 7,296,121
`
`accumulates invalidation acknowledgements from other nodes having shared copies
`
`of the memory line before sending an “exclusive copy” of the memory line to the
`
`requesting node. Id. (“[I]n DELAYED mode, this grant is deferred until all the
`
`invalidation acknowledgments are received by the home.”). The “home node” in Park
`
`is the same as the PFU concept of the ’121 Patent.
`
`4. Sony-1008: U.S. Pat. No. 6,088,769 (“Luick”)
`
`Luick issued on July 11, 2000 and is prior art to the ’121 Patent under 35 U.S.C.
`
`§ 102(b). Luick discloses a cache-coherency method that is identical to the cache
`
`coherency method described and claimed by the ’121 Patent, except that Luick is
`
`implemented over a bus architecture for the processing nodes whereas the ’121 Patent
`
`is implemented over a point-to-point architecture for the processing nodes. Luick
`
`describes using a bus interconnect 124 to interconnect nodes 101 (i.e., Node 1, Node
`
`2, and Node 3), which each contain a processor 103 and a cache 107. See Luick at Fig.
`
`1 (below), 3:65-4:4. Also interconnected to the bus, is a Global Coherence Unit
`
`(“GCU”), which provide a means for maintaining cache coherence across the
`
`processor nodes. Id. at 5:14-35. When a processor 103 requests data that is not in its
`
`own cache 115, 117, the node’s cache controller 113, may send the data request over
`
`the interconnect bus 124 to the GCU 123. Id. at 7:10-16. Using a Global Coherence
`
`Table 129 within the GCU, the GCU determines which of the plurality of nodes
`
`contains the requested data. See id. at 5:14-25, 7:16-22. The GCU 123 then forwards
`
`the request to a designated responding node, and that responding node, in turn, sends
`
`
`
`10
`
`

`

`Petition for Inter Partes Review of U.S. Pat. No. 7,296,121
`
`the requested data back to the original requesting node. See id. at 7:22-41. In one
`
`embodiment, the GCU 123 requests the data from the responding node, which sends
`
`the data back to the GCU first, and the GCU then sends the data to the requesting
`
`node. See id. at 7:55-65. Accordingly, the GCU maintains cache coherency across the
`
`processers without data requests being sent to each of the plurality of processing
`
`nodes. The GCU in Luick is the same as the PFU concept of the ’121 Patent.
`
`Luick, Fig. 1
`
`
`
`5. Sony-1009: U.S. Pat. Pub. 2002/0073261 (“Kosaraju”)
`
`Kosaraju published on June 13, 2002, and is prior art to the ’121 Patent under
`
`35 U.S.C. § 102(b). Kosaraju was filed on December 13, 2000 and is also prior art to
`
`the ’121 Patent under 35 U.S.C. § 102(e) even if the Board finds that the ’121 Patent is
`
`entitled to its parent application’s filing date.
`
`Kosaraju describes interconnecting devices in a multiple processor architecture. See
`
`Kosaraju ¶¶ 0001, 0002, 0003. In particular, Kosaraju discloses that the advantages of
`
`
`
`11
`
`

`

`Petition for Inter Partes Review of U.S. Pat. No. 7,296,121
`
`using a point-to-point architecture instead of a shared bus architecture were well
`
`known in the prior art:
`
`Joining several processors in parallel increases processing capacity. . . .
`Generally, multiple parallel processors are joined together on a shared bus.
`. . . For example, a PentiumTM processor may employ the shared bus
`architecture illustrated in FIG. 1. However, a point-to point architecture,
`typically, provides a higher bandwidth than does a shared bus architecture.
`In a shared bus architecture, multiple devices all share the same bus and
`must follow an order and protocol to use the bus. In contrast, a point-to-
`point bus architecture provides an uninterrupted connection between two
`separate devices. Thus, in general, a point-to-point bus creates a higher
`bandwidth between two separate devices. A higher bandwidth can have the
`beneficial effect of yielding an increased performance from a single
`processor or group of processors.
`See Kosaraju ¶¶ 0002-0003, Figs. 1, 5. Kosaraju illustrates the shared bus architecture
`
`and point-to-point architecture in Figures 1 and 5, respectively (reproduced below).
`
`Id. ¶¶ 0002-0003, 0007, 0011, 0024.
`
`
`
`
`
`
`Kosaraju, Fig. 1
`
`
`
`Kosaraju, Fig. 5
`
`
`
`12
`
`

`

`Petition for Inter Partes Review of U.S. Pat. No. 7,296,121
`
`Statutory Grounds for Challenge
`
`E.
`Cancellation of claims 1-3, 8, 11-12, and 14-25 is requested on the following
`
`grounds:
`
`A. Koster anticipates claims 1-3, 8, 11-12, 14-16, and 25 under 35 U.S.C. § 102(e).
`
`B. Koster alone renders claims 17-18 and 24 obvious under 35 U.S.C. § 103(a).
`
`C. Koster in view of Kuskin renders claims 19-23 obvious under 35 U.S.C. § 103(a).
`
`D. Koster in view of Kuskin and Park renders claims 15 and 25 obvious under
`
`35 U.S.C. § 103(a).
`
`E. Luick in view of Kosaraju renders claims 1-3, 8, 11-12, 14-18, and 24-25 obvious
`
`under 35 U.S.C. § 103(a).
`
`F. Luick in view of Kosaraju and Kuskin renders claims 19-23 obvious under
`
`35 U.S.C. § 103(a).
`
`G. Luick in view of Kosaraju, Kuskin, and Park renders claims 15 and 25 obvious
`
`under 35 U.S.C. § 103(a).
`
`Claim Construction
`
`F.
`The claim terms should be given their “broadest reasonable construction in light
`
`of the specification.” 37 C.F.R. § 42.100(b). The ’121 Patent specification expressly
`
`defines many of the claim terms. Trintec Indus., Inc. v. Top-U.S.A. Corp., 295 F.3d 1292,
`
`1295 (Fed. Cir. 2002) (“[T]he inventor may act as his own lexicographer.”).
`
`
`
`13
`
`

`

`Petition for Inter Partes Review of U.S. Pat. No. 7,296,121
`
`1. “node” (claims 1-3, 8, 11-12, and 14-25)
`
`The AUTHORITATIVE DICTIONARY OF IEEE STANDARDS TERMS (2000) defines
`
`“node” as “an entity associated with one or more interconnected lines and optionally
`
`containing other functional units, such as cache and memory.” Sony-1010. The
`
`specification uses the term “node” consistent with this ordinary meaning. See, e.g.,
`
`’121 Patent at 6:53-56, 8:65-9:4. Accordingly, the term “node” means “an entity
`
`associated with one or more interconnected lines and optionally containing other
`
`functional units, such as cache and memory.”
`
`2. “processing node” (claims 1-3, 8, 11-12, and 14-25)
`
`The claims use both the terms “processing node” and the term “node” unmodified
`
`by the term “processor.” Id. at Claims 2, 3. The specification states that “the terms
`
`node and processor are often used interchangeably herein. However, it should be
`
`understood that according to various implementations, a node (e.g., processors 202a-
`
`202d) may comprise multiple sub-units, e.g., CPUs, memory controllers, I/O bridges,
`
`etc.” Id. at 6:53-56; see also 8:65-9:4. Thus, despite the terms “node” and “processor”
`
`being used interchangeably in the specification, the term “node” is broader, “and may
`
`correspond to one or a plurality of resources (including, for example, a processor).”
`
`Id. at 8:65-67. The specification further states that “a node comprises multiple sub-
`
`units, e.g., CPUs, memory controllers, I/O bridges, etc.” Id. at 9:2-4. Accordingly, the
`
`claim term “processing node” refers to a specific type of node, i.e., one that contains a
`
`processor.
`
`
`
`14
`
`

`

`Petition for Inter Partes Review of U.S. Pat. No. 7,296,121
`
`3. “point-to-point” (claims 1-3, 8, 11-12, and 14-25)
`
`The specification states that “[i]n a point-to-point architecture, a cluster of
`
`processors includes multiple processors directly connected to each other through point-to-
`
`point links.” Id. 4:38-40 (emphasis added). Thus, the term “point-to-point” means “a
`
`direct connection between two devices (i.e., without intermediary devices or
`
`connections).”
`
`4. “plurality of processing nodes interconnected by a first point-to-point
`architecture” (claims 1-3, 8, 11-12, 14-25)
`
`The specification states that “[i]n a point-to-point architecture, a cluster of
`
`processors includes multiple processors directly connected to each other through point-to-point
`
`links.” Id. at 4:38-40 (emphasis added). In Fig. 18, although several pairs of the
`
`processors 1802a, 1802b, 1802c, and 1802d are connected to each other through
`
`point-to-point links, not every pair of processors is connected to each other through
`
`point-to-point links (e.g., processor 1802a and 1802d). Id. at Fig. 18 (below), Claims 1,
`
`16, and 25, 26:58-27:22. Accordingly, a “plurality of processing nodes interconnected
`
`by a first point-to-point architecture” should encompass systems employing at least
`
`two processors connected to each other through point-to-point links. Therefore, the
`
`term “plurality of processing nodes interconnected by a first point-to-point
`
`architecture” should mean “a plurality of processing nodes wherein at least two
`
`processing nodes are connected to each other through point-to-point links.”
`
`
`
`15
`
`

`

`Petition for Inter Partes Review of U.S. Pat. No. 7,296,121
`
`Fig. 18 of the ’121 Patent
`
`
`
`5. “probe” (claims 1-3, 8, 11-12, 14-25)
`
`“Probe” is expressly defined as “[a] mechanism for eliciting a response from a
`
`node to maintain cache coherency in a system.” Id. at 5:45-48. For example, “any
`
`message for snooping a cache can be referred to as a probe.” Id. at 11:66-67.
`
`6. “probe filtering information” (claims 1-3, 8, 11-12, and 14-25)
`
`“Probe filter[ing] information” is expressly defined as “[a]ny criterion that can be
`
`used to reduce the number of clusters or nodes probed.” Id. at 14:50-52.
`
`7. “cache coherence controller” (claim 3)
`
`“Cache coherence controller” is expressly defined as “[a]ny mechanism or
`
`apparatus that can be used to provide communication between multiple processor
`
`clusters while maintaining cache coherence.” Id. at 7:2-5.
`
`8. “cache coherence directory” (claim 3)
`
`“Coherence directory” is defined in the specification as “[a]ny mechanism for
`
`maintaining state information associated with various memory lines.” Id. at 5:64-66.
`
`
`
`16
`
`

`

`Petition for Inter Partes Review of U.S. Pat. No. 7,296,121
`
`9. “probe filtering unit” (claims 1-3, 8, 11-12, and 14-25)
`
`The ’121 Patent explains that the “‘probe filtering unit’ or ‘PFU’ . . . is not intended
`
`to be limiting or exclusive. Rather, any device or object operable to perform the described
`
`functionalities, e.g., a cache coherency controller as described herein, is within the scope
`
`of the invention.” See ’121 Patent at 26:53-57(emphasis added). Accordingly, a probe
`
`filtering unit should be construed broadly enough to encompass a cache coherency
`
`controller. See, e.g., id. at claim 3, 27:6-7 (“PFU 1830 may comprise a cache coherence
`
`controller”). In addition, the claims of the ’121 Patent specify which “filtering”
`
`functions are performed by the “probe filtering unit” with respect to that particular
`
`claim. See, e.g., ’121 Patent at claims 1, 16, 25. For example, claim 1 of the ’121 Patent
`
`requires that the probe filtering unit, inter alia, be operable to “receive probes
`
`corresponding to memory lines from the processing nodes and to transmit the probes
`
`only to selected ones of the processing nodes.” Accordingly, the term “probe filtering
`
`unit” means “a device or object operable to perform the claimed functionalities.”
`
`10. “accumulate responses to each probe” (claim 15) and “accumulating
`probe responses” (claim 25)
`
`The use of the plural term “responses” in the claims of the ’121 Patent includes the
`
`singular use of the term, i.e., where there is only one response. See, e.g., ’121 Patent at
`
`claims 11 and 12. For example, claim 11 recites a “first number of responses” and
`
`claim 12 further requires that the “first number is one.” Accordingly, even though
`
`claims 15 recites “accumulate responses,” this term should be interpreted under the
`
`
`
`17
`
`

`

`Petition for Inter Partes Review of U.S. Pat. No. 7,296,121
`
`broadest reasonable construction standard to encompass a system that “accumulates”
`
`only a single response. Similarly, even though claim 25 recites “accumulating probe
`
`responses,” this term should be interpreted under the broadest reasonable
`
`construction standard to encompass a method having the step of “accumulating” only
`
`a single response. Indeed, the specification of the ’121 Patent even uses the phrase
`
`“accumulates the response.” ’121 Patent at 9:38-39. Therefore, the term “accumulate
`
`responses to each probe” (claim 15) means “accumulate one or more responses to
`
`each probe.” Similarly, the term “accumulating probe responses” (claim 25) means
`
`“accumulating one or more probe responses.”
`
`11. “application-specific integrated circuit” (claim 18)
`
`An application-specific integrated circuit (“ASIC”) is “an IC [(‘integrated circuit’)]
`
`designed for a particular application.” See Jeffrey L. Hilbert, APPLICATIO