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`Petition for Inter Partes Review of 
`U.S. Pat. No. 7,296,121
`IPR2015‐00158
`EXHIBIT
`Sony‐
`
`

`
`Page 57
`
`Todd Green
`Nate McFadden
`Andre Cuello
`Alisa Andreola
`
`AC(/uiring l!Clitor:
`Development Editor:
`Project Manager:
`Designer:
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`Library of Congress Cataloging-in-Publication Data
`Sass, Ronald (Ronald R.)
`Embedded systems design with platform FPGAs: Principles and Practices I Ronald Sass.
`p.cm.
`Includes bibliographical references.
`ISBN 978-0-12-374333-6
`1. Embedded computer systems. 2. Field programmable gate arrays. I. Title.
`TK7895.E42S27 2010
`004.16-<:lc22
`
`2010010632
`
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`I .
`S b. f'
`ELSEVIER
`BOOK AID
`' a
`I e OUI1C at1011
`Intcrnation.•l
`
`

`
`58 Chapter 2 THE TARGET
`
`·,.
`' •
`
`1 I 1 I'
`
`r
`
`hardware. Over time, it was recognized that the descriptions could
`be used to simulate hardware circuits on a general-purpose pro(cid:173)
`cessor. This process of translating an HDL source into a form
`suitable for a general-purpose processor to mimic the hardware
`described is called simulation. Simulation has proven to be an
`extremely useful tool for developing hardware and verifying the
`functionality before physically manufacturing the hardware. It was
`only later that people began to synthesize hardware, automatically
`generating the logic configuration for the specified device from the
`hardware description language.
`Unfortunately, while simulation provided a rich set of con(cid:173)
`structs to help the designer test and analyze the design, many of
`these constructs extend beyond what is physically implementable
`within hardware (on the FPGA) or synthesize inefficiently into the
`FPGA resources. As a result, only a subset of hardware descrip(cid:173)
`tion languages can be used to synthesize designs to hardware. The
`objective of this section is to present two ofth_e more popular hard(cid:173)
`ware description languages, VHDL and Verilog. It is arguable to
`which is better suited !for FPGA design; both are presented here for
`completeness, but it is left to the readers to decide which (if any)
`is best suited for their needs. We will focus on VHDL throughout
`the remainder of this book as it becomes redundant to give two
`examples, one in VHDL and one in Verilog, for every concept. That
`being said, we will also focus within this section on synthesizable
`HDL and how it maps to the previous section's components.
`
`2.4.1 . VHDL
`VHDL, which stands for VHSIC1 Hardware Description Language,
`describes digital circuits. In simulation, VHDL source files are ana(cid:173)
`lyzed and a description of the behavior is expressed in the form
`of a netlist. A netlist is a computer representation of a collection
`of logic units and how they are to be connected. The logic units
`are typically AND/OR/NOT gates or some set of primitives that
`makes sense for the target (4-LUTs, for example). The behavior
`of the circuit is exercised by providing a sequence of inputs. The
`inputs, called test vectors, can be created manually or by writing a
`program/script that generates them. The component that is gen(cid:173)
`erating test vectors and driving the device under test is typically
`called a test bench.
`Synthesizable VHDL
`In VHDL, there are two major styles or forms ofwriting hard(cid:173)
`ware descriptions. Both styles are valid VHDL codes; however, they
`
`1 Very high-speed integrated circuit.
`
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