Renée E. Rothauge, OSB #903712
`ReneeRothauge@markowitzherbold.com
`MARKOWITZ HERBOLD PC
`Suite 3000, Pacwest Center
`1211 SW Fifth Avenue
`Portland, OR 97204-3730
`Telephone: (503) 295-3085
`Fax: (503) 323-9105
`
`Michael J. Summersgill (pro hac vice)
`Jordan L. Hirsch (pro hac vice)
`Sean K. Thompson (pro hac vice)
`WILMER HALE LLP
`60 State Street
`Boston, MA 02109
`(617) 526-6000
`
`Grant K. Rowan (pro hac vice)
`WILMER HALE LLP
`1875 Pennsylvania Avenue, NW
`Washington, DC 20006
`(202) 663-6000
`
`Arthur W. Coviello (pro hac vice)
`WILMER HALE LLP
`950 Page Mill Road
`Palo Alto, CA 94304
`(650) 663-6000
`
`Attorneys for Defendant Intel Corporation
`
`IN THE UNITED STATES DISTRICT COURT
`FOR THE DISTRICT OF OREGON
`PORTLAND DIVISION
`
`MEMORY INTEGRITY, LLC,
`
` Case No.: 3:15-cv-00262-SI
`
`Plaintiff,
`
`Defendant Intel Corporation’s
`INITIAL INVALIDITY CONTENTIONS
`
`
`
`v.
`
`INTEL CORPORATION,
`
`
`
`
`
` Defendant.
`
`INTEL’S INITIAL INVALIDITY CONTENTIONS
`
`
`Public Version – Confidential Information Redacted and Confidentiality Designation Removed Per Agreement
`Between the Parties
`
`

`
`Public Version - Confidential Infonnation Redacted and Confidentiality Designation Removed Per Agreement
`Between the Pruiies
`
`I.
`
`INTRODUCTION
`
`Pursuant to Pru·agraph 5(b) of the Scheduling Order (Dkt. No. 23) and the Court's Febmruy
`
`17, 2015 Order Granting in Prui Stipulated Motion to Amend Scheduling Order (Dkt. No. 47),
`
`Defendant Intel Corporation ("Intel") hereby provides its Initial Invalidity Contentions
`
`("Invalidity Contentions") with respect to the claims of U.S. Patent Nos. 7,296,12 1 ("the ' 121
`
`Patent"); 7,107,409 ("the '409 Patent"); 7,103,636 ("the ' 636 Patent"); 8,572,206 ("the '206 Patent");
`
`and 8,898,254 ("the '254 Patent") (collectively the "Asse1ied Patents") identified by Plaintiff
`
`Mem01y Integrity, LLC ("MI" or "Mem01y Integrity") in its Mru·ch 26, 2015 Initial Infringement
`
`Contentions ("Infi:ingement Contentions").
`
`Mem01y Integrity has asseiied the claims listed below against Intel in its Infi:ingement
`
`Contentions:
`
`•
`
`•
`
`•
`
`•
`
`•
`
`' 121 Patent: claims 1-6, 8, 11-17, 19-25;
`
`'409 Patent: claims 1-3, 6-12, 18-20, 22-23, 25-30, 34, 36-38, 42-43, 45,47-49, 51-52;
`
`'636 Patent: claims 11-18,21-31, 33-36;
`
`'206 Patent: claims 1-2, 7, 14-15, 19, 21-22, 24-32, 34-35, 37-41, 43-44; and
`
`'254 Patent: claims 1-3, 5-8.
`
`With respect to each asse1ied claim, and based on its investigation to date, Intel hereby:
`
`(a) identifies each item of prior rui that either anticipates or renders obvious each asse1i ed claim;
`
`(b) specifies whether each such item of prior rut (or combination of several of the same) anticipates
`
`each asserted claim or renders it obvious; (c) submits a chart identifying where specifically in each
`
`item of prior rui each limitation of each claim is disclosed, described, or taught in the prior rut;
`
`(d) identifies the grounds for invalidating asse1ied claims for failing to claim patentable subject
`
`matter under 35 U.S. C. § 101, or for invalidating asse1ied claims based on indefiniteness under 35
`
`U.S. C. § 112(2) or enablement or written description under 35 U.S.C. § 112(1).
`
`

`
`Public Version - Confidential Infonnation Redacted and Confidentiality Designation Removed Per Agreement
`Between the Pruiies
`
`II.
`
`RESERVATIONS
`
`Intel reserves the right to amend its Invalidity Contentions should Mem01y Integrity
`
`attempt to supplement its deficient Infringement Contentions. Mem01y Integrity served its
`
`Infringement Contentions on Mru·ch 16, 2015. By letter datedApril22, 2015, Intel inf01med MI of
`
`multiple deficiencies in its Infringement Contentions. In pruiicular, runong other deficiencies,
`
`Intel inf01med MI that its Infringement Contentions were deficient because they included
`
`improper or inadequate contentions with respect to:
`
`• previously lmdisclosed products (Intel's Broadwell microprocessors) and claims
`(claims 12, 21, 23 and 35 of the '636 patent; claims 6, 8, and 52 of the '409 patent;
`claims 4-6, 13 of the '121 patent; and claims 21-22, 24-29 of the '206 patent);
`
`• Westmere, Ivy Bridge, and Broadwell microprocessors;
`
`• doctrine of equivalents; and
`
`•
`
`certain claim limitations for which MI cited no evidence whatsoever.
`
`MI has done nothing to address these deficiencies. Intel reserves its right to runend its Invalidity
`
`Contentions should MI attempt to serve amended Infringement Contentions.
`
`MI has also failed to complete its production of documents in response to Intel's October 8,
`
`2014 First Set of Requests for the Production of Documents (Nos. 1-70). Intel reserves its right to
`
`revise, supplement, or amend its Invalidity Contentions based on subsequently produced
`
`documents and infonnation.
`
`Intel fmi her reserves its right to revise, supplement, or amend its Invalidity Contentions to
`
`reflect any additional inf01mation leamed during the course of fact and expert discove1y . In
`
`prui iculru·, on Januruy 28, 2015 and Januruy 22, 2015 respectively, Intel subpoenaed documents
`
`from Oracle Corporation and Intemational Business Machines Corporation regru·ding prior rui
`
`systems-celiain Sun Server products and IBM's POWER4 microprocessor-that Intel believes
`
`show that ce1iain of the asselied claims ru·e invalid, but Intel has not yet received all requested
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`Between the Pruiies
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`documents from either company. Intel specifically reserves its right to amend its Invalidity
`
`Contentions to add additional details regarding this prior rui.
`
`The references discussed in the claim chruis attached hereto may disclose the elements of
`
`the asserted claims explicitly, implicitly, or inherently, or they may be relied upon to show the
`
`state of the rui in the relevant time frame.
`
`Intel's claim chruis cite particulru· teachings and disclosmes of the prior rui as applied to
`
`features of the assetied claims. However, persons having ordinaty skill in the ati generally may
`
`view an item of prior rut in the context of other publications, literatme, products, and
`
`understanding. As such, the cited p01iions ru·e only exrunples, and Intel reserves its right to rely on
`
`unci ted p01i ions of the prior rui references and on other publications and expeti testimony as aids
`
`in understanding and interpreting the cited p01iions, as providing context thereto, and as additional
`
`evidence that the prior rui discloses a claim limitation. Intel fmi her reserves its right to rely on
`
`unci ted p01iions of the prior rut references, other publications, and testimony to establish bases for
`
`combinations of cetiain cited references that render the asserted claims obvious.
`
`For pmposes of these Invalidity Contentions, Intel identifies prior rui references and
`
`provides element-by-element claim chruis based on Ml's infringement allegations as set forth in its
`
`Infringement Contentions. To the extent MI adopts different positions, Intel reserves its right to
`
`revise, supplement, or amend its Invalidity Contentions.
`
`Nothing stated herein shall be treated as an admission or suggestion that Intel agrees with
`
`Ml's appru·ent intetpretation of the claims. Moreover, nothing in these Contentions shall be treated
`
`as an admission that any of Intel's accused technology meets any limitations of the claims.
`
`Finally, references to the preamble of a claim in these Contentions shall not be treated as an
`
`admission that the prerunble is a limitation of a claim.
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`Between the Pruiies
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`III.
`
`Invalidity Contentions
`
`A.
`
`The '121 Patent
`
`1.
`
`Identification of Prior Art
`
`The references set f01ih in the table below, in Section III.F Obviousness of the Claimed
`
`Concepts, an d in Exhibit 1, anticipate and/or render obvious the assetied claims of the '121 patent.
`
`Exhibit Name
`No.
`
`C-1
`
`C-2
`C-3
`C-4
`C-5
`C-6
`C-7
`C-8
`
`David Chaiken et al., Direct01y-Based Cache Coherence in Large-Scale
`Multiprocessors, COMPUTER, Jlme 1990 ("Chaiken")
`U.S. Pat. No. 6,088,769 to Luick ("Luick '769")
`U.S. Pat. No. 6,598,123 to Anderson ("Anderson")
`U.S. Pat. No. 6,810,467 to Khare ("Khare '467")
`U.S. Pat. App. No. 2002/0053004 Alto Pong ("Pong ")
`Intel 870 Chipset and related references ("870 Chipset an d its related publications")
`U.S. Pat. No. 7,698,509 to Koster ("Koster '509")
`Daniel Lenoski et al. , The Direct01y-Based Cache Coherence Protocol for the DASH
`Multiprocessor, 17th Annual Intemational Symposium on Computer Architecture
`(1990) ("Lenoski")
`
`2.
`
`Disclosure of Invalidity Due to Anticipation
`
`Subject to the reservation of rights above an d based on Intel's present understanding of the
`
`assetied claims of the Assetied Patents an d Mem01y Integrity's appru·ent constmction of the
`
`assetied claims as applied in Memory Integrity's infringement contentions, the prior ati references
`
`identified in Exhibits C-1 - C-8 anticipate the asserted claims, at least under Mem01y Integrity's
`
`apparent infringement an d claim constmction theories. The chruis identify where each element of
`
`each assetied claim can be found in each item of prior rui.
`
`3.
`
`Disclosure of Invalidity Due to Obviousness
`
`To the extent a fmder of fact detennines that a limitation of a given claim was not disclosed
`
`by one of the references identified above, those claims ru·e nevetiheless unpatentable as obvious
`
`because the Asserted Claims contain nothing that goes beyond ordinaty innovation. To the extent
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`not anticipated, no asse1ied claim goes beyond combining known elements to achieve predictable
`
`results or does more than choose between clear altem atives known to those of skill in the rui.
`
`To the extent that Mem01y Integrity contends that Chaiken, Luick '769, Anderson, Khare
`
`'467, Pong, 870 Chipset and its related publications, Koster '509, and/or Lenoski does not disclose
`
`or suggest a point-to-point architecture, any of these references can be combined with each other
`
`and/or any of those disclosed or cited in Section III.F.1 ("Point-to-Point Architecture"). It would
`
`have been obvious for one of ordinruy skill in the rui at the time of the alleged invention of the
`
`Asse1ied Claims to have made such combination(s) for the reasons set forth in Section III.F.1
`
`("Point-to-Point Architecture"), Exhibits C-1 to C-8, and/or elsewhere in Intel 's Invalidity
`
`Contentions.
`
`To the extent that Mem01y Integrity contends that Chaiken, Luick '769, Anderson, Khare
`
`'467, Pong, 870 Chipset and its related publications, Koster '509, and/or Lenoski does not disclose
`
`or suggest one or more clusters, any of these references can be combined with each other and/or
`
`any of those disclosed or cited in Section III.F.4 ("Clusters"). It would have been obvious for one
`
`of ordinruy skill in the rui at the time of the alleged invention of the Asse1ied Claims to have made
`
`such combination(s) for the reasons set forth in Section III.F.4 ("Clusters"), Exhibits C-1 to C-8,
`
`and/or elsewhere in Intel's Invalidity Contentions.
`
`To the extent that Mem01y Integrity contends that Chaiken, Luick '769, Anderson, Khare
`
`'467, Pong, 870 Chipset and its related publications, Koster '509, and/or Lenoski does not disclose
`
`or suggest a cache coherence controller and/or interconnection controller, any of these references
`
`can be combined with each other and/or any of those disclosed or cited in Section III.F.7 ("Cache
`
`Coherence Controller" and "Interconnection Controller"). It would have been obvious for one of
`
`ordinruy skill in the rut at the time of the alleged invention of the Asse1ied Claims to have made
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`such combination(s) for the reasons set forth in Section III.F.7 ("Cache Coherence Controller" and
`
`"Interconnection Contr·oller"), Exhibits C-1 to C-8, and/or elsewhere in Intel's Invalidity
`
`Contentions.
`
`To the extent that Mem01y Integrity contends that Chaiken, Luick '769, Anderson, Khare
`
`'467, Pong, 870 Chipset and its related publications, Koster '509, and/or Lenoski does not disclose
`
`or suggest an integrated circuit comprising a probe filtering unit or interconnection controller,
`
`computer-readable medium having data stm ctures stored therein representative of a probe filtering
`
`unit or interconnection contr·oller, data structures comprising a simulatable representation of a
`
`probe filtering lmit or interconnection controller, a simulatable representation comprising a netlist,
`
`data structures comprising a code description of a probe filtering unit or interconnection contr·oller,
`
`code description con esponding to a hru·dwru·e description language, and/or a set of semiconductor
`
`processing masks representative of at least a portion of a probe filtering unit or interconnection
`
`controller, any of these references can be combined with each other and/or any of those disclosed
`
`or cited in Section III.F.14 ("Integrated circuit, computer-readable medium, semiconductor
`
`processing masks"). It would have been obvious for one of ordinruy skill in the rui at the time of
`
`the alleged invention of the Asserted Claims to have made such combination(s) for the reasons set
`
`f01ih in Section III.F.14 ("Integrated circuit, computer-readable medium, semiconductor
`
`processing masks"), Exhibits C-1 to C-8, and/or elsewhere in Intel's Invalidity Contentions.
`
`To the extent that Mem01y Integrity contends that Chaiken, Luick '769, Anderson, Khare
`
`'467, Pong, 870 Chipset and its related publications, Koster '509, and/or Lenoski does not disclose
`
`or suggest a probe filtering unit con esponding to an additional node interconnected with the
`
`processing nodes, an additional node comprises a cache coherence controller, and/or a cache
`
`coherence contr·oller comprises the probe filtering unit, any of these references can be combined
`
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`with each other and/or any ofthose disclosed or cited in Section III.F.15 ("Probe filtering unit
`
`con esponds to an additional node interconnected with the processing nodes, additional node
`
`comprises a cache coherence controller, cache coherence controller comprises the probe filtering
`
`unit"). It would have been obvious for one of ordinruy skill in the rut at the time of the alleged
`
`invention of the Asse1ied Claims to have made such combination(s) for the reasons set f01ih in
`
`Section III.F.15 ("Probe filtering lmit con esponds to an additional node interconnected with the
`
`processing nodes, additional node comprises a cache coherence controller, cache coherence
`
`controller comprises the probe filtering unit"), Exhibits C-1 to C-8, and/or elsewhere in Intel's
`
`Invalidity Contentions.
`
`To the extent that Mem01y Integrity contends that Chaiken, Luick '769, Anderson, Khare
`
`'467, Pong, 870 Chipset and its related publications, Koster '509, and/or Lenoski does not disclose
`
`or suggest probe filtering infonnation comprising a cache coherence direct01y which includes
`
`entries con esponding to mem01y lines stored in the selected cache memories, any of these
`
`references can be combined with each other and/or any of those disclosed or cited in Section
`
`III.F .16 ("Probe filtering inf01m ation comprises a cache coherence direct01y which includes
`
`entries con esponding to mem01y lines stored in the selected cache memories"). It would have
`
`been obvious for one of ordinruy skill in the rui at the time of the alleged invention of the Asse1ied
`
`Claims to have made such combination( s) for the reasons set forth in Section III.F .16 ("Probe
`
`filtering inf01m ation comprises a cache coherence direct01y which includes entries con esponding
`
`to mem01y lines stored in the selected cache memories"), Exhibits C-1 to C-8, and/or elsewhere in
`
`Intel's Invalidity Contentions.
`
`To the extent that Mem01y Integrity contends that Chaiken, Luick '769, Anderson, Khare
`
`'467, Pong, 870 Chipset and its related publications, Koster '509, and/or Lenoski does not disclose
`
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`or suggest that each of the processing nodes is operable to u·ansmit the probes only to the probe
`
`filtering lmit, any of these references can be combined with each other and/or any of those
`
`disclosed or cited in Section III.F .17 ("Each of the processing nodes is operable to u·ansmit the
`
`probes only to the probe filtering unit"). It would have been obvious for one of ordinruy skill in the
`
`rut at the time of the alleged invention of the Asse1ted Claims to have made such combination(s)
`
`for the reasons set f01th in Section III.F .17 ("Each of the processing nodes is operable to u·ansmit
`
`the probes only to the probe filtering unit"), Exhibits C-1 to C-8, and/or elsewhere in Intel's
`
`Invalidity Contentions.
`
`To the extent that Mem01y Integrity contends that Chaiken, Luick '769, Anderson, Khare
`
`'467, Pong, 870 Chipset and its related publications, Koster '509, and/or Lenoski does not disclose
`
`or suggest each of the processing nodes programmed to complete a mem01y u·ansaction after
`
`receiving a first number of responses to a first probe, the first number being fewer than the number
`
`of processing nodes; a probe filtering unit having temporruy storage associated therewith for
`
`holding read response data from one of the cache memories, where the first number is one; and/or
`
`a probe filtering unit operable to f01ward read response data to a requesting node before
`
`accumulating all probe responses associated with the mem01y u·ansaction, where the first number
`
`is two, any of these references can be combined with each other and/or any of those disclosed or
`
`cited in Section III.F .18 ("Each of the processing nodes is programmed to complete a mem01y
`
`u·ansaction after receiving a first number of responses to a first probe, the first number being fewer
`
`than the number of processing nodes; Probe filtering unit having temporruy storage associated
`
`therewith for holding read response data from one of the cache memories, where the first number is
`
`one; Probe filtering unit operable to f01ward read response data to a requesting node before
`
`accumulating all probe responses associated with the mem01y u·ansaction, where the first number
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`is two"). It would have been obvious for one of ordinruy skill in the rui at the time of the alleged
`
`invention of the Assetied Claims to have made such combination(s) for the reasons set f01ih in
`
`Section III.F.18 ("Each of the processing nodes is progrrunmed to complete a mem01y transaction
`
`after receiving a first number of responses to a first probe, the first number being fewer than the
`
`number of processing nodes; Probe filtering unit having temporaty storage associated therewith
`
`for holding read response data from one of the cache memories, where the first number is one;
`
`Probe filtering lmit operable to fotwru·d read response data to a requesting node before
`
`accumulating all probe responses associated with the mem01y transaction, where the first number
`
`is two"), Exhibits C-1 to C-8, and/or elsewhere in Intel's Invalidity Contentions.
`
`To the extent that Mem01y Integrity contends that Chaiken, Luick '769, Anderson, Khare
`
`'467, Pong, 870 Chipset and its related publications, Koster '509, and/or Lenoski does not disclose
`
`or suggest a probe filtering unit operable to modify the probes such that the selected processing
`
`nodes transmit responses to the probes to the probe filtering unit, any of these references can be
`
`combined with each other and/or any of those disclosed or cited in Section III.F.19 ("Probe
`
`filtering lmit operable to modify the probes such that the selected processing nodes transmit
`
`responses to the probes to the probe filtering unit"). It would have been obvious for one of
`
`ordinaty skill in the ati at the time of the alleged invention of the Assetied Claims to have made
`
`such combination(s) for the reasons set forth in Section III.F.19 ("Probe filtering unit operable to
`
`modify the probes such that the selected processing nodes transmit responses to the probes to the
`
`probe filtering unit"), Exhibits C-1 to C-8, and/or elsewhere in Intel's Invalidity Contentions.
`
`To the extent that Mem01y Integ!'ity contends that Chaiken, Luick '769, Anderson, Khare
`
`'467, Pong, 870 Chipset and its related publications, Koster '509, and/or Lenoski does not disclose
`
`or suggest a probe filtering unit operable to accumulate responses to each probe, and respond to
`
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`requesting nodes in accordance with the accumulated responses, any of these references can be
`
`combined with each other and/or any of those disclosed or cited in Section III.F.20 ("Probe
`
`filtering lmit operable to accumulate responses to each probe, and respond to requesting nodes in
`
`accordance with the accumulated responses"). It would have been obvious for one of ordina1y
`
`skill in the rui at the time of the alleged invention of the Assetied Claims to have made such
`
`combination(s) for the reasons set forth in Section III.F.20 ("Probe filtering unit operable to
`
`accumulate responses to each probe, and respond to requesting nodes in accordance with the
`
`accumulated responses"), Exhibits C-1 to C-8, and/or elsewhere in Intel's Invalidity Contentions.
`
`To the extent that Mem01y Integrity contends that Chaiken, Luick '769, Anderson, Khare
`
`'467, Pong, 870 Chipset and its related publications, Koster '509, and/or Lenoski does not disclose
`
`or suggest any other prui iculru· claimed feature(s), any of these references can be combined with
`
`any of the references cited in Exhibits C-1 to C-8 as teaching the pruiicular claimed feature(s). It
`
`would have been obvious for one of ordinruy skill in the rut at the time of the alleged invention of
`
`the Assetied Claims to have made such combination(s) for the reasons set f01i h in Exhibits C-1 to
`
`C-8 and/or elsewhere in Intel's Invalidity Contentions.
`
`B.
`
`The ' 409 Patent
`
`1.
`
`Identification of Prior Art
`
`The references set f01i h in the table below, in Section III.F Obviousness of the Claimed
`
`Concepts, and in Exhibit 1, anticipate and/or render obvious the asseti ed claims of the '409 patent.
`
`Exhibit Name
`No.
`
`A-1
`A-2
`A-3
`A-4
`A-5
`A-6
`
`U.S. Pat. No. 6,055,610 to Smith et al. ("Smith ' 610")
`U.S. Pat. No. 6,799,217 to Wilson et al. ("Wilson '217")
`U.S. Pat. No. 6,631,447 to Morioka et al. ("Morioka '447")
`U.S. Pat. No. 6,081,874 to Cru-penter ("Cru-penter ' 874")
`U.S. Pat. No. 6,516,391 to Tsushima et al. ("Tsushima")
`U.S. Pat. No. 6,338,122 to Baumgrutner ("Baumgrutner")
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`A -7
`A-8
`A -9
`
`IBM POWER4 Processor system and related references ("IBM POWER4")
`U.S. Pat. No. 6,615,322 to Arimilli ("Arimilli")
`Slmfire server system and related references ("Slmfire")
`
`2.
`
`Disclosure of Invalidity Due to Anticipation
`
`Subject to the reservation of rights above an d based on Intel's present understanding of the
`
`asse1ted claims of the Asse1ted Patents an d Mem01y Integrity's appar ent constm ction of the
`
`asse1ted claims as applied in Memory Integrity's infringement contentions, th e prior rut references
`
`identified in Exhibits A-1 - A-9 anticipate the asse1ted claims, at least lmder Mem01y Integrity's
`
`appru·ent infringement an d claim constm ction theories. The chruts identify where each element of
`
`each asse1ted claim can be found in each item of prior rut.
`
`3.
`
`Disclosure of Invalidity Due to Obviousness
`
`To the extent a fmder of fact determines that a limitation of a given claim was not disclosed
`
`by one of the references identified above, th ose claims ru·e neve1theless unpatentable as obvious
`
`because the Asselied Claims contain nothing that goes beyond ordinmy innovation. To the extent
`
`not anticipated, no asse1ted claim goes beyond combining known elements to achieve predictable
`
`results or does more than choose between clear altem atives known to those of skill in the rut.
`
`To th e extent thatMem 01y Integrity contends th at Smith '610; IBM Power 4; Wilson '217;
`
`Morioka '447; Cmpenter '874; Tsushima; Baumgminer; IBM POWER4; Arimilli; and/or Slmfire
`
`does not disclose or suggest a "point to point architecture," any of these references can be
`
`combined with each other and/or any of those disclosed or cited in Section III.F. 1 ("Point-to-Point
`
`Architecture"). It would have been obvious for one of ordinruy skill in the rut at the time of the
`
`alleged invention of th e Asse1ted Claims to have made such combination(s) for the reasons set
`
`f01th in Section III.F.1 ("Point-to-Point Architecture"), Exhibits A-1 to A-9, and/or elsewhere in
`
`Intel's Invalidity Contentions.
`
`- 11 -
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`Public Version - Confidential Infonnation Redacted and Confidentiality Designation Removed Per Agreement
`Between the Pruiies
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`To the extent thatMem01y Integrity contends that Smith '610; IBM Power 4; Wilson '217;
`
`Morioka '447; Catpenter '874; Tsushima; Baumgruiner; IBM POWER4; Arimilli; and/or SunFire
`
`does not disclose or suggest "speculative" "probing," any of these references can be combined
`
`with any of those disclosed or cited in Section III.F.2 ("Speculative" "Probing"). It would have
`
`been obvious for one of ordinruy skill in the rui at the time of the alleged invention of the Assetied
`
`Claims to have made such combination(s) for the reasons set forth in Section III.F.2
`
`("Speculative" "Probing"), Exhibits A-1 to A-9, and/or elsewhere in Intel's Invalidity
`
`Contentions.
`
`To the extent thatMem01y Integrity contends that Smith '610; IBM Power 4; Wilson '217;
`
`Morioka '447; Catpenter '874; Tsushima; Baumgruiner; IBM POWER4; Arimilli; and/or SunFire
`
`does not disclose or suggest "detennining if speculative probing of the local node can be
`
`perf01med," any of these references can be combined with any of those disclosed or cited in
`
`Section III.F.3 ("Detennining if Speculative Probing of the Local Node Can Be Perfonned"). It
`
`would have been obvious for one of ordinruy skill in the rut at the time of the alleged invention of
`
`the Assetied Claims to have made such combination(s) for the reasons set f01ih in Section III.F.3
`
`("Detetmining if Speculative Probing of the Local Node Can Be Perf01med"), Exhibits A-1 to
`
`A-9, and/or elsewhere in Intel's Invalidity Contentions.
`
`To the extent thatMem01y Integrity contends that Smith '610; IBM Power 4; Wilson '217;
`
`Morioka '447; Crupenter '874; Tsushima; Baumgruiner; IBM POWER4; Arimilli; and/or Slmfii·e
`
`does not disclose or suggest "clusters," any of these references can be combined with any of the
`
`disclosed or cited in Section III.F.4 ("Clusters"). It would have been obvious for one of ordinruy
`
`skill in the rui at the time of the alleged invention of the Assetied Claims to have made such
`
`- 12 -
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`Public Version - Confidential Infonnation Redacted and Confidentiality Designation Removed Per Agreement
`Between the Pruiies
`
`combination(s) for the reasons set f01ih in Section III.F.4 ("Clusters"), Exhibits A-1 to A-9, and/or
`
`elsewhere in Intel's Invalidity Contentions.
`
`To the extent thatMem01y Integrity contends that Smith '610; IBM Power 4; Wilson '217;
`
`Morioka '447; Crupenter '874; Tsushima; Baumgruiner; IBM POWER4; Arimilli; and/or SlmFire
`
`does not disclose or suggest a "mem01y controller," any of these references can be combined with
`
`any of those disclosed or cited in Section III.F.5 ("Mem01y Controller"). It would have been
`
`obvious for one of ordinruy skill in the ati at the time of the alleged invention of the Assetied
`
`Claims to have made such combination(s) for the reasons set forth in Section III.F.5 ("Mem01y
`
`Controller"), Exhibits A-1 to A-9, and/or elsewhere in Intel's Invalidity Contentions.
`
`To the extent thatMem01y Integrity contends that Smith '610; IBM Power 4; Wilson '217;
`
`Morioka '447; Crupenter '874; Tsushima; Baumgruiner; IBM POWER4; Arimilli; and/or SlmFire
`
`does not disclose or suggest "locking" a "mem01y line," any of these references can be combined
`
`with any of those disclosed or cited in Section III.F.6 ("Locking" a "Mem01y Line"). It would
`
`have been obvious for one of ordinruy skill in the rui at the time of the alleged invention of the
`
`Assetied Claims to have made such combination(s) for the reasons set f01ih in Section III.F.6
`
`("Locking" a "Mem01y Line"), Exhibits A-1 to A-9, and/or elsewhere in Intel's Invalidity
`
`Contentions.
`
`To the extent thatMem01y Integrity contends that Smith '610; IBM Power 4; Wilson '217;
`
`Morioka '447; Crupenter '874; Tsushima; Baumgruiner; IBM POWER4; Arimilli; and/or SlmFire
`
`does not disclose or suggest a "cache coherence controller" and/or an "interconnection controller,"
`
`any of these references can be combined with any of the disclosed or cited in Section III.F.7
`
`("Cache Coherence Controller" and "Interconnection Controller"). It would have been obvious
`
`for one of ordinruy skill in the rui at the time of the alleged invention of the Assetied Claims to
`
`- 13-
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`

`
`Public Version - Confidential Infonnation Redacted and Confidentiality Designation Removed Per Agreement
`Between the Pruiies
`
`have made such combination(s) for the reasons set f01ih in Section III.F.7 ("Cache Coherence
`
`Controller" and "Interconnection Contr·oller"), Exhibits A-1 to A-9, and/or elsewhere in Intel's
`
`Invalidity Contentions.
`
`To the extent thatMem01y Integrity contends that Smith '610; IBM Power 4; Wilson '217;
`
`Morioka '447; Catpenter '874; Tsushima; Baumgruiner; IBM POWER4; Arimilli; and/or SunFire
`
`does not disclose or suggest a "cache coherence controller" "constm cted to act as an aggregate
`
`remote cache," any of these references can be combined with any of the disclosed or cited in
`
`Section III.F.8 ("Cache Coherence Contr·oller" and "Constructed to Act As An Aggregate Remote
`
`Cache"). It would have been obvious for one of ordinruy skill in the rui at the time of the alleged
`
`invention of the Assetied Claims to have made such combination(s) for the reasons set f01ih in
`
`Section III.F.8 ("Cache Coherence Contr·oller" and "Constructed to Act As An Aggregate Remote
`
`Cache"), Exhibits A-1 to A-9, and/or elsewhere in Intel's Invalidity Contentions.
`
`To the extent thatMem01y Integrity contends that Smith '610; IBM Power 4; Wilson '217;
`
`Morioka '447; Crupenter '874; Tsushima; Baumgruiner; IBM POWER4; Arimilli; and/or SlmFil·e
`
`does not disclose or suggest a "cache coherence controller" "constmcted to act as a probing agent
`
`pail·," any of these references can be combined with any of the disclosed or cited in Section III.F.9
`
`("Cache Coherence Contr·oller" and "Constmcted to Act As A Probing Agent Pail·"). It would
`
`have been obvious for one of ordinruy skill in the rui at the time of the alleged invention of the
`
`Assetied Claims to have made such combination(s) for the reasons set forth in Section III.F.9
`
`("Cache Coherence Contr·oller" and "Constructed to Act As A Probing Agent Pail·"), Exhibits A -1
`
`to A-9, and/or elsewhere in Intel's Invalidity Contentions.
`
`To the extent thatMem01y Integrity contends that Smith '610; IBM Power 4; Wilson '217;
`
`Morioka '447; Crupenter '874; Tsushima; Baumgruiner; IBM POWER4; Arimilli; and/or SlmFil·e
`
`- 14 -
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`
`Public Version - Confidential Infonnation Redacted and Confidentiality Designation Removed Per Agreement
`Between the Pruiies
`
`does not disclose or suggest a "cache coherence controller" "constm cted to act as a remote
`
`mem01y," any of these references can be combined with any of those disclosed or cited in Section
`
`III.F.1 0 ("Cache Coherence Controller" and "Constm cted to Act As A Remote Mem01y"). It
`
`would have been obvious for one of ordinruy skill in the rut at the time of the alleged invention of
`
`the Assetied Claims to have made such combina