Patent No. 7,296,121
`IPR2015-00158
`
`
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`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`SONY CORPORATION; SONY ELECTRONICS INC.;
`SONY MOBILE COMMUNICATIONS AB; AND
`SONY MOBILE COMMUNICATIONS (USA) INC.
`Petitioners
`
`v.
`
`MEMORY INTEGRITY, LLC
`Patent Owner
`
`U.S. Patent No. 7,296,121
`
`
`
`Inter Partes Review Case No. 2015-00158
`
`
`
`MEMORY INTEGRITY, LLC’S PATENT OWNER
`RESPONSE PURSUANT TO 37 CFR § 42.120(a)
`
`
`
`
`
`
`IPR2015-00158
`
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`SONY CORPORATION; SONY ELECTRONICS INC.;
`SONY MOBILE COMMUNICATIONS AB; AND
`SONY MOBILE COMMUNICATIONS (USA) INC.
`Petitioners
`
`v.
`
`MEMORY INTEGRITY, LLC
`Patent Owner
`
`U.S. Patent No. 7,296,121
`
`
`
`Inter Partes Review Case No. 2015-00158
`
`
`
`MEMORY INTEGRITY, LLC’S PATENT OWNER
`RESPONSE PURSUANT TO 37 CFR § 42.120(a)
`
`
`
`
`
`
`
`Patent No. 7,296,121
`IPR2015-00158
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`TABLE OF CONTENTS
`
`I.
`
`INTRODUCTION ........................................................................................... 1
`
`II MEMORY INTEGRITY’S CLAIM CONSTRUCTIONS ............................. 1
`
`A.
`
`“states” ..................................................................................................... 1
`
`III. PETITIONERS HAVE NOT MET THEIR BURDEN TO SHOW
`UNPATENTABILITY OF THE INSTITUTED CLAIMS........................... 12
`
`A. Petitioners Failed To Demonstrate That Claim 24 Is Obvious Over
`Koster Alone .......................................................................................... 13
`
`1. Koster Does Not Disclose “Probe Filtering Information
`Representative Of States Associated With Selected Ones Of
`The Cache Memories” As Required By Claim 24 ........................ 13
`
`B. Petitioners Failed To Demonstrate That Claims 19-23 Are Obvious
`Over Koster In View of Kuskin ............................................................ 16
`
`1. The Petition Fails To Demonstrate That The Combination Of
`Koster And Kuskin Teaches The “Probe Filtering Information
`Representative Of States” Limitation Of Claims 19-23 ............... 16
`
`IV. CONCLUSION .............................................................................................. 16
`
`
`
`i
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`Patent No. 7,296,121
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`EXHIBIT LIST
`
`
`
`Exhibit No.
`Memory Integrity-2001
`
`Memory Integrity-2002
`
`Memory Integrity-2003
`
`Description
`Plaintiff Memory Integrity, LLC’s Initial Identification
`of Asserted Claims And Accused Products, served on
`Petitioners in Memory Integrity LLC v. Amazon.com
`Inc., et al., Nos. 1:13-cv-01795, -01796, -01802,
`-01808 (D. Del. served Oct. 13, 2014)
`Excerpts from D. E. Culler, J. P. Singh, and A. Gupta
`PARALLEL COMPUTER ARCHITECTURE, pp. 279-280
`(1999)
`Sorin et al. , “Specifying and Verifying a Broadcast and
`a Multicast Snooping Cache Coherence Protocol,”
`IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED
`SYSTEMS, Vol. 13, No. 6, pp. 1-23(June 2002)
`Excerpts from Merriam-Webster’s Collegiate
`Dictionary (10th ed. 1999)
`Excerpts from David A. Patterson, et al., COMPUTER
`ORGANIZATION AND DESIGN (3d ed. 2005)
`Memory Integrity-2006 U.S. Patent Application No. 10/288,347
`Memory Integrity-2007 U.S. Patent No. 7,107,408 to Glasco
`Memory Integrity-2008 U.S. Patent No. 7,107,409 to Glasco
`Memory Integrity-2009 Not Used
`Memory Integrity-2010
`Sorin, et al., A PRIMER ON MEMORY CONSISTENCY AND
`CACHE COHERENCE (2011)
`Excerpts from D. E. Culler, J. P. Singh, and A. Gupta
`PARALLEL COMPUTER ARCHITECTURE, pp. 302, 307-310
`(1999)
`Excerpts from Microsoft Computer Dictionary (1999)
`Excerpts from Modern Dictionary of Electronics (7th
`ed. 1999)
`Excerpts from Merriam-Webster’s Collegiate
`Dictionary (10th ed. 1999)
`
`Memory Integrity-2004
`
`Memory Integrity-2005
`
`Memory Integrity-2011
`
`Memory Integrity-2012
`Memory Integrity-2013
`
`Memory Integrity-2014
`
`
`
`ii
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`Patent No. 7,296,121
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`Description
`Excerpts from Laughton et al., ELECTRICAL ENGINEER’S
`REFERENCE BOOK, pp. 15/3 (16th ed. 2003)
`Memory Integrity-2016 Declaration of Vojin G. Oklobdzija, PhD in Support of
`Patent Owner’s Responses
`Curriculum Vitae of Vojin G. Oklobdzija, PhD
`
`Exhibit No.
`Memory Integrity-2015
`
`Memory Integrity-2017
`
`
`
`iii
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`
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`TABLE OF AUTHORITIES
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`Patent No. 7,296,121
`IPR2015-00158
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`Page(s)
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`Cases
`Microsoft Corp. v. Proxyconn, Inc.,
`789 F.3d 1292 (Fed. Cir. 2015) ........................................................................ 2, 3
`
`Statutes
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`35 U.S.C. § 316(e) ................................................................................................... 12
`
`Other Authorities
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`37 C.F.R. § 42.1(d) .................................................................................................. 12
`
`Decision on Institution of Inter Partes Review ......................................................... 1
`
`Jeffrey Kuskin, et al., The Stanford FLASH Microprocessor, PROCEEDINGS
`OF THE 21ST ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER
`ARCHITECTURE, IEEE (1994) ................................................................................ 1
`
`Sorin, et al., A Primer on Memory Consistency and Cache Coherence (2011) ........ 4
`
`Sorin, et al., Specifying and Verifying a Broadcast and a Multicast Snooping
`Cache Coherence Protocol (2002) ....................................................................... 5
`
`
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`iv
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`
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`I. INTRODUCTION
`Patent Owner Memory Integrity LLC (“Memory Integrity” or “MI”) submits
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`Patent No. 7,296,121
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`this Response to the Petition for Inter Partes Review (“the Petition”) of U.S. Patent
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`No. 7,296,121 (“the ’121 patent”) filed by the Petitioners, and the Patent Trial and
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`Appeal Board (“the PTAB” or “the Board”) Decision on Institution of Inter Partes
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`Review (Paper No. 7, “Institution Decision”). The Board instituted review of
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`claims 19-24 (the “instituted claims”). In particular, the Board instituted review of
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`claim 24 as obvious over U.S. Patent No. 7,698,509 to Koster et al. (“Koster”), and
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`claims 19-23 as obvious over Koster in view of Jeffrey Kuskin, et al., The Stanford
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`FLASH Microprocessor, PROCEEDINGS OF THE 21ST ANNUAL INTERNATIONAL
`
`SYMPOSIUM ON COMPUTER ARCHITECTURE, IEEE (1994) (“Kuskin”). As explained
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`in more detail below, the Petitioner’s arguments rely on an incorrect claim
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`construction. As such, the Petitioners have not carried their burden to demonstrate
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`by a preponderance of the evidence that the instituted claims are unpatentable.
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`II. MEMORY INTEGRITY’S CLAIM CONSTRUCTIONS
`Memory Integrity proposes the following claim constructions for the
`
`purposes of this inter partes review proceeding.
`
`A.
`
`“states”
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`The term “states” is recited in independent claims 1 and 16 of the ’121
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`Patent as part of the longer phrase “probe filtering information representative of
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`1
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`
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`states associated with selected ones of the cache memories.” The term “states” is
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`also recited in independent claim 25 in the similar phrase “probe filtering
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`information . . . representative of states associated with selected ones of the cache
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`memories.”
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`In its decision on institution, the Board did not provide a specific
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`construction for “states,” but preliminarily determined that “states” in the claims of
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`the ’121 Patent are not limited to “cache coherence protocol states,” and that such
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`states may consist of mere presence. IPR2015-00158, Paper 7 (“Institution
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`Decision”) at 9-10. This was despite the fact that the Board determined that the
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`term “probe” in the claims should be construed as “a mechanism for eliciting a
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`response from a node to maintain cache coherency in a system.” Id. at 8. Patent
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`Owner submits, as further demonstrated in the declaration of Dr. Vojin Oklobdzija
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`filed herewith, that the appropriate construction of states is limited to cache
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`coherence states, and does not include mere presence.
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`As the Federal Circuit recently held, the Board may not “construe claims
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`during IPR so broadly that its constructions are unreasonable under general claim
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`construction principles.” Microsoft Corp. v. Proxyconn, Inc., 789 F.3d 1292 (Fed.
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`Cir. 2015). In particular, “giving claims their broadest reasonable interpretation
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`does not include giving claims a legally incorrect interpretation . . . [r]ather, claims
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`should always be read in light of the specification and teachings in the underlying
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`2
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`
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`patent.” Id. (citations and quotations omitted). “Even under the broadest
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`reasonable interpretation, the Board’s construction cannot be divorced from the
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`specification and the record evidence and must be consistent with the one that
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`those skilled in the art would reach.” Id. “A construction that is unreasonably
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`broad and which does not reasonably reflect the plain language and disclosure will
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`not pass muster.” Id.
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`Patent Owner respectfully submits that the construction of “states” adopted
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`by the Board in its decision on institution is incorrect because it does not properly
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`account for important teachings of the ’121 Patent and is divorced from the
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`particular technical field from which the ’121 Patent arises—the field of cache
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`coherency.
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`Indeed, the teachings of the ’121 Patent make it clear that its inventions are
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`directed to the specific field of cache coherency. Ex. 2016 (“Oklobdzija Decl.”) ¶¶
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`11-29. For example, from the very beginning of the “Background of the
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`Invention” section, the ’121 Patent states that “Data access in multiple processor
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`systems can raise issues relating to cache coherency.” IPR2015-00158, Ex. 1001
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`(“’121 Patent”) at 1:26-27. Similarly, the ’121 Patent describes the primary
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`problem to be solved as “to provide techniques for improving data access and
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`cache coherency in systems having multiple processors connected using point-to-
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`point links.” Id. at 2:39-42.
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`3
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`The Petitioners did not propose any construction of the term “states” in their
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`Petition. In the Board’s decision on institution, the Board primarily relied on the
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`“Microsoft Computer Dictionary”—a technical dictionary that is broadly directed
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`to the entire field of computing rather than to the specific technical fields at issue
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`in the ’121 Patent. Oklobdzija Decl. ¶ 14.
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`As Dr. Oklobdzija opines, although “state” may have many broad and
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`different meanings in both general English usage, as well as in the general field of
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`computers, the term “state” connotes a specific meaning in the field of cache
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`coherency—a cache coherency state. Oklobdzija Decl. ¶ 15. As an example of
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`this, in one of the treatises on cache coherency, Sorin et al., A Primer on Memory
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`Consistency and Cache Coherence (2011), the author equates the term “state” with
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`cache coherence protocol states. For example, in a section on cache coherence
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`protocol states, the author merely labels the section “States” as the heading for the
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`section, and then immediately discusses various characteristics of cache coherence
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`states, such as validity, dirtiness, exclusivity, and ownership. Ex. 2010 at 88-89;
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`Oklobdzija Decl. ¶ 15. This treatise also states that “[m]any coherence protocols
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`use a subset of the classic five state MOESI model first introduced by Sweazey and
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`Smith” and that “[t]he MOESI states, although quite common, are not an
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`exhaustive set of stable states. . . . [t]here are many possible coherence states, but
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`we focus our attention in this primer on the well-known MOESI states.” Id. at 89-
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`4
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`91; Oklobdzija Decl. ¶ 15. This interchangeable use of the term “states” and
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`“coherence states” and, use of the term “state” alone to discuss the states of a
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`particular cache coherence protocol, demonstrates that the term “state” means a
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`cache coherence protocol state in the field of cache coherency.
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`Additionally, the usage of the term “state” also dates back to the filing of the
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`patent. For example, in Specifying and Verifying a Broadcast and a Multicast
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`Snooping Cache Coherence Protocol, by Sorin et al. (2002), the author states that
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`“[a] processor’s access to a cache block is determined by the state of that block in
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`its cache, and this state is generally one of the five MOESI (Modified, Owned,
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`Exclusive, Shared, Invalid) states.” Oklobdzija Decl. ¶ 16; IPR2015-00158, Ex.
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`2003 at 1. Again, this demonstrates that, in the field of cache coherency, the term
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`“state” is equated with and means a cache coherence protocol state.
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`The teachings of the ’121 Patent also demonstrate that the use of the term
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`“state” in the patent is directed to cache coherence protocol states. Oklobdzija
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`Decl. ¶ 17. For example, the ’121 Patent states that: “[A] coherence protocol can
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`contain several types of messages . . . includ[ing] . . . probes,” that “[p]robes are
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`used to query each cache in the system, and that “[t]he probe packet can carry
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`information that allows the caches to properly transition the cache state for a
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`specified line.” ’121 Patent at 9:21-29 (emphasis added). Here, the term “state” is
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`plainly described in the context of a “coherence protocol,” and the probe’s method
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`5
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`of maintaining coherency in this embodiment is to inform the cache how to
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`transition from one cache state to another. The reference to “transition[ing]” states
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`makes it clear that the relevant state is a cache coherence protocol state.
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`Oklobdzija Decl. ¶ 18_.
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`Similarly, the ’121 Patent explains that “[b]y using a coherence directory,
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`global memory line state information (with respect to each cluster) can be
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`maintained and accessed by a memory controller or a cache coherence controller in
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`a particular cluster.” ’121 Patent at 13:4-7 (emphasis added). Again, this section
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`does not specifically state that the “memory line state information” is referring to
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`states in a cache coherence protocol—that is because, as Dr. Oklobdzija opines,
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`one of skill in the art would already understand that the term “state” in a reference
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`discussing cache coherency would refer to cache coherence protocol states.
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`Oklobdzija Decl. ¶ 19. However, the passage would make no sense if a
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`“coherence directory” was concerned with states other than coherence states. As
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`Dr. Oklobdzija opines, one of skill in the art would expect that if the phrase
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`“memory line state information” was referring to cache coherence protocol states
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`as well as other states, the patent would describe what those other “states” are—but
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`no description of “states” other than cache coherence protocol states is provided.
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`Id. Rather, the only thing described in the discussion of the coherence directory
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`using the term “states” are cache coherence protocol states.
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`6
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`
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`Figures 7 and 8 are strongly illustrative that the ’121 Patent uses “state” to
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`mean cache coherence protocol states. In particular, in describing Figure 7, the
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`patent simply states “the coherence directory 701 includes state information 713”
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`and “[i]n some embodiments, the memory line states are modified, owned, shared,
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`and invalid.” ’121 Patent at 13:55-59 (emphasis added); Oklobdzija Decl. ¶ 20.
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`Again, the patent is equating the word “state” with coherence states. Moreover,
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`Figure 7 of the ’121 Patent itself shows that the “State” field of the “Coherence
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`Directory” stores the traditional cache coherence protocol states of “Invalid,”
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`“Shared,” “Owned,” and “Modified.” ’121 Patent at Fig. 7; Oklobdzija Decl. ¶ 20.
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`Additionally, presence is not a cache coherence protocol state and mere
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`presence should not be construed as satisfying the “state” limitation. As Dr.
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`Oklobdzija opines, there is no cache coherence protocol that operates with mere
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`presence as any state, and Dr. Oklobdzija does not believe any such protocol could
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`work. Oklobdzija Decl. ¶ 21. In addition, Dr. Oklobdzija opines that a cache
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`coherence protocol state is concerned with the states of lines which are stored in
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`the cache, but presence merely indicates whether a line is stored in cache. Id.
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`Dr. Oklobdzija’s opinions are confirmed and supported by the teachings of
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`the ’121 Patent. For example, the ’121 Patent teaches that “because the cache
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`coherence directory provides information about where [i.e., in which cluster the
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`line is present] memory lines are cached as well as their states, probes only need
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`be directed toward the clusters in which the requested memory line is cached” and
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`“[t]he state of a particular cached line will determine what type of probe is
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`generated.” ’121 Patent at 19:36-43 (emphasis added). This passage plainly
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`indicates not only that the “state” of a memory line is different from “where” the
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`memory line is (i.e. in which cluster it is present), but also that a “state” only exists
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`for a cached line, i.e., one that is stored in a cache. This confirms that the relevant
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`“state” as used in the ’121 Patent is a state of a line that is “cached,” i.e. it is
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`already known that the line is present in one of the caches. On the other hand, the
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`“state” provides additional information about “a particular cached line” that is
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`known to already be “somewhere” (i.e. it is already known to be present).
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`Oklobdzija Decl. ¶ 22. Dr. Oklobdzija also notes that because the cache coherence
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`directory is implemented using an associative memory in the ’121 Patent, if a line
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`were not present, searching the coherence directory’s associative memory for the
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`cache line’s tag would simply result in a cache miss, rather than returning some
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`particular row containing a state field. Oklobdzija Decl. ¶ 23. Thus, presence in a
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`cache is distinct from and a pre-condition to the existence of state for that cache
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`line. Id.
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`The ’121 Patent’s discussion of an “occupancy vector” also demonstrates
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`that the ’121 Patent does not consider mere presence to be a “state.” The ’121
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`Patent explains that “[a]ny mechanism for tracking what clusters hold a copy of the
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`relevant memory line in cache [i.e., in which clusters the memory line is present] is
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`referred to herein as an occupancy vector.” ’121 Patent at 14:2-4; Oklobdzija Decl.
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`¶ 24. The patent provides the example of the occupancy vector “implemented as
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`an N-bit string, where each bit represents the availability of the data in the cache of
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`N clusters.” ’121 Patent at 13:67-14:2. The ’121 Patent’s discussion of “state
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`information” and “occupancy vector” expressly treats them as different, stating that
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`“the coherence directory 701 includes state information 713, dirty data owner
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`information 715, and an occupancy vector 717 associated with the memory lines
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`711.” ’121 Patent at 13:55-57. The “State” field and the “Occupancy Vector”
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`field are also depicted as two different fields in the coherence directory in Figure 7
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`of the ’121 Patent. ’121 Patent at Fig. 7. It would be peculiar for the ’121 Patent
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`to refer to the “occupancy vector” and “state” in this way if the patent envisioned
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`the term “state” to also potentially include presence information. Oklobdzija Decl.
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`¶ 24. If “State” could include presence information, one would expect that Figure
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`7 would say “Protocol State” instead of “State” to make clear that the “Occupancy
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`Vector” also held the “state” for a line. But it does not, instead indicating that the
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`’121 Patent understands presence and “state” to be different, and that “state”
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`exclusively refers to cache coherence protocol states. Oklobdzija Decl. ¶ 24.
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`Figure 8 of the ’121 Patent also demonstrates that “states” refers to cache
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`coherence protocol states. Figure 8 shows “Probe filter information” and lists
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`9
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`various cache coherence protocol states of the MOSI protocol, corresponding to
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`the same states depicted in Figure 7’s “State” column. This demonstrates that the
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`claimed “probe filtering information representative of states associated with
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`selected ones of the cache memories” is referring to “probe filtering information
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`representative of” cache coherence protocol states, and not mere presence.
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`The Board relies on a couple of passages in the ’121 Patent as supposedly
`
`supporting a broad construction of “state” not limited to cache coherence protocol
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`states. However, these passages do not support this construction. First, the Board
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`points to language in the patent that states:
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`Although the coherence directory 701 includes the four states of
`modified, owned, shared, and invalid [i.e., the MOSI protocol], it
`should be noted that particular implementations may use a different
`set of states. In one example, a system may have the five states of
`modified, exclusive, owned, shared, and invalid [i.e., MOESI
`protocol]. The techniques of the present invention can be used with a
`variety of different possible memory line states.
`
`See Institution Decision at 9-10 (quoting ’121 Patent at 14:30-36). However, as
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`Dr. Oklobdzija opines, because this passage should be read from the perspective of
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`one skilled in the art in the field of cache coherency, the reference to “a different
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`set of states” and a “variety of different possible memory line states” merely refers
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`to different sets of cache coherence protocol states—that is, the invention is not
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`10
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`limited to using the states of any specific cache coherence protocol. Oklobdzija
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`Decl. ¶ 26.1 This passage does not state or imply that states other than cache
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`coherence protocol states would be encompassed by the invention. Oklobdzija
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`Decl. ¶ 26. Importantly, all discussions and examples in the ’121 Patent of probe
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`filtering based on information representative of states discusses cache coherence
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`protocol states. Oklobdzija Decl. ¶ 26. Moreover, there is no evidence in the
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`record, including any opinions of Petitioners’ expert, explaining how such a system
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`could work. Oklobdzija Decl. ¶ 27.
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`The Board also draws attention to a passage stating that “According to a
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`specific embodiment, the directory of shared states may be implemented as
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`described above with reference to FIGS. 7 and 8, and indicates where particular
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`memory lines are cached within the cluster.” See Institution Decision at 10
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`(quoting ’121 Patent at 28:29-34). The Board apparently interprets this language
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`to mean that the “states” “indicate where particular memory lines are cached.”
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`However, the phrase “indicates where particular memory lines are cached” is
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`modifying the term “directory,” not the term “states.” Oklobdzija Decl. ¶ 29. As
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`Figures 7 and 8 depict, in addition to “states,” the directory also stores “dirty data
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`1 Protocols with different sets of states from the MOESI states are known in the
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`field. An example is the Dragon protocol. Ex. 2010 at 302; Oklobdzija Decl. ¶ 28.
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`11
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`owner” information and an “occupancy vector”—and it is those items, not “states”
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`which “indicate[] where particular memory lines are cached within the cluster.”
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`Oklobdzija Decl. ¶ 29. Indeed, as discussed above, the patent expressly
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`distinguishes “where” a cache line is from its “state,” explaining that: “the cache
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`coherence directory provides information about where [i.e., in which cluster the
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`line is present] memory lines are cached as well as their states.” ’121 Patent at
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`19:36-38.
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`Thus, the teachings of the ’121 Patent and the field of cache coherency as a
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`whole demonstrate that the term “state” in the ’121 Patent refers to cache
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`coherency states, and that mere presence is not a “state.”
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`III. PETITIONERS HAVE NOT MET THEIR BURDEN TO SHOW
`UNPATENTABILITY OF THE INSTITUTED CLAIMS
`
`The Petitioners have not and cannot meet their burden to show that any of
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`claims 19-24 are unpatentable. See 35 U.S.C. § 316(e), 37 C.F.R. § 42.1(d). The
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`Petitioners did not show that Koster discloses all of the limitations of any of the
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`instituted claims or that Koster or the combination of Koster and Kuskin renders
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`the instituted claims obvious. Accordingly, the Board should not hold any of the
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`instituted claims unpatentable.
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`12
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`Petitioners Failed To Demonstrate That Claim 24 Is Obvious Over
`Koster Alone
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`Patent No. 7,296,121
`IPR2015-00158
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`A.
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`As explained below, Koster fails to disclose the “probe filtering information
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`representative of states” limitation of claim 16. Since claim 24 depends from
`
`claim 16, Koster cannot disclose this limitation of dependent claim 24. Nor do the
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`Petitioners allege that Koster renders this limitation obvious. Thus, the Petitioners
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`have failed to show that Koster renders claims 24 unpatentable.
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`1. Koster Does Not Disclose “Probe Filtering Information
`Representative Of States Associated With Selected Ones Of The
`Cache Memories” As Required By Claim 24
`
`Claim 16 of the ’121 Patent recites “probe filtering information
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`representative of states associated with selected ones of the cache memories.”
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`Each of claims 19-24 depend directly or indirectly from claim 16, and therefore
`
`include this same limitation. The Petitioners contend that Koster’s tags stored in
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`shadow tag memory 164 satisfy this limitation. Pet. at 20. However, these tags do
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`not represent “states associated with selected ones of the cache memories” under
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`the proper claim construction. Oklobdzija Decl. ¶ 45. As explained above, this
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`term should be construed to refer to “cache coherency states.” Under the proper
`
`construction, Koster’s tags do not satisfy this limitation because they are not
`
`representative of cache coherency states. Id. Tags merely provide address
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`information. See id.; Ex. 2005 at 475 (defining “tag” as “A field in a table used for
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`a memory hierarchy that contains the address information required to identify
`13
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`whether the associated block in the hierarchy corresponds to a requested word.”).
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`Patent No. 7,296,121
`IPR2015-00158
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`In other words, a tag identifies a memory address but does not provide any
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`information regarding the state of that memory address. Oklobdzija Decl. ¶ 45.
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`Furthermore, Koster does not disclose the use of any other field representative of a
`
`cache coherence protocol state in the shadow tag memory. Id. Notably,
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`Petitioners’ own expert does not provide any explanation regarding the contents of
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`Koster’s shadow tag memory or assert that a person of skill in the art would have
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`understood Koster’s shadow tag memory to include any information other than
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`tags. Ex. 1013, ¶ 19. Accordingly, Koster’s disclosure of shadow tag memory 164
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`fails to disclose that it stores any information representative of cache coherence
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`protocol states.2 Oklobdzija Decl. ¶ 45.
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`The ’121 Patent confirms the distinction between tags and state information.
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`For example, in discussing the types of transaction information that the cache
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`coherence controller can maintain, the ’121 Patent refers to tags and state
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`information as separate items: “Transaction information maintained in the pending
`
`
`2
`Of course, even though tags by themselves do not represent a cache
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`coherence protocol state, there is no dispute that tags could be used in combination
`
`with other information to constitute “probe filtering information representative of
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`states associated with selected ones of the cache memories.”
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`14
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`
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`buffer 309 can include . . . tags, and state information.” Ex. 1001 at 7:67-8:4.
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`Patent No. 7,296,121
`IPR2015-00158
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`Additionally, Figure 7 of the ’121 Patent, which illustrates an example of a
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`coherence directory, contains separate columns for the memory line addresses (i.e.,
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`tags) and the state information. See Ex. 1001 at Fig. 7, 13:44-14:47.
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`Notably, the Petitioners do not provide any construction for the phrase
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`“states associated with selected ones of the cache memories” or any analysis of
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`how Koster’s tags allegedly meet this limitation. Pet. at 20. Rather, Petitioners
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`merely make the conclusory assertion that the tags of data are representative of
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`“states associated with selected ones of the cache memories.” Id. Similarly,
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`Petitioners’ expert provides no analysis regarding this limitation.
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`In its Decision on Institution, the Board found that Koster’s tags indicate
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`“where specific data is cached (i.e., the presence of data in specific locations)” and
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`that the “states” limitation is broad enough to include the “condition of presence.”
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`Institution Decision at 10 & 23. However, for the reasons explained in the claim
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`construction section above, the condition of presence is not a cache coherency state
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`and therefore cannot satisfy this limitation. Oklobdzija Decl. ¶¶ 21-29.
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`Thus, Koster fails to disclose the “probe filtering information representative
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`of states” limitation of claim 16. Since claim 24 depends from claim 16, Koster
`
`cannot disclose this limitation of dependent claim 24. Nor do the Petitioners allege
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`15
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`that Koster renders this limitation obvious. Thus, the Petition fails to show that
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`Patent No. 7,296,121
`IPR2015-00158
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`Koster renders claim 24 unpatentable. Oklobdzija Decl. ¶¶ 51 & 70.
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`B.
`
`Petitioners Failed To Demonstrate That Claims 19-23 Are Obvious
`Over Koster In View of Kuskin
`1.
`
`The Petition Fails To Demonstrate That The Combination Of
`Koster And Kuskin Teaches The “Probe Filtering Information
`Representative Of States” Limitation Of Claims 19-23
`
`As discussed in Section III.A.1 above, Koster fails to disclose the “probe
`
`filtering information representative of states” limitation of claim 16. Since claims
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`19-23 depend from claim 16, Koster cannot disclose this limitation of dependent
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`claims 19-23. Nor do the Petitioners allege that Kuskin discloses this missing
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`limitation. Accordingly, the Petition fails to show that the combination of Koster
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`and Kuskin renders claims 19-23 unpatentable. Oklobdzija Decl. ¶ 70.
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`IV. CONCLUSION
`For the foregoing reasons, Patent Owner respectfully requests that the Board
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`find that Petitioners have failed to meet their burden to show that the instituted
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`claims are unpatentable.
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`16
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`Patent No. 7,296,121
`IPR2015-00158
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`Respectfully submitted,
`
`
`
` /Jonathan D. Baker/
`Jonathan D. Baker
`Reg. No. 45708
`Farney Daniels PC
`411 Borel Avenue, Suite 350
`San Mateo, California 94402
`Phone: 424-268-5210
`E-mail: jbaker@farneydaniels.com
`
`17
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`Date: August 11, 2015
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`
`
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`
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`CERTIFICATE OF SERVICE
`
`Patent No. 7,296,121
`IPR2015-00158
`
`
`Under 37 C.F.R. §§ 42.6(e), this is to certify that I served a copy of the
`
`foregoing MEMORY INTEGRITY, LLC’S PATENT OWNER PRELIMINARY
`
`RESPONSE PURSUANT TO 37 C.F.R. § 42.107(A) along with the accompany-
`
`ing exhibits via email on August 11, 2015 to Petitioner’s counsel of record at the
`
`following email addresses:
`
`Lewis V. Popovski, Reg. No. 37,423
`Zaed M. Billah, Reg. No. 71,418
`Michael Sander, Reg. No. 71,667
`Kenyon & Kenyon LLP
`One Broadway
`New York, NY 10004
`Phone: 212-425-7200
`Fax: 212-425-5288
`Email:
`MemoryIntegrityv.Sony10760-225@kenyon.com
`lpopovski@kenyon.com
`zbillah@kenyon.com
`msander@kenyon.com
`
`Dated: August 11, 2015
`
` /Jonathan D. Baker/
`Jonathan Baker
`Reg. No. 45708
`
`
`
`
`
`18
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