Patent No. 7,296,121
`IPR2015-00158
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`
`
`SONY CORPORATION; SONY ELECTRONICS INC.;
`SONY MOBILE COMMUNICATIONS AB; AND
`SONY MOBILE COMMUNICATIONS (USA) INC.
`Petitioners
`
`v.
`
`MEMORY INTEGRITY, LLC
`Patent Owner
`
`U.S. Patent No. 7,296,121
`
`
`
`Inter Partes Review Case No. 2015-00158
`
`
`
`MEMORY INTEGRITY, LLC’S PATENT OWNER
`MOTION TO AMEND PURSUANT TO 37 CFR § 42.121
`
`
`
`

`
`Patent No. 7,296,121
`IPR2015-00158
`
`
`TABLE OF CONTENTS
`
`I. STATEMENT OF RELIEF REQUESTED ........................................................... 1 
`
`II. SUPPORT FOR THE SUBSTITUE CLAIMS [37 CFR § 42.121(B)(1)-(2)] ..... 1 
`
`A.  The ‘347 and ‘161 Applications Disclose the Limitations of Original
`Claim 16 .................................................................................................. 3 
`
`B.  The ‘347 and ‘161 Applications Discloses the Limitations of
`Original Claims 19-24 Via Incorporation By Reference ........................ 6 
`
`C.  The ‘347 and ‘161 Applications Disclose the New Proposed
`Limitations of Substitute Claims 29-34 .................................................. 8 
`
`III. CONSTRUCTION OF THE PROPOSED NEW LIMITATIONS ................... 10 
`
`A.  Construction of “cache coherency state” .............................................. 10 
`
`B.  Construction of “cache coherence protocol” ......................................... 12 
`
`C.  Construction of “modified state,” “exclusive state,” “shared state,”
`and “invalid state” ................................................................................. 13 
`
`D.  Construction of “coherent protocol interface” and “non-coherent
`protocol interface” ................................................................................ 16 
`
`IV. SCOPE OF THE PROPOSED SUBSTITUTE CLAIMS [37 C.F.R. §
`42.121(A)(2)(I)-(II)] ...................................................................................... 17 
`
`V. THE PROPOSED SUBSTITUTE CLAIMS SHOULD BE ALLOWED IF
`THE RESPECTIVE ORIGINAL CLAIMS ARE FOUND
`UNPATENTABLE ........................................................................................ 18 
`
`A.  The Pong and Koster references are the only references which
`arguably teach probe filtering in a system with processing nodes
`connected by point-to-point links .......................................................... 19 
`
`B.  No eligible prior art reference discloses “a probe filtering unit
`coupled to a coherent protocol interface and a non-coherent protocol
`interface” ............................................................................................... 22 
`
`VI. CONCLUSION .................................................................................................. 25
`i
`
`
`
`

`
`Patent No. 7,296,121
`IPR2015-00158
`
`
`EXHIBIT LIST
`
`Description
`Claims Appendix in Support of Motion to Amend
`
`Declaration of Vojin Oklobdzija, PhD in Support of
`Motion to Amend
`U.S. Patent Application No. 10/966,161 (“the ’161
`App.”)
`U.S. Patent Application No. 10/157,388 (“the ’388
`App.”)
`U.S. Patent Application No. 10/156,893 (“the ’893
`App.”)
`Papamarcos et al., A Low-Overhead Coherence
`Solution For Multiprocessors With Private Cache
`Memories (1984)
`Fong Pong et al., Design and Performance of SMPs
`With Asynchronous Caches (Nov. 1999)
`U.S. Patent No. 7,103,725
`
`U.S. Patent No. 7,395,379
`
`U.S. Patent No. 7,653,790
`
`U.S. Patent No. 7,251,698
`
`U.S. Patent No. 7,155,525
`
`U.S. Patent No. 7,281,055
`
`U.S. Patent No. 6,865,595
`
`U.S. Patent No. 7,103,636
`
`U.S.P.T.O. Assignment Database Records for U.S.
`Patent No. 7,296,121
`U.S.P.T.O. Assignment Database Records for U.S.
`Patent No. 7,003,633
`
`ii
`
`
`
`Exhibit No.
`Memory Integrity Ex.
`2018
`Memory Integrity Ex.
`2019
`Memory Integrity Ex.
`2020
`Memory Integrity Ex.
`2021
`Memory Integrity Ex.
`2022
`Memory Integrity Ex.
`2023
`
`Memory Integrity Ex.
`2024
`Memory Integrity Ex.
`2025
`Memory Integrity Ex.
`2026
`Memory Integrity Ex.
`2027
`Memory Integrity Ex.
`2028
`Memory Integrity Ex.
`2029
`Memory Integrity Ex.
`2030
`Memory Integrity Ex.
`2031
`Memory Integrity Ex.
`2032
`Memory Integrity Ex.
`2033
`Memory Integrity Ex.
`2034
`
`
`
`

`
`Patent No. 7,296,121
`IPR2015-00158
`
`
`U.S.P.T.O. Assignment Database Records for U.S.
`Patent Nos. 7,103,725, 7,107,408, 7,107,409,
`7,395,379, 7,653,790, 7,251,698, 7,155,525, 7,281,055,
`6,865,595 and 7,103,636
`Proprietary Information and Invention Assignment
`Agreement of David B. Glasco
`Hellwagner et al., SCI: Scalable Coherent Interface
`(1999)
`Defendants’ Answer in Memory Integrity LLC v.
`Samsung Electronics Company Ltd. et al, Dkt. No. 12
`(D. Del.)
`Redacted copy of Invalidity Contentions for ’121
`Patent served by Intel Corporation in Memory Integrity
`LLC v. Intel Corporation, (D. Or.)
`U.S. Patent Publ. No. 2002/0053004 (“Pong”)
`
`
`
`Memory Integrity Ex.
`2035
`Memory Integrity Ex.
`2036
`Memory Integrity Ex.
`2037
`
`Memory Integrity Ex.
`2038
`
`Memory Integrity Ex.
`2039
`Memory Integrity Ex.
`2040
`
`
`
`
`
`iii
`
`

`
`TABLE OF AUTHORITIES
`
`Patent No. 7,296,121
`IPR2015-00158
`
`
` Page(s)
`
`Cases
`Idle Free Systems, Inc. v. Bergstrom, Inc., IPR2012-00027, (PTAB
`Jun. 11, 2013). ..................................................................................................... 17
`
`MasterImage 3D, Inc. v. RealD Inc., IPR2015-00040 (PTAB Jul. 15,
`2015) ............................................................................................................. 18-20
`
`iv
`
`
`
`
`
`

`
`I. STATEMENT OF RELIEF REQUESTED
`Patent Owner moves under Rule 42.121 to amend U.S. Patent No. 7,296,121
`
`Patent No. 7,296,121
`IPR2015-00158
`
`
`(“the ’121 Patent”) contingent on the outcome of the trial. If any of the original
`
`claims 19-24 are found unpatentable, it is requested to replace them with their
`
`respective proposed substitute claims as set forth in the claims appendix filed
`
`herewith.
`
`II. SUPPORT FOR THE SUBSTITUE CLAIMS [37 CFR § 42.121(b)(1)-(2)]
`Proposed substitute claims 19-341 find section 112 support in the originally
`
`filed application leading to the ’121 Patent: Ex. 1001, U.S. Patent Application No.
`
`
`1
`Patent Owner’s claim appendix begins numbering the substitute claims at
`
`claim 29, and concludes at claim 34, and leaves claims 26-28 blank. This is based
`
`on the Board’s instruction to file separate motions to amend in each of the pending
`
`trials, but to ensure that the claims are consistent across the motions. In particular,
`
`the motion to amend filed in IPR2015-00159, where grounds have been instituted
`
`on claims 16-18, proposes substitute claims 26-28 corresponding to original claims
`
`16-18. Since claims 16-18 are not subject to institution in this proceeding, no
`
`substitute claims are presented in this motion. As to proposed substitute claims 19-
`
`24, they are the same in each motion to amend in each of IPR2015-00158, -00159,
`
`and -00163.
`
`
`
`1
`
`

`
`10/966,161 (“the ’161 App.”), as well as Ex. 2006, U.S. Patent Application No.
`
`Patent No. 7,296,121
`IPR2015-00158
`
`
`10/288,347 (“the ’347 App.”), which was incorporated by reference by the
`
`originally filed specification of the ’161 application (the ’161 Application is a
`
`continuation-in-part of the ’347 Application).
`
`Each of proposed substitute claims 19-34 were drafted by first converting
`
`the respective original claim 19-24 to independent form, and then adding the same
`
`proposed new limitations: “wherein said states comprise cache coherency states of
`
`a cache coherence protocol, and wherein said cache coherence protocol includes at
`
`least a modified state, an exclusive state, a shared state, and an invalid state, and
`
`wherein said probe filtering unit is coupled to a coherent protocol interface and a
`
`non-coherent protocol interface” (“the proposed new limitations”). Thus, each of
`
`proposed substitute claims recite the limitations of original claim 16.
`
`As demonstrated below, the ‘347 Application contains support for each of
`
`the proposed substitute claims, and because the ‘161 Application has a priority
`
`claim to the ‘347 App. at 1:9-13, the proposed substitute claims are therefore
`
`entitled to the priority date of the ‘347 Application. However, to the extent the
`
`Board determines that any of the proposed substitute claims are not entitled to the
`
`priority date of the ‘347 Application, they also have section 112 support in the
`
`disclosures of the ‘161 Application, as explained below.
`
`
`
`2
`
`

`
`A. The ‘347 and ‘161 Applications Disclose the Limitations of Original
`Claim 16
`
`Patent No. 7,296,121
`IPR2015-00158
`
`
`As the Board previously concluded in its decisions on institution in
`
`IPR2015-00158, Paper No. 7 and IPR2015-00163, Paper No. 18, support for each
`
`of the original limitations of claim 16 may be found in the ’347 Application.
`
`However, to the extent necessary, additional support for the original limitations of
`
`claim 16 is further provided in the ’161 Application. The ’347 Application
`
`discloses “a probe filtering unit” and “the probe filtering unit being operable to
`
`receive probes corresponding to memory lines from the processing nodes and to
`
`transmit the probes only to selected ones of the processing nodes with reference to
`
`probe filtering information representative of states associated with selected ones of
`
`the cache memories” in Figures 2, 3, 7, 8, 11 and the corresponding discussion at
`
`’347 App. at 9:4-10:19, 20:31-23:16, 25:7-26:14. In particular, the ’347
`
`application discloses a cache coherence controller that receives probes from the
`
`processing nodes and then uses probe filtering information to transmit probes to a
`
`subset of the processing nodes. See id. It explains that “probe filter information is
`
`used to limit the number of probe requests transmitted to request and remote
`
`clusters.” ’347 App. at 33:9-10. The application further explains that:
`
`FIG. 8 is a diagrammatic representation showing probe filter
`information that can be used to reduce the number of transactions in a
`multiple cluster system. Any criterion that can be used to reduce the
`
`
`
`3
`
`

`
`number of clusters probed from a home cluster is referred to herein as
`probe filter information.
`
`Patent No. 7,296,121
`IPR2015-00158
`
`
`Id. at 22:20-23. The application also explains that:
`
`FIG. 11 is a process flow diagram showing one example of a
`technique for handling probe requests at a home cache coherence
`controller . . . [that uses] probe filter information at 1113 to determine
`whether the number of probes to various clusters in the system can be
`reduced.
`
`Id. at 25:7-13. The ’161 Application provides further disclosure of the probe
`
`filtering unit in Figures 18-22 and the corresponding discussion at ’161 App. at,
`
`43:4-48:3. The ’161 Application also describes that “the filtering of probes within
`
`a cluster, i.e. local probe filtering, . . . may be implemented in a . . . probe filtering
`
`unit (PFU).” ’161 App. at 42:20-43:2. The ’161 Application describes the claimed
`
`functionality of the probe filtering unit, or PFU, as “[t]he PFU accepts the probe
`
`and looks up the address in the directory of shared cache states . . . [i]f, . . . the
`
`directory lookup determines the cache line may be cached in the system (2010), the
`
`PFU sends out a probe only on links corresponding to the nodes that may contain
`
`the cache line (2014).” ’161App. at 45:21-22, 46:4-7.
`
`The ’347 Application also discloses that the probe filtering unit is “for use in
`
`a computer system comprising a plurality of processing nodes interconnected by a
`
`first point-to-point architecture , each processing node having a cache memory
`
`
`
`4
`
`

`
`associated therewith” in Figures 1A, 1B, and 2, and the corresponding discussion
`
`Patent No. 7,296,121
`IPR2015-00158
`
`
`at ’347 App. at 9:4-11:19. For example, Figures 1A and 1B show point-to-point
`
`connections between processing clusters, and Figure 2 shows that the processors
`
`and cache coherence controller within each cluster are also connected using point-
`
`to-point connections. The specification also discloses that each processor has an
`
`associated cache memory. Id. at 2:3-4, 12:29-31, Fig. 4. Moreover, the Apple
`
`Petitioners’ proposed construction of “processing node” as “an interconnectable
`
`computer subsystem comprising at least one processor” (2015IPR-00163, Pet. at 6)
`
`is broad enough to encompass a cluster of processors. The ’161 Application
`
`contains these same disclosures. ’161 App., Figs. 1A, 1B, 2, at 10:8-12:27.
`
`Additionally, the ’161 Application also contains further disclosures in Figure 18
`
`and the associated text, which demonstrates point-to-point connections between
`
`individual processors within a cluster, each with their own associated cache. ’161
`
`App. at, Fig. 18, 43:4-27 (“System 1800 includes processing nodes 1802a-1802 . . .
`
`and point-to-point communication links 1808a-1808e . . . The point-to-point
`
`communication links are configured to allow interconnections between processing
`
`nodes 1802a-1802d . . . and probe filtering unit 1830 according to a point-to-point
`
`communication protocol.”).
`
`
`
`5
`
`

`
`The ‘347 and ‘161 Applications Discloses the Limitations of Original
`Claims 19-24 Via Incorporation By Reference
`
`Patent No. 7,296,121
`IPR2015-00158
`
`
`B.
`
`The ’161 Application incorporates by reference U.S. Application No. the
`
`’347 Application, ’161 App. at 2:13-17. The ’347 Application in turn incorporates
`
`by reference U.S. Patent Application No. 10/157,388. ’347 App. at 1:17-23. U.S.
`
`Application No. 10/157,388 in turn incorporates by reference U.S. Patent
`
`Application No. 10/156,893 (Ex. 2022, “the ’893 App.”). Ex. 2021 at 1:28-29.2
`
`The ’893 Application describes an “interconnection controller 230” which,
`
`“[a]ccording to some embodiments,” “performs a variety of other functions
`
`including the maintaining of cache coherency . . .” ’893 App. at 6:9-10. Figures
`
`1A, 1B, and 2 of the’893 Application are substantially the same, respectively, as
`
`Figures 1A, 1B, and 2 of the ’161 and ’347 Applications, with the “cache
`
`coherence controller” of Figure 2 of the’161 ’347 Applications instead being
`
`labeled a “controller,” which the ‘893 Application describes as an “interconnection
`
`controller.” ’893 App Figs 1-2, ’161 App. Figs. 1-2, ’347 App. Figs. 1-2. Thus,
`
`
`2
`The ’893 Application was referred to by its title and its attorney docket
`
`number in the incorporation by reference of the original ’388 Application. Ex.
`
`2021 at 1:28-29. However, the ’388 Application was amended during prosecution
`
`to fill in the assigned U.S. Application numbers prior to its issuance as U.S. Patent
`
`No. 7,103,636 (Ex. 2032).
`
`
`
`6
`
`

`
`the ’893 Application teaches that the cache coherence controller may also be an
`
`Patent No. 7,296,121
`IPR2015-00158
`
`
`interconnection controller.
`
`Claim 19 (and proposed substitute claim 29) adds the further limitation to
`
`claim 16 that “At least one computer-readable medium having data structures
`
`stored therein representative of the probe filtering unit.” Claim 20 (and proposed
`
`substitute claim 30) adds the further limitation that “the data structures comprise a
`
`simulatable representation of the probe filtering unit.” Claim 21 (and proposed
`
`substitute claim 31) adds the further limitation that “the simulatable representation
`
`comprises a netlist.” Each of these limitations is disclosed in the ’893
`
`Application’s teaching that “the interconnection controller described herein may be
`
`represented (without limitation) in software (object code or machine code), in
`
`varying stages of compilation, as one or more netlists, in a simulation language . .
`
`.” ’893 App. at 21:18-22:4. As noted above, the interconnection controller of
`
`the’893 Application is the same component as the cache coherence controller of
`
`the ’161 and ’347 Applications. 3
`
`
`3
`This Board already concluded that “the ’347 application’s disclosure related
`
`to a cache coherence controller and probe filtering information ‘reasonably
`
`conveys to those skilled in the art that the inventor had possession’ of the claimed
`
`‘probe filtering unit.’” IPR2015-00158, Paper 7 at 17.
`
`
`
`7
`
`

`
`Claim 22 (and proposed substitute claim 32) adds the further limitation to
`
`Patent No. 7,296,121
`IPR2015-00158
`
`
`claim 19 that “the data structures comprise a code description of the probe
`
`filtering unit. Claim 23 (and proposed substitute claim 33) adds the further
`
`limitation that the “the code description corresponds to a hardware description
`
`language.” These limitations are satisfied by the ’893 Application’s description
`
`that “the interconnection controller described herein may be represented (without
`
`limitation) in software (object code or machine code), in varying stages of
`
`compilation, . . . in a hardware description language.” ’893 App. at 21:18-22:4.
`
`Claim 24 (and proposed substitute claim 34) adds the further limitation to
`
`claim 16 that “[a] set of semiconductor processing masks representative of at least
`
`a portion of the probe filtering unit.” The ’893 Application also provides
`
`disclosure as to this limitation, describing that “the interconnection controller
`
`described herein may be represented (without limitation) . . . by a set of
`
`semiconductor processing masks.” ’893 App. at 21:18-22:4. Therefore, the ‘347
`
`and ‘161 Applications disclose the limitations or original claims 19-24.
`
`C. The ‘347 and ‘161 Applications Disclose the New Proposed Limitations
`of Substitute Claims 29-34
`
`Each of the new proposed limitations of proposed substitute claims 29-34 is
`
`supported by the ’347 and ’161 Applications. As to the proposed new limitation
`
`“wherein said states comprise cache coherency states of a cache coherence
`
`
`
`8
`
`

`
`protocol, and wherein said cache coherence protocol includes at least a modified
`
`Patent No. 7,296,121
`IPR2015-00158
`
`
`state, an exclusive state, a shared state, and an invalid state,” the ’347 Application
`
`teaches that “system may have the five states of modified, exclusive, owned,
`
`shared, and invalid” and “[t]he techniques of the present invention can be used
`
`with a variety of different possible memory line states.” ’347 App. at 22:8-10.
`
`The ‘347 Application further explains how such states operate as part of a cache
`
`coherence protocol. For example, it teaches that “a coherence protocol includes …
`
`probes,” which “are used to query each cache in the system” and that “[t]he probe
`
`packet can carry information that allows the caches to properly transition the cache
`
`state for a specified line.” ’347 App. at 13:30-15:3.
`
`As to the proposed new limitation “wherein said probe filtering unit is
`
`coupled to a coherent protocol interface and a non-coherent protocol interface,”
`
`Figure 3 of the ’347 Application is a depiction of a cache coherence controller with
`
`a “Coherent Interfance 307” and a “Noncoherent Interface 311.” ’347 App. Fig. 3.
`
`The ’347 Application explains that “[t]he cache coherence controller” can
`
`“support[] the local point-to-point coherence protocol” and “can also be configured
`
`to handle a non-coherent protocol to allow communication with I/O devices.” ’347
`
`App. at 11:13-14. The ’347 Application also explains that:
`
`The cache coherence controller has an interface such as a coherent
`protocol interface 307 that allows the cache coherence controller to
`
`
`
`9
`
`

`
`Patent No. 7,296,121
`IPR2015-00158
`
`
`communicate with other processors in the cluster as well as external
`processor clusters. The cache coherence controller can also include
`other interfaces such as a non-coherent protocol interface 311 for
`communicating with I/O devices. According to various embodiments,
`each interface 307 and 311 is implemented either as a full crossbar or
`as separate receive and transmit units using components such as
`multiplexers and buffers.
`’161 App. at at 13:11-17. Of course, the ’161 Application explains that “the probe
`
`filtering functionalities described herein may be implemented in a cache coherence
`
`controller,” ’161 App. at 42:22-24, and this Board has already determined that the
`
`earlier disclosures of the ‘347 Application regarding a cache coherence controller
`
`and probe filtering information showed possession of a probe filtering unit.
`
`IPR2015-00158, Paper 7 at 17; see also ’347 App. at 23:20–24:16, 26:7–27:14,
`
`34:9–10, Figs. 8, 11, supra at 3. Thus, the ’347 Application has support for a
`
`probe filtering unit which is coupled to a coherent protocol interface and a non-
`
`coherent protocol interface.
`
`III. CONSTRUCTION OF THE PROPOSED NEW LIMITATIONS
`Patent Owner provides proposed claim constructions for the terms in the
`
`proposed new limitations of proposed substitute claims 29-34 consistent with the
`
`broadest reasonable interpretation standard applied by this Board.
`
`A. Construction of “cache coherency state”
`The term “cache coherency state” is an ordinary term whose meaning is well
`
`
`
`10
`
`

`
`understood in the field of cache coherency and Patent Owner submits that no
`
`Patent No. 7,296,121
`IPR2015-00158
`
`
`further construction is necessary. However, to the extent that the Board determines
`
`that a construction is necessary, Patent Owner requests that the Board construe the
`
`term “cache coherency state” as “a state in a cache coherence protocol which
`
`specifies the characteristics of a data block or memory line stored in a cache
`
`memory.” This is consistent with the ordinary meaning of “cache coherency state”
`
`in the field.
`
`For example, Sorin et al., A Primer on Memory Consistency and Cache
`
`Coherence (2011) teaches that: a “designer of a coherence protocol must choose
`
`the states, transactions, events, and transitions for each type of coherence controller
`
`in the system.” Ex. 2010 at 88. The Sorin book further teaches that “[i]n a system
`
`with only one actor (e.g., a single core processor without coherent DMA), the state
`
`of a cache block is either valid or invalid,” but “[t]here might be two possible valid
`
`states for a cache block if there is a need to distinguish blocks that are dirty.” Id.
`
`Sorin further teaches that “[a] system with multiple actors can also use just these
`
`two or three states, . . . but we often want to distinguish between different kinds of
`
`valid states.” Id. Sorin further teaches that “[m]any coherence protocols use a
`
`subset of the classic five state MOESI model” . . . and that these “states refer to the
`
`states of blocks in a cache.” Id. at 89. The Sorin book teaches that these states
`
`reflect different combinations of various characteristics of the block in a cache,
`
`
`
`11
`
`

`
`such as validity (whether the block “has the most-up-to-date value”), dirtiness (for
`
`Patent No. 7,296,121
`IPR2015-00158
`
`
`a block which has “the most up-to-date value”, whether its “value differs from the
`
`value” of that block stored in memory or last-level cache), exclusivity (whether a
`
`block is “the only privately cached copy of the block in the system”), and
`
`ownership (whether the cache in which the block is stored ‘is responsible for
`
`responding to coherence requests for that block’). Id. at 89.
`
`B. Construction of “cache coherence protocol”
`The term “cache coherence protocol” is also an ordinary term whose
`
`meaning is well understood in the field of cache coherency and Patent Owner
`
`submits that no further construction is necessary. However, to the extent that the
`
`Board determines that a construction is necessary, Patent Owner requests that the
`
`Board construe the term “cache coherence protocol” as “a protocol for maintaining
`
`cache coherency in a computer system with multiple processing nodes, comprising
`
`a plurality of cache coherency states, as well as rules and messages for
`
`transitioning between such states.” This is consistent with the ordinary meaning of
`
`“cache coherence protocol” in the field.
`
`As discussed, Sorin et al., A Primer on Memory Consistency and Cache
`
`Coherence (2011) teaches that: “designer of a coherence protocol must choose the
`
`states, transactions, events, and transitions for each type of coherence controller in
`
`the system.” Ex. 2010 at 88. Sorin also describes “a coherence protocol” as “a set
`
`
`
`12
`
`

`
`of rules implemented . . . within a [computer] system.” Id. at 4.
`
`Patent No. 7,296,121
`IPR2015-00158
`
`
`Similarly, the ’121 Patent teaches that “a coherence protocol can contain
`
`several types of messages . . . includ[ing] . . . data or cache access requests, probes,
`
`responses or probe responses, and data packets.” ’121 Pat. at 9:21-33. The ’121
`
`Patent further teaches that “ [t]he probe packet can carry information that allows
`
`the caches to properly transition the cache state for a specified line.” Id. It also
`
`teaches that probes can ‘also include ‘next state’ information which indicates to
`
`each node what the state of its copy of the line should be at the end of the
`
`transaction.” ’121 Pat. at 26:25-27. It continues to explain that, “[a]ccording to a
`
`specific embodiment, the next state information indicates one of three possibilities,
`
`i.e., that there should be no change to the line status, that it should be moved to
`
`‘shared,’ or moved to ‘invalid.’” ’121 Pat. at 26:28-31. Thus, the ’121 Patent also
`
`confirms that a cache coherence protocol is a protocol for maintaining cache
`
`coherency in a computer system with multiple processing nodes, comprising a
`
`plurality of cache coherency states, as well as rules and messages for transitioning
`
`between such states.”
`
`C. Construction of “modified state,” “exclusive state,” “shared state,” and
`“invalid state”
`The terms “modified state,” “exclusive state,” “shared state,” and “invalid
`
`state” are ordinary terms whose meaning is well understood in the field of cache
`
`
`
`13
`
`

`
`coherency and Patent Owner submits that no further construction is necessary.
`
`Patent No. 7,296,121
`IPR2015-00158
`
`
`However, to the extent that the Board determines that a construction is necessary,
`
`Patent Owner requests that the Board construe the term “modified state” as “a state
`
`indicating that the cache memory holds the only valid copy of the pertinent line (or
`
`block), and the value of the line (or block) may have been modified from the value
`
`stored in memory,” that the Board construe the term “exclusive state” as “a state
`
`indicating that the cache memory holds the only valid copy of the pertinent line (or
`
`block), and the value of the line (or block) has not been modified from the value
`
`stored in memory,” that the Board construe the term “shared state” as “a state
`
`indicating that the cache memory is one of potentially multiple memories holding
`
`valid, read-only copies of the pertinent line (or block),” and that the Board construe
`
`the term “invalid state” as “a state indicating that the cache does not hold a valid
`
`copy of the pertinent line (or block), i.e. that its value for the pertinent line (or
`
`block) is not the most-up-to-date value.”
`
`These constructions are consistent with the term’s ordinary meaning in the
`
`field. As discussed, Sorin et al., A Primer on Memory Consistency and Cache
`
`Coherence (2011) defines the “modified” state as:
`
`The block is valid, exclusive, owned, and potentially dirty. The block
`may be read or written. The cache has the only valid copy of the
`block, the cache must respond to requests for the block, and the copy
`
`
`
`14
`
`

`
`of the block at the LLC/memory is potentially stale.
`Ex. 2010 at 89. Sorin defines the “exclusive” state as:
`
`Patent No. 7,296,121
`IPR2015-00158
`
`
`The block is valid, exclusive, and clean. The cache has a read-only
`copy of the block. No other caches have a valid copy of the block, and
`the copy of the block in the LLC/memory is up-to-date.
`Id. at 90. Sorin defines the “shared” state as:
`
`The block is valid but not exclusive, not dirty, and not owned. The
`cache has a read-only copy of the block. Other caches may have
`valid, read-only copies of the block.
`Id. at 89. Similarly, Papamarcos et al., A Low-Overhead Coherence Solution For
`
`Multiprocessors With Private Cache Memories (1984) describes both potential
`
`“Shared-Modified” and “Shared-Unmodified states” and notes that in the shared
`
`state “some other caches may have this block” but describes that a block may
`
`become “no longer truly Shared,” such as by having all but one of the caches evict
`
`the block. Ex. 2023 at 349.
`
`
`
`As to the invalid state, Sorin teaches that “[a] valid block has the most up-to-
`
`date value for this block” and teaches that the “invalid” state indicates that “[t]he
`
`block is invalid . . .”Ex. 2010 at 88-89. Papamarcos et al., A Low-Overhead
`
`Coherence Solution For Multiprocessors With Private Cache Memories describes
`
`the “invalid” state as simply indicating that the “[b]lock does not contain valid
`
`data.” Ex. 2023 at 349.
`
`
`
`15
`
`

`
`D. Construction of “coherent protocol interface” and “non-coherent
`protocol interface”
`
`Patent No. 7,296,121
`IPR2015-00158
`
`
`The terms “coherent protocol interface” and “non-coherent protocol
`
`interface are ordinary terms whose meaning is well understood in the field of cache
`
`coherency and Patent Owner submits that no further construction is necessary.
`
`However, to the extent that the Board determines that a construction is necessary,
`
`Patent Owner requests that the Board construe the term “coherent protocol
`
`interface” as “an interface for communications between components in a computer
`
`system while maintaining cache coherency” and construe the term “non-coherent
`
`protocol interface” as “an interface for communicating with components in a
`
`computer system without regard to maintaining cache coherency.” This is
`
`consistent with their ordinary meaning in the field, as well as the specific teachings
`
`of the ’121 Patent. For example, the ’121 Patent teaches that:
`
`The cache coherence controller has an interface such as a coherent
`protocol interface 307 that allows the cache coherence controller to
`communicate with other processors in the cluster as well as external
`processor clusters. . . . According to various embodiments, each
`interface 307 and 311 is implemented either as a full crossbar or as
`separate receive and transmit units using components such as
`multiplexers and buffers.
`’121 Pat. at 8:5-19. The ’121 Patent also teaches that “[t]he cache coherence
`
`controller” can be “an Application Specific Integrated Circuit (ASIC) supporting
`
`
`
`16
`
`

`
`the local point-to-point coherence protocol” and that the “PFU [can be] an
`
`Patent No. 7,296,121
`IPR2015-00158
`
`
`Application Specific Integrated Circuit (ASIC) supporting the local point-to-point
`
`coherence protocol” and that the “PFU [] can also be configured to handle a non-
`
`coherent protocol to allow communication with I/O devices.” ’121 Pat. at 7:42-52.
`
`This is consistent with Patent Owner’s proposed construction, as one would want
`
`communications between processors to be coherent, but communications with I/O
`
`devices need not be coherent.
`
`IV. SCOPE OF THE PROPOSED SUBSTITUTE CLAIMS [37 C.F.R. §
`42.121(a)(2)(i)-(ii)]
`
`The proposed substitute claims 29-34 have an acceptable scope under 37
`
`C.F.R. § 42.121(a)(2)(i)-(ii). Firstly, each proposed substitute claim responds to a
`
`ground of unpatentability involved in the trial of this action, because they include
`
`each feature of the challenged claims which they replace, and further narrow those
`
`claims’ features by adding new limitations. See Idle Free Systems, Inc. v.
`
`Bergstrom, Inc., IPR2012-00027, Paper 26 at 3 (PTAB Jun. 11, 2013). Secondly,
`
`each proposed substitute claim does not enlarge the scope of the claims of the
`
`patent or introduce new subject matter. 37 C.F.R. § 42.121(a)(2)(ii). The
`
`proposed substitute claims do not introduce new matter because they are supported
`
`by the ’347 and ’161 Applications, as discussed above. The proposed substitute
`
`claims do not enlarge the scope of the claims of the ’121 Patent because they
`
`
`
`17
`
`

`
`merely consist of the original claims 19-24 of the ’121 Patent, rewriting the claims
`
`Patent No. 7,296,121
`IPR2015-00158
`
`
`in into independent form, and adding the new proposed limitations, discussed
`
`above, to the end of the claim.
`
`V. THE PROPOSED SUBSTITUTE CLAIMS SHOULD BE ALLOWED IF
`THE RESPECTIVE ORIGINAL CLAIMS ARE FOUND UNPATENTABLE
`
`If