UNITED STATES PATENT AND TRADEMARK OFFICE
`
`Case Nos. IPR2015-00158
`IPR2015-00159
`IPR2015-00163
`
`
`In re Patent of: Morton et al.
`U.S. Patent No. 7,296,121
`Issue Date:
`Nov. 13, 2007
`Appl. Serial No.: 10/966,161
`Filing Date:
`Oct. 15, 2004
`Title: REDUCING PROBE TRAFFIC IN MULTIPROCESSOR SYSTEMS
`
`
`
`DECLARATION OF VOJIN OKLOBDZIJA, Ph.D.
`IN SUPPORT OF PATENT OWNER’S MOTIONS TO AMEND
`
`
`I, Vojin Oklobdzija, PhD, hereby declare as follows:
`
`1.
`
`My name is Dr. Vojin Oklobdzija. I submit this declaration in
`
`support of Patent Owner’s Motions to Amend in IPR2015-00158, -00159, and -
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`00163. I have been asked to offer technical opinions relating to U.S. Patent No.
`
`7,296,121 and the proposed substitute claims presented by the motions.
`
`2.
`
`I received a Dipl. Ing. (equivalent to a Master’s in Electrical
`
`Engineering in the U.S.) degree in Telecommunications and Electronics in 1971
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`from the University of Belgrade, Yugoslavia, followed by a Master’s in Computer
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`Science from the University of California, Los Angeles in 1978. I received a Ph.D.
`
`in Computer Science with a minor in Electronics from the University of California,
`
`Los Angeles in 1982.
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`3.
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`Following my Ph.D. graduation, I spent 9 years at IBM’s T.J.
`
`Watson Research Center working on microprocessor architecture, development
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`
`
`1
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`
`
`Case Nos. IPR2015-00158
`IPR2015-00159
`IPR2015-00163
`
`
`In re Patent of: Morton et al.
`U.S. Patent No. 7,296,121
`Issue Date:
`Nov. 13, 2007
`Appl. Serial No.: 10/966,161
`Filing Date:
`Oct. 15, 2004
`Title: REDUCING PROBE TRAFFIC IN MULTIPROCESSOR SYSTEMS
`
`
`
`DECLARATION OF VOJIN OKLOBDZIJA, Ph.D.
`IN SUPPORT OF PATENT OWNER’S MOTIONS TO AMEND
`
`
`I, Vojin Oklobdzija, PhD, hereby declare as follows:
`
`1.
`
`My name is Dr. Vojin Oklobdzija. I submit this declaration in
`
`support of Patent Owner’s Motions to Amend in IPR2015-00158, -00159, and -
`
`00163. I have been asked to offer technical opinions relating to U.S. Patent No.
`
`7,296,121 and the proposed substitute claims presented by the motions.
`
`2.
`
`I received a Dipl. Ing. (equivalent to a Master’s in Electrical
`
`Engineering in the U.S.) degree in Telecommunications and Electronics in 1971
`
`from the University of Belgrade, Yugoslavia, followed by a Master’s in Computer
`
`Science from the University of California, Los Angeles in 1978. I received a Ph.D.
`
`in Computer Science with a minor in Electronics from the University of California,
`
`Los Angeles in 1982.
`
`3.
`
`Following my Ph.D. graduation, I spent 9 years at IBM’s T.J.
`
`Watson Research Center working on microprocessor architecture, development
`
`
`
`1
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`
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`and design. In my career at IBM, I worked on the early development of RISC
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`Patent No. 7,296,121
`Case Nos. IPR2015-00158, -00159, -00163
`
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`(Reduced Instruction Set Architecture Computer) architecture and development of
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`a new processor generation for IBM. Most notably, I worked on the first
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`commercial RISC computer, IBM ROMP, as well as the first super-scalar
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`microprocessor, IBM RS/6000.
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`4.
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`After leaving IBM, I have held faculty (Full Professor) position at
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`the University of California, Davis; and visiting positions at the University of
`
`California Berkeley, Sydney University in Australia; EPFL in Switzerland and
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`others. I have over 20 years of teaching experience, teaching courses in:
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`Computer Architecture, Computer Design, Digital Design, VLSI Circuits as well
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`as advanced post-graduate courses in Computer Architecture and Design. During
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`this time, I served as a consultant with members of the microprocessor industry
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`extensively and was a principal architect in the Siemens/Infineon TriCore
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`processor.
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`5.
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`After retiring from the academia, I returned back to industry. In
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`2013, I became a Senior Director of Microprocessor Development at Skyera Inc., a
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`startup company that was subsequently acquired by Hitachi Ltd. While working at
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`Skyera, I lead a team developing an on-chip processor array consisting of a grid or
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`256 processors, including development of its cache-coherency mechanism and its
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`fast cache memory hierarchy.
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`
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`2
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`
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`Patent No. 7,296,121
`Case Nos. IPR2015-00158, -00159, -00163
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`Currently I am President and CTO of my own startup company,
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`6.
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`Silicon Analytics Inc. and I also work as a consultant. I am a named inventor on
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`15 issued U.S. Patents and a similar number of international patents. I have also
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`authored several books on microprocessor design, including a book titled
`
`“Computer Engineering Handbook,” published by CRC Press in 2001, which won
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`the CHOICE Outstanding Academic Title Award for 2002, as well as “High
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`Performance Energy Efficient Microprocessor Design” published Springer in 2006.
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`I have attached a true and correct copy of my curriculum vitae as Exhibit 2017,
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`which further sets forth my qualifications.
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`7.
`
`I have reviewed and am familiar with the content of U.S. Patent No.
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`7,296,121 (“the ’121 Patent”). I have also reviewed each of the items of prior art
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`cited on the face of the ’121 Patent. I have also reviewed the prior art submitted in
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`connection with IPR2015-00158, -00159, -00161, -00163, and -00172. I have also
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`reviewed the prior art disclosed by the Samsung defendants in their answer filed
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`Memory Integrity LLC v. Samsung Electronics Company Ltd. et al, Dkt. No. 12 (D.
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`Del. Feb. 24, 2014), Ex. 2038. I have also reviewed the invalidity contentions
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`served by Intel Corporation for the ’121 Patent in Memory Integrity LLC v. Intel
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`
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`3
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`
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`Corporation, (D. Or. filed Nov. 1, 2013), Ex. 2039, and the associated prior art1. I
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`Patent No. 7,296,121
`Case Nos. IPR2015-00158, -00159, -00163
`
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`understand and am informed that, together, this comprises all prior art of record of
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`the ’121 Patent as well as all prior art to the ’121 Patent known to the Patent
`
`Owner.
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`8.
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`I have reviewed the art of record and the prior art known to the
`
`Patent Owner and it is my opinion that substitute claims 26-34 are patentable over
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`such prior art, even if the Board concludes that the corresponding original claims
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`are unpatentable. No single reference which I have reviewed contains each
`
`
`1
`The only qualification to my review of these materials is that, in the
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`invalidity contentions served by Intel Corporation, there are certain documents
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`relating to the Intel 870 Chipset which have not been provided to me, and certain
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`quotes from those documents which have been redacted. I understand that I am not
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`permitted to see those documents because Intel has designated those documents
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`“Confidential Attorneys’ Eyes Only” and “Subject to the Prosecution Bar,” and
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`because the protective order in the litigation prohibits anyone who sees such
`
`materials from being involved in, among other things, participating in advising on
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`new or amended claims. However, I believe I have been able to adequately review
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`and understand the materiality of the Intel 870 Chipset based on other public
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`documentation available regarding that chipset.
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`
`
`4
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`
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`limitation of any of the proposed substitute claims, and no combination of such
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`Patent No. 7,296,121
`Case Nos. IPR2015-00158, -00159, -00163
`
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`references renders any of the proposed substitute claims obvious.
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`9.
`
`As to the limitations of the original claim 16 of the ’121 Patent, it is
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`my opinion that the Pong and Koster references are the closest and most material
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`prior art to those claim limitations and the only references of which I have
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`reviewed which arguably teach probe filtering in a system with processing nodes
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`connected by point-to-point links.2 As to the Koster reference, I am informed that
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`Koster is not prior art because the substitute claims are entitled to the November 4,
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`2002 priority date of the ’347 Application.
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`10.
`
`As to the Pong reference, Pong itself does not teach any particular
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`cache coherence protocol states and thus does not practice the limitation of the
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`proposed substitute claims that “wherein said states comprise cache coherency
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`states of a cache coherence protocol, and wherein said cache coherence protocol
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`includes at least a modified state, an exclusive state, a shared state, and an invalid
`
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`2 I say arguably because, as set forth in my declaration in support of Patent
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`Owner’s responses, I do not believe that Pong or Koster render any claims of the
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`’121 Patent invalid. However, I understand that the Board may disagree with my
`
`analysis and that the purpose of these motions is to substitute claims if the Board
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`concludes that the original claims are invalid.
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`
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`5
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`
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`Patent No. 7,296,121
`Case Nos. IPR2015-00158, -00159, -00163
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`state.” Moreover, I do not believe that Pong can be readily adapted or modified, or
`
`combined with other references to practice this limitation. In particular, Fong
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`Pong et al., Design and Performance of SMPs With Asynchronous Caches (Nov.
`
`1999) teaches, in describing the same system as the Pong patent application
`
`reference, that the specific way of connecting the asynchronous architecture
`
`employed by Pong prevented use of the conventional Exclusive state. Ex. 2024.
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`In particular, Mr. Pong states that “[b]ecause we have no Shared, Dirty or Inhibit
`
`bus lines . . . we cannot implement the E (Exclusive) state of the MESI protocol.”
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`Ex. 2024 at 7. The reason for this is straightforward—as the Pong patent
`
`publication discusses, the Pong architecture uses two separate sets of connections
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`for connecting the processors—a “memory control path” and a “data path.” Ex.
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`1003 ¶¶ 28-42. In Pong’s system “[t]he control path is implemented using an
`
`address bus or switch,” and the “data path” is “implemented with [its own] data
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`bus or switch .” Ex. 1003 ¶¶ 28-42; see also id. Fig. 3 (depicting separate “address
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`bus/switch” and “data bus/switch.”). The Pong article further explains that prior
`
`art systems using the full MESI protocol, including the Exclusive state, included
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`Shared and Dirty Buses. Ex. 2024 at 3. However, the Pong article teaches that the
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`limited point-to-point architecture of Pong does not have those buses or a point-to-
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`point equivalent. Ex. 2024 at 7. Thus, it is my opinion that the Pong system is not
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`readily adaptable to being modified to add an Exclusive state or being combined
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`
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`6
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`
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`with another reference using an Exclusive state to create a system which includes
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`Patent No. 7,296,121
`Case Nos. IPR2015-00158, -00159, -00163
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`an Exclusive state.
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`11.
`
`As to the limitation, “wherein said probe filtering unit is coupled to a
`
`coherent protocol interface and a non-coherent protocol interface,” based on the
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`prior art I have reviewed, I do not believe that such interfaces are taught in the art
`
`prior to November 4, 2002 (which I understand is the effective filing date of the
`
`proposed substitute claims). The closest prior art regarding these limitations I
`
`found in my review was several patents issued to Mr. David Glasco, one of the
`
`inventors of the ’121 Patent and assigned to Newisys, Inc. In particular, they are
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`U.S. Patent Nos. 7,103,725 (filed Mar. 22, 2002, published Sep. 25, 2003 as
`
`US2003/0182514, issued Sep. 5, 2006); 7,107,408 (filed Mar. 22, 2006, published
`
`Sep. 25, 2003 as US2003/0182508, issued Sep. 12, 2006); 7,107,409 (filed Mar.
`
`22, 2002, published Sep. 25, 2003 as US2003/0182509, issued Sep. 12, 2006);
`
`7,395,379 (filed May 13, 2002, published Nov. 13, 2003 as US 2003/0212741,
`
`issued Jul. 1, 2008); 7,653,790 (filed May 13, 2002, published Nov. 13, 2003 as
`
`US2003/0210655, issued Jan. 26, 2010); 7,251,698 (filed May 28, 2002, published
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`Dec. 4, 2003 as US2003/0225909, issued Jul. 31, 2007); 7,155,525 (filed May 28,
`
`2002, published Dec. 18, 2003 as US2003/0233388, issued Dec. 26, 2006);
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`7,281,055 (filed May 28, 2002, published Dec. 4, 2003 as 2003/0225938, issued
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`Oct. 9, 2007); 6,865,595 (filed May 28, 2002, published Dec. 4, 2003 as
`
`
`
`7
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`
`
`US2003/0225978, issued Mar. 8, 2005); and 7,103,636 (filed May 28, 2002,
`
`Patent No. 7,296,121
`Case Nos. IPR2015-00158, -00159, -00163
`
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`published Dec. 4, 2003 as US2003/0225979, issued Sep. 5, 2006). Each of these
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`discuss a coherent protocol interface and a non-coherent protocol interface, and
`
`have a figure identical to Figure 3 of the ’121 Patent. E.g. Ex. 2031 (U.S. Patent
`
`No. 6,865,595) at Fig. 3, 8:36-43 (“The cache coherence controller 230 is an
`
`Application Specific Integrated Circuit (ASIC) supporting the local point-to-point
`
`coherence protocol. The cache coherence controller 230 can also be configured to
`
`handle a non-coherent protocol to allow communication with I/O devices”.).
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`However, it is my opinion that none of these patents anticipates any of the
`
`proposed substitute claims because, for at least the reason that none of them teach
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`or discuss “probe filtering information representative of states associated with
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`selected ones of the cache memories.” I understand and am informed that these
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`patents to Mr. Glasco cannot be prior art to the substitute claims under an
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`obviousness combination due to their common ownership with the ’121 Patent.
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`12.
`
`Another reference which I believe reflects the state of the art of
`
`coherent and non-coherent interfaces in November 4, 2002 is Hellwagner et al.,
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`SCI: Scalable Coherent Interface (1999). This reference teaches:
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`[C]ache coherence protocols are provided as options only. A
`compliant SCI implementation need not cover coherence; an SCI
`network even cannot participate in coherence actions when it is
`
`
`
`8
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`
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`Patent No. 7,296,121
`Case Nos. IPR2015-00158, -00159, -00163
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`attached to the I/O bus . . .
`Ex. 2038 at 9. Thus, this reference appears to teach the use of a coherent interface
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`or a non-coherent interface, but suggests that a system cannot have both at once.
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`In particular the phrase that it “cannot participate in coherence actions when it is
`
`attached to the I/O bus” teaches that the system of Hellwagner may not be coupled
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`to a coherent interface while also being coupled to a non-coherent interface.
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`Moreover, the Hellwagner does not teach probe filtering.
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`13.
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`Thus, it is my opinion that the prior art of record to the ’121 Patent,
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`as well as the prior art known to the Patent Owner, as of November 4, 2002, does
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`not teach having a coherent protocol interface and a non-coherent protocol
`
`interface, and certainly does not teach coupling them to a probe filtering unit.
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`9
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`Case Nos. IPR2015-00158, -00159, -00163
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`Patent No. 7,296,121
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`I declare under penalty of perjury that the foregoing is true and correct.
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`Executed on: August 11, 2015
`
`<
`
`‘._
`
`r’ éfi.
`
`Vojin Oklobdzija, PhD
`
`
`
`Patent No. 7,296,121
`Case Nos. IPR2015-00158, -00159, -00163
`
`
`CERTIFICATE OF SERVICE
`
`The undersigned hereby certifies that a copy of the foregoing Declaration Of
`
`Vojin Oklobdzija, Ph.D. In Support Of Patent Owner’s Motions to Amend was
`
`served via email on August 11, 2015, on the attorneys for the Petitioners:
`
`W. Karl Renner, Reg. No. 41,265
`Roberto Devoto, Reg. No. 55,108
`3200 RBC Plaza
`60 South Sixth Street
`Minneapolis, MN 55402
`Phone: 202-783-5070
`Fax: 202-783-2331
`Email:
`IPR39521-0007IP1@fr.com
`
`
`IPR39521-0007IP2@fr.com
`
`
`IPR39521-0007IP3@fr.com
`
`
`IPR39521-0007IP4@fr.com
`
`
`renner@fr.com
`
`
`devoto@fr.com
`
`Lewis V. Popovski, Reg. No. 37,423
`Zaed M. Billah, Reg. No. 71,418
`Michael Sander, Reg. No. 71,667
`Kenyon & Kenyon LLP
`One Broadway
`New York, NY 10004
`Phone: 212-425-7200
`Fax: 212-425-5288
`Email:
`MemoryIntegrityv.Sony10760-225@kenyon.com
`lpopovski@kenyon.com
`zbillah@kenyon.com
`msander@kenyon.com
`
`
`
`
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`
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`11
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`
`
`Date: August 11, 2015
`
`
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`
`
`Patent No. 7,296,121
`Case Nos. IPR2015-00158, -00159, -00163
`
`
` /Michael D. Saunders/
`Michael D. Saunders, Admitted Pro
`Hac Vice
`
`12
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