Apple, Inc. et al. v. Memory Integrity, LLC
`and
`Sony Corp. et al. v. Memory Integrity, LLC
`
`IPR2015-00158, -00159, -00163
`U.S. Patent No. 7,296,121
`
`Patent Owner’s Demonstratives
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`www.FarneyDaniels.com | © Farney Daniels PC
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`1
`
`
`and
`Sony Corp. et al. v. Memory Integrity, LLC
`
`IPR2015-00158, -00159, -00163
`U.S. Patent No. 7,296,121
`
`Patent Owner’s Demonstratives
`
`www.FarneyDaniels.com | © Farney Daniels PC
`
`1
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`
`
`Overview
`• The references do not disclose the
`“states” limitation (cls. 1, 16, and 25)
`• The references do not disclose the
`“programmed” limitation (cl. 11)
`• The references do not disclose the
`“accumulating” limitation (cls. 13 and 25)
`
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`2
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`The “states” term
`• “a probe filtering unit which is operable to … transmit the probes …
`with reference to probe filtering information representative of
`states associated with selected ones of the cache memories”
`• ‘121 Pat. cl. 1
`• “ the probe filtering unit being operable to … transmit the probes …
`with reference to probe filtering information representative of
`states associated with selected ones of the cache memories”
`• ‘121 Pat. cl. 16
`• “evaluating the probe with the probe filtering unit …, the evaluating
`being done with reference to probe filtering information associated
`with the probe filtering unit and representative of states associated
`with selected ones of the cache memories”
`• ‘121 Pat. cl. 25
`
`
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`3
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`Construction of “states” term
`• ‘121 Patent is directed to the field of cache coherency
`
`‘121 Pat. at 1:26-27 (cited by PO Resp. at 3)
`
`‘121 Pat. at 2:39-42 (cited by PO Resp. at 3)
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`4
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`Construction of “states” term
`• In the field of cache coherency, “states” refers to cache
`coherency states
`
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`
`
`Oklobdzija PO Resp. Decl. ¶ 15 (-00159, Ex. 2016)
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`5
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`Construction of “states” term
`• Publications in the field of cache coherency equate “state”
`with the states of a cache coherence protocol
`
`
`. . .
`
`Sorin, et al. (2011) (Ex. 2010 at 88) (cited by PO Resp. at 4)
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`6
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`Construction of “states” term
`• Publications in the field of cache coherency equate “state”
`with the states of a cache coherence protocol
`
`
`Sorin, et al. (2011) (Ex. 2010 at 89) (cited by PO Resp. at 4)
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`7
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`Construction of “states” term
`• Publications in the field of cache coherency equate “state”
`with the states of a cache coherence protocol
`
`
`Sorin, et al. (2002) (Ex. 2006 at 1) (cited by PO Resp. at 4-5)
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`8
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`Construction of “states” term
`• ‘121 Patent uses the term “states” consistent with ordinary
`meaning in field of cache coherency to refer to cache
`coherency states
`
`
`. . .
`
`‘121 Pat. Fig. 7; 13:55-59 (cited by PO Resp. at 6,8)
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`9
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`
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`Construction of “states” term
`• ‘121 Patent uses the term “states” consistent with ordinary
`meaning in field of cache coherency to refer to cache
`coherency states
`
`
`‘121 Pat.
`Figs. 7,
`8; (cited
`by PO
`Resp. at
`6,8)
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`10
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`Construction of “states” term
`• The ‘121 Patent distinguishes presence “vectors” from “state”
`information
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`11
`
`‘121 Pat. Fig. 7, 13:55-57, 13:64-14:7
`(cited by PO Resp. at 8)
`
`
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`Koster does not disclose the “states” limitation
`• Koster does not disclose filtering probes based on
`“probe filtering information representative of” cache
`coherency states (PO Resp. at 21-24)
`• Tags stored in shadow tag memory are not
`representative of cache coherency states – tags
`merely provide address information (PO Resp. at 21)
`• Only discussion of cache coherency states in Koster:
`“the set-associative cache may use a MOESI (Modified Owner
`Exclusive Shared Invalid) cache-coherency protocol”
`(-00163 IPR, Ex. 1009 [Koster] at 6:35-38)
`“the second local cache memory is maintained using a MOESI
`cache-coherency protocol.”
`(id. at cls. 5, 14)
`
`12
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`Koster does not disclose the “states” limitation
`• Koster does not disclose filtering probes based on
`
`“probe filtering information representative of” cache
`coherency states (PO Resp. at 23-24)
`
`
`
`Oklobdzija PO Resp. Decl. ¶ 50 (-00159 IPR, Ex. 2016)
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`13
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`Pong does not disclose the “states” limitation
`• First, Pong’s presence bit vector cannot meet the
`“states” limitation because mere presence is not a
`cache coherency state. (PO Resp. at 25)
`• Second, contrary to Petitioners’ argument, Pong’s
`presence bit vector does not convey whether a line is in
`a “valid” state. (Id. at 25-27)
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`14
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`Pong does not disclose the “states” limitation
`• Pong does not mention any particular cache coherency
`states (e.g., MOESI)
`• Does not say that bit vector has “valid/invalid” state
`
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`15
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`
`
` Oklobdzija PO Resp. Decl. ¶ 89 (-00159 IPR, Ex. 2016)
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`Pong does not disclose the “states” limitation
`• Pong’s bit vector does not inherently disclose the
`“states” limitation in write update embodiments
`• Write-update protocols do not have valid/invalid states
`
`Oklobdzija
`PO Resp.
`Decl. ¶ 90
`(-00159
`IPR, Ex.
`2016)
`
`16
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`Oklobdzija PO Resp. Decl. ¶ 89 (-00163 IPR, Ex. 2016)
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`Pong does not disclose the “states” limitation
`• The “valid” / “write update” theory for Pong’s bit vector
`does not satisfy claim limitation as a whole
`
`
`
`Oklobdzija
`PO Resp.
`Decl. ¶ 90
`(-00159
`IPR, Ex.
`2016)
`
`
`
`• Petitioner’s expert does not respond to this point in his
`reply declaration
`
`17
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`The “programmed” term
`• “11. The computer system of claim 1 wherein each of the
`processing nodes is programmed to complete a memory
`transaction after receiving a first number of responses to a
`first probe, the first number being fewer than the number of
`processing nodes.” (‘121 Pat. cl. 11)
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`18
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`The “programmed” term
`• Claim 11 was instituted in -159 IPR on ground of anticipation over Pong
`• However, no express discussion of claim 11 in the Board’s Decision on
`Institution in the -159 IPR (-00159 IPR, Paper No. 12 at 23)
`
`• Claim 11 was instituted in -163 IPR on ground of anticipation over Koster
`•
`“On this record, we are persuaded by Petitioner’s logic that Koster
`inherently discloses that a microprocessor necessarily” performs the
`limitation
`“Patent Owner seems to suggest that Koster leaves open that the
`microprocessor could be configured to complete memory transactions
`using something other than programming, but Patent Owner does not
`hint at what this alternative method might be.” (-00163 IPR, Paper No. 18 at 21)
`
`• Same ground of anticipation over Koster for claim 11 was denied
`institution in -158 IPR
`• Noting “failure to address any programming in Koster, whether explicit
`or inherent” (-00158 IPR, Paper No. 7 at 20)
`
`•
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`19
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`The “programmed” term
`• Apple petitioners rely on inherency argument for
`“programmed” limitation for both Pong and Koster
`
`
`-00159 IPR, Pet. at 31
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`20
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`-00163 IPR, Pet. at 35
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`Central questions regarding “programmed”
`• As Board articulated, can a “microprocessor [] be configured to
`complete memory transactions using something other than
`programming”?
`• If so, then there is no proof that processors are inherently
`“programmed” in Pong and Koster, and no anticipation of
`claim 11 (-163 IPR, PO Resp. at 25-29; -159 IPR, PO Resp. at 30-33)
`
`• Should the term “programmed” as recited in claim 11 be
`construed to encompass all methods of configuring a
`processor (-163 IPR, PO Resp. at 25-29; -159 IPR, PO Resp. at 12-19)
`• Is “programmed” synonymous with “configured”?
`• Or, are some methods of configuring not within the scope
`of “programmed”?
`• Specifically, is “hard-wired logic” within the scope of
`“programmed”?
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`21
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`Oklobdzija
`PO Resp.
`Decl. ¶ ¶
`33, 38
`(-00159
`IPR, Ex.
`2016)
`
`Construction of the “programmed” term
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`22
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`Construction of the “programmed” term
`• “Programmed” requires configuration by a sequence of
`instructions, and does not include “hardwired” logic
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`(Decision
`on
`Institution,
`-00163
`IPR, Paper
`No. 18 at
`21 n.7 )
`
`Ex. 2014
`at 931
`(Merriam-
`Webster
`Collegiate
`Dictionary
`10th ed.)
`
`23
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`
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`Construction of the “programmed” term
`• “Programmed” requires configuration by a sequence of
`instructions, and does not include “hardwired” logic
`
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`Ex. 2012 at 359 (Microsoft Computer Dictionary)
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`Ex. 2012 at 214 (Microsoft Computer Dictionary)
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`24
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`Construction of the “programmed” term
`• “Programmed” requires configuration by a sequence of
`instructions, and does not include “hardwired” logic
`
`Ex. 2015 at 15/3 (ELECTRICAL ENGINEER’S REFERENCE BOOK, edited by M.A. Laughton, et al.)
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`25
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`Construction of the “programmed” term
`• “Programmed” requires configuration by a sequence of
`instructions, and does not include “hardwired” logic
`
`Ex. 2015 at 15/3 (ELECTRICAL ENGINEER’S REFERENCE BOOK, edited by M.A. Laughton, et al.)
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`26
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`Construction of the “programmed” term
`• “Programmed” requires configuration by a sequence of
`instructions, and does not include “hardwired” logic
`‘121 Pat. at 28:8-24
`(cited by -159 PO
`Resp. at 12)
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`27
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`Construction of the “programmed” term
`• Petitioners’ counter-argument: FPGAs are “programmable” but do
`not use instructions
`
`Horst Reply
`Decl. at ¶ ¶ 3,
`6 (Ex. 1025)
`
`
`
`• But Petitioner’s expert’s reply declaration does not address Board’s
`question of whether “microprocessor could be configured to
`complete memory transactions using something other than
`programming”
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`28
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`Construction of the “programmed” term
`• Petitioners’ argue that “programmed” should be construed as
`“designed to perform a sequence of operations,” (Ex. 1025 (Horst Reply
`Decl.) ¶ 6)
`• Thus, Petitioners argue that:
`
`Pet. Reply in -
`163 IPR at 14
`
`
`
`• Petitioners and their expert ignore the numerous technical
`dictionaries and treatises cited by Patent Owner and instead rely on
`a single general purpose dictionary definition in support of their
`construction
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`29
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`Koster and Pong do not disclose the “programmed”
`limitation
`• Koster and Pong do not provide any explicit or implicit
`disclosure that their processors are “programmed” to
`complete a memory transaction after receiving a first number
`of responses to a first probe.
`• As demonstrated by the Oklobdzija Declaration, processors
`can be configured to complete memory transactions after
`receiving a first number of responses without being
`“programmed” to do so, such as by the use of hard-wired
`logic. Oklobdzija PO Resp. Decl. ¶¶ 55-56, 101-102 (-00159 IPR, Ex. 2016)
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`30
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`The “accumulating” term
`• “15. The computer system of claim 1 wherein the probe
`filtering unit is operable to accumulate responses to each
`probe, and respond to requesting nodes in accordance with
`the accumulated responses.” (‘121 Pat. cl. 15)
`
`• “25. . . . transmitting the probe from the probe filtering unit
`only to selected ones of the processing nodes identified by the
`evaluating; accumulating probe responses from the selected
`processing nodes with the probe filtering unit;” (‘121 Pat. cl. 25)
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`31
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`The “accumulating” terms
`• Claim 15 was instituted in -159 IPR on a ground of anticipation
`over Pong
`• However, there was no express discussion of claim 15 in the
`Board’s Decision on Institution in the -159 IPR
`(-00159 IPR, Paper No. 12 at 23)
`
`• Claim 15 was denied institution in -158 and -163 IPRs on
`ground of anticipation over Koster
`• In the Decision on Institution, the Board found that Koster
`was not prior art with respect to claim 15
`• No express discussion of the interpretation of the
`“accumulating” terms or their application to the prior art
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`32
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`The “accumulating” term
`• Requires multiple responses to a “probe” be “accumulated”
`• Claims themselves recite “accumulate responses” and
`“accumulate responses to each probe”
`• Specification teaches multiple responses “accumulat[ed]”
`
`
`
`
`
`‘121 Pat. at 29:42-50 (cited by -159
`PO Resp. at 34)
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`33
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`The “accumulating” term
`
`
`
` • Petitioners argue that Pong must accumulate responses
`because responses must go through queues or FIFO buffers
`
`
`Pet. in -159
`IPR at 34-35
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`34
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`The “accumulating” term
`• But there is only one response to each probe in Pong
`
`
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`Pong ¶ 47
`(-00159
`IPR, Ex.
`1003)
`
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`
`
`Oklobdzija PO
`Resp. Decl. ¶
`109
`(-00159 IPR,
`Ex. 2016)
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`35
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`The “accumulating” term
`• But there is only one response to each probe in Pong
`
`
`
`Pong ¶ 13 (-00159
`IPR, Ex. 1003)
`
`
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`
`Oklobdzija PO Resp.
`Decl. ¶ 109
`(-00159 IPR, Ex.
`2016)
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`36
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`The “accumulating” term
`• FIFO Buffers do not necessarily accumulate
`
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`Oklobdzija PO Resp. Decl. ¶ 110 (-00159 IPR, Ex. 2016)
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`37
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`
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`Patent Owner’s Demonstratives
`for
`Motion to Amend
`
`IPR2015-00158, -00159, -00163
`U.S. Patent No. 7,296,121
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`38
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`Proposed Amendments
`• Patent Owner proposes amending claims 16-24
`
`• Each claim has been re-written in independent form,
`and then two additional limitations added:
`– “wherein said states comprise cache coherency states of a
`cache coherence protocol, and wherein said cache
`coherence protocol includes at least a modified state, an
`exclusive state, a shared state, and an invalid state” and
`– “wherein said probe filtering unit is coupled to a coherent
`protocol interface and a non-coherent protocol interface”
`• ‘159 IPR, claims appendix, cls. 26-34.
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`39
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`Prima Facie Showing of Patentability
`• The proposed claims have 112 support dating to the
`filing of the ‘347 Application
`– In the Decisions on Institution, the Board already found in
`the -159 and -163 IPR that the original claims 16-18 are
`supported by the ‘347 Application
`– Claims 19-24 are also supported by App. No. 10/156,893
`(which is incorporated by the ‘347 Appl. through further
`incorporation by reference in Appl. No. 10/157,388)
`
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`40
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`
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`Prima Facie Showing of Patentability
`• The proposed claims have 112 support dating to the
`filing of the ‘347 Application
`– Claims 19-24 are also supported by App. No. 10/156,893
`(which is incorporated by the ‘347 Appl. through further
`incorporation by reference in Appl. No. 10/157,388)
`
`
`
`Ex. 2022 (‘893 Appl.) at 21:18-22:4 (cited by Mtn. to Amend at 7)
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`41
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`
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`Prima Facie Showing of Patentability
`• The proposed claims have 112 support dating to the
`filing of the ‘347 Application
`– Claims 19-24 are also supported by App. No. 10/156,893
`(which is incorporated by the ‘347 Appl. through further
`incorporation by reference in Appl. No. 10/157,388)
`• The limitations on multiple incorporation by reference “do not apply
`to applications relied on only to establish an earlier effective filing
`date under 35 U.S.C. 119 or 35 U.S.C. 120.” M.P.E.P. § 608.1(p)(I)(B)
`(8th Ed., Rev. 2., May 2004); M.P.E.P. § 608.1(p)(2)(B) (9th Ed., ER9-
`07.2015, Oct. 2015).
`• “Incorporation by reference in the earlier application of . . . a U.S.
`patent or application which itself incorporates ‘essential material’ by
`reference . . . is not critical in the case of a ‘benefit’ application.” Id.
`– PO Mtn. to Amend Reply at 1-2
`
`42
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`Prima Facie Showing of Patentability
`• The proposed claims have 112 support dating to the
`filing of the ‘347 Application
`– The ‘347 Application discloses “wherein said states
`comprise cache coherency states of a cache coherence
`protocol, and wherein said cache coherence protocol
`includes at least a modified state, an exclusive state, a
`shared state, and an invalid state”
`
`
`
`
`‘347 Appl. at 22:8-10(cited by Mtn. to Amend at 9)
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`43
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`
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`Prima Facie Showing of Patentability
`• The ‘347 Application discloses
`“wherein said probe filtering unit is
`coupled to a coherent protocol
`interface and a non-coherent
`protocol interface”
`
`
`
`
`
`
`‘347 Appl. at Fig. 3 (cited by Mtn. to Amend at 9-10)
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`
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`Prima Facie Showing of Patentability
`• The ‘347 Application discloses “wherein said probe filtering
`unit is coupled to a coherent protocol interface and a non-
`coherent protocol interface”
`
`
`‘347 Appl. at 11:13-14(cited by Mtn. to Amend at 9-10)
`
`
`
`
`
`‘347 Appl. at 12:4-10(cited by Mtn. to Amend at 9-10, PO Reply in Sup. Amend at 7)
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`Prima Facie Showing of Patentability
`• Patent Owner’s expert performed the required prima
`facie showing of patentability of the proposed
`substitute claims
`
`
`Oklobdzija Mtn. to Amend. Decl ¶ 8 (Ex. 2019)
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`46
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`
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`Prima Facie Showing of Patentability
`• Patent Owner’s expert identified the art reviewed
`
`
`Oklobdzija Mtn.
`to Amend. Decl ¶
`7 (Ex. 2019)
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`47
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`
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`Prima Facie Showing of Patentability
`• Patent Owner’s expert discussed the closest prior art
`
`
`Oklobdzija Mtn.
`to Amend. Decl ¶
`9 (Ex. 2019)
`
`Oklobdzija Mtn.
`to Amend. Decl ¶
`11 (Ex. 2019)
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`48
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`
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`Prima Facie Showing of Patentability
`• Patent Owner’s expert identified state of the art
`
`
`Oklobdzija Mtn.
`to Amend. Decl ¶
`12 (Ex. 2019)
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`49
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`
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`SGI Origin Does not teach the substitute claims
`• Petitioners are unclear whether Origin’s “hub” chip—alleged probe
`filtering unit—is inside or outside of the alleged “processing node”
`
`
`Oklobdzija
`Reply
`Decl. ¶ 10
`(Ex. 2042)
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`50
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`
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`SGI Origin Does not teach the substitute claims
`• “Hub” chip outside of “processing node” also fails to read on the
`substitute claims
`
`
`Oklobdzija
`Reply
`Decl. ¶ 12
`(Ex. 2042)
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`51
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`
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`SGI Origin Does not teach the substitute claims
`• Alleged PFU does not “receive probes . . . from processing nodes,” it
`receives it from another hub
`
`
`Horst Opp. Decl. ¶ 8 (additional annotation in green)
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`52
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`
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`SGI Origin Does not teach the substitute claims
`• Alleged “probe” sent by request node’s hub chip cannot be said to
`be the same as what the request node’s processor sends
`
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`Oklobdzija Reply Decl. ¶ 13 (Ex. 2042)
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`53
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`
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`SGI Origin Does not teach the substitute claims
`• Alleged “probe” sent by request node’s hub chip cannot be said to
`be the same as what the request node’s processor sends
`
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`54
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`Culler at 616, Fig. 8.21;
`Oklobdzija Reply Decl. ¶ 13 (Ex. 2042)
`
`
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`SGI Origin Does not teach the substitute claims
`• No point-to-point architecture—Origin’s processors only connected
`through a “SysAD” bus and “hub” chips—none connected “directly”
`
`
`’121 Pat. at 4:38-42 (cited by PO Mtn. to Amend Reply at 10)
`
`Oklobdzija Reply Decl. ¶ 13 (Ex. 2042)
`
`www.FarneyDaniels.com | © Farney Daniels PC
`
`55
`
`Culler at 598, Fig. 8.15
`
`
`
`SGI Origin Does not teach the substitute claims
`• Origin’s hub chip is not coupled to a coherent protocol interface and
`a non-coherent protocol interface
`
`
`Oklobdzija Reply Decl. ¶ 15 (Ex. 2042)
`www.FarneyDaniels.com | © Farney Daniels PC
`
`56
`
`
`
`SGI Origin Does not teach the substitute claims
`• Origin’s hub chip is not coupled to a coherent protocol interface and
`a non-coherent protocol interface
`
`
`. . .
`
`Oklobdzija Reply Decl. ¶ 15 (Ex. 2042)
`
`www.FarneyDaniels.com | © Farney Daniels PC
`
`57
`
`
`
`SGI Origin Does not teach the substitute claims
`• Origin’s hub chip is not coupled to a coherent protocol interface and
`a non-coherent protocol interface
`
`
`Oklobdzija Reply Decl. ¶ 15 (Ex. 2042)
`
`www.FarneyDaniels.com | © Farney Daniels PC
`
`58
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