Paper No. ____
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`_____________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________________________
`
`HUGHES NETWORK SYSTEMS, LLC and
`HUGHES COMMUNICATIONS, INC.,
`Petitioner,
`
`v.
`
`CALIFORNIA INSTITUTE OF TECHNOLOGY,
`Patent Owner.
`_____________________________
`
`Case IPR2015-00059
`Patent 7,916,781
`_____________________________
`
`
`
`DECLARATION OF SOLOMON W. GOLOMB, PH.D. IN SUPPORT OF
`PATENT OWNER’S RESPONSE TO INTER PARTES REVIEW OF
`U.S. PATENT NO. 7,916,781
`
`CALTECH - EXHIBIT 2024
`
`
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`_____________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________________________
`
`HUGHES NETWORK SYSTEMS, LLC and
`HUGHES COMMUNICATIONS, INC.,
`Petitioner,
`
`v.
`
`CALIFORNIA INSTITUTE OF TECHNOLOGY,
`Patent Owner.
`_____________________________
`
`Case IPR2015-00059
`Patent 7,916,781
`_____________________________
`
`
`
`DECLARATION OF SOLOMON W. GOLOMB, PH.D. IN SUPPORT OF
`PATENT OWNER’S RESPONSE TO INTER PARTES REVIEW OF
`U.S. PATENT NO. 7,916,781
`
`CALTECH - EXHIBIT 2024
`
`
`
`
`
`I.
`
`II.
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`TABLE OF CONTENTS
`TABLE OF CONTENTS
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`QUALIFICATIONS ........................................................................................ 1
`QUALIFICATIONS ...................................................................................... ..1
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`SCOPE OF WORK.......................................................................................... 4
`SCOPE OF WORK........................................................................................ ..4
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`III. LEGAL STANDARDS ................................................................................... 4
`III.
`LEGAL STANDARDS ................................................................................. ..4
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`IV. LEVEL OF ORDINARY SKILL AND RELEVANT TIME ......................... 5
`IV.
`LEVEL OF ORDINARY SKILL AND RELEVANT TIME ....................... ..5
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`V.
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`CLAIM CONSTRUCTION ............................................................................ 5
`CLAIM CONSTRUCTION .......................................................................... ..5
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`VI. CLAIMS 1 AND 2 ARE NOT ANTICIPATED BY DIVSALAR ............... 21
`VI.
`CLAIMS 1 AND 2 ARE NOT ANTICIPATED BY DIVSALAR ............. ..21
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`VII. CONCLUDING STATEMENTS .................................................................. 27
`VII.
`CONCLUDING STATEMENTS ................................................................ ..27
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`-i-
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`I, Solomon W. Golomb, declare as follows:
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`I.
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`QUALIFICATIONS
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`1. My name is Solomon Golomb. I am a Distinguished and University
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`Professor of Electrical Engineering and Mathematics at the University of Southern
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`California (“USC”). I received my B.A. in Mathematics from Johns Hopkins
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`University in 1951 and my M.S. in Mathematics from Harvard University in 1953.
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`I received my Ph.D. in Mathematics from Harvard University in 1957.
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`2.
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`For over sixty years I have conducted research in the field of
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`communication systems and signals. Following completion of my Ph.D. thesis, I
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`worked at NASA’s Jet Propulsion Laboratory (“JPL”) in Pasadena, California from
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`1956 to 1963, initially as a Senior Research Engineer and eventually as a Deputy
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`Section Chief of the Telecommunications Research Section.1 At JPL, I was one of
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`the leaders of their space communications efforts and I played a key role in
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`formulating the design of deep-space communications for subsequent lunar and
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`planetary explorations.
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`3.
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`In 1963 I joined USC as a professor. Throughout the past five
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`decades I have taught courses and conducted research in Electrical Engineering
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`and Mathematics. My areas of research have included communication systems and
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`signals, including space-communications technology and radar and sonar signals,
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`
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`1 NASA’s Jet Propulsion Laboratory (JPL) is a division of the California
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`Institute of Technology.
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`as well as coding for reliability, security, data compression, and synchronization. I
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`am recognized for my work with shift register sequences, or pseudorandom
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`sequences, which have extensive applications in radar, space communications,
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`cryptography, and now cell phone communications. I also developed what came to
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`be known as Golomb Coding, a lossless data compression method using codes I
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`developed in the 1960s. My efforts in these fields have helped make USC a center
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`for communications research.
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`4.
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`From 1995 to 1998 I was the Director of Technology for the
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`Annenberg Center of Communication at USC. I received the USC Presidential
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`Medallion in 1985 and was awarded the title of University Professor in 1993. In
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`1999 I was appointed as the first holder of the Andrew and Erna Viterbi Chair in
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`Communications for the USC Viterbi School of Engineering. In 2008 I was named
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`a USC Distinguished University Professor.
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`5.
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`I am the author or co-author of a number of books on communications
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`and coding theory, including Digital Communications with Space Applications
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`(originally published in 1964, revised edition published in 1982), Shift Register
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`Sequences (originally published in 1967, revised edition published in 1982), Basic
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`Concepts in Information Theory and Coding (1994), and Signal Design for Good
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`Correlation: For Wireless Communication, Cryptography, and Radar (2005). In
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`1987 I contributed a chapter on error correcting codes to the TIME-LIFE book
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`Understanding Computers: Memory and Storage.
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`6.
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`In addition to these books, I have authored or co-authored hundreds of
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`other publications on communications systems and signals, coding theory, and
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`mathematics, including works specifically directed to error correcting codes. I
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`have presented lectures regarding error correcting codes at academic conferences
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`and symposiums, including the National Computer Conference and the
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`Symposium on Applications of Algebra to Error-Correcting Codes.
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`7.
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`In addition to my posts at USC, I have received numerous awards and
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`recognition for my contributions to the field of communication systems and
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`signals. In 2013, I received the National Medal of Science, the highest honor
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`bestowed by the United States for scientific innovation, from President Obama for
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`my advances in mathematics and communications. I was elected to the National
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`Academy of Engineering in 1976 and to the National Academy of Sciences in
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`2003. I was named a Fellow of the Institute of Electrical and Electronics
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`Engineers (“IEEE”) in 1982 and subsequently received the IEEE Shannon Award
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`of the Information Theory Society. In 2000 I received the Richard W. Hamming
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`Medal of the IEEE. The Hamming Medal is named after a pioneer in the
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`development of computer science and error correcting codes in particular, and is
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`awarded for exceptional contributions to information sciences, systems, and
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`technology. I have been a Foreign Member of the Russian Academy of Natural
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`Science since 1994. I was appointed a Fellow of the American Mathematical
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`Society in 2012 and a Fellow of the Society for Industrial and Applied
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`Mathematics in 2013.
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`8.
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`A copy of my curriculum vitae is attached as Exhibit 2029.
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`II.
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`SCOPE OF WORK
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`9.
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`I understand that a petition (Paper 1) was filed with the United States
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`Patent and Trademark Office for inter partes review of U.S. Patent No. 7,916,781
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`(“’781 patent,” Ex. 1005).
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`10.
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`I further understand that the Patent Trial and Appeal Board (“PTAB”
`
`or the “Board”) has decided to institute inter partes review (Paper 18) of claims 1
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`and 2 of the ’781 patent under 35 U.S.C. § 102 based on Divsalar (Ex. 1011).
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`11.
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`I have been specifically asked to provide my expert opinions on the
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`validity of claims 1 and 2 of the ’781 patent. In connection with this analysis, I
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`have reviewed the ’781 patent as well as the Divsalar reference. I have also
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`reviewed and considered Board’s Decision on Institution of Inter Partes Review,
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`and may cite to them in this declaration.
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`III. LEGAL STANDARDS
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`12.
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`I understand that a claim is not patentable under 35 U.S.C. §102, for
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`lack of novelty, if each and every element of the claim is found, either expressly or
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`inherently described, in a single prior art reference. I understand that such a claim
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`can be considered “anticipated” by the prior art reference.
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`13.
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`I understand that to establish anticipation by inherency, the inherent
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`teaching must necessarily result from the description in the prior art reference. The
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`mere possibility that a certain thing may result from a given set of circumstances is
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`not sufficient to demonstrate inherency.
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`14.
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`I understand that the claims of a patent are analyzed from the
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`perspective of a “person of ordinary skill in the art” at the time the invention was
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`made.
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`IV. LEVEL OF ORDINARY SKILL AND RELEVANT TIME
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`15.
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`I understand that the application that led to the ’781 patent was filed
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`on June 30, 2008. I understand that the ’781 patent claims priority to provisional
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`application No. 60/205,095, filed on May 18, 2000.
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`16.
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`I have been advised that “a person of ordinary skill in the relevant
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`field” is a hypothetical person to whom one could assign a routine task with
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`reasonable confidence that the task would be successfully carried out. I have been
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`advised that the relevant timeframe is prior to May 18, 2000.
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`17. By virtue of my education, experience, and training, I am familiar
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`with the level of skill in the art of the ’781 patent prior to May 18, 2000.
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`18.
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`In my opinion, a person of ordinary skill in the relevant field prior to
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`May 18, 2000 would include someone who had, through education or practical
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`experience, the equivalent of a master’s degree in electrical engineering or
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`mathematics, and three to four years of work or research experience in the field of
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`error control coding, or a Ph.D. in electrical engineering or mathematics, with at
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`least two years of experience in error control coding.
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`V. CLAIM CONSTRUCTION
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`19.
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`I have been advised that, in the present proceeding, the ’781 patent
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`claims are to be given their broadest reasonable interpretation in view of the
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`specification. I also understand that, at the same time, absent some reason to the
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`contrary, claim terms are typically given their ordinary and accustomed meaning as
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`would be understood by one of ordinary skill in the art. I further understand that
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`the terminology in the specification and the claims need not be the same. I have
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`followed these principles in my analysis throughout this declaration. I discuss
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`some terms below and what I understand as constructions of these terms.
`A.
`“first encoding operation being a linear transform operation that
`generates L transformed bits”
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`20. Claim 1 of the ’781 patent recites the term “the first encoding
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`operation being a linear transform operation that generates L transformed bits.” A
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`person of ordinary skill would look to the specification of the ’781 patent to
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`understand what this term means.
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`21. The specification consistently refers to the invention as comprising
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`two main aspects: an “outer coder” and an “inner coder.” For example, the
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`Abstract begins by stating that “[a] serial concatenated coder includes an outer
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`coder and an inner coder.” Ex. 1005 at Abstract. Similarly, the Summary section
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`of the ’781 patent describes the claimed coding system as made up of the same two
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`“outer coder” and “inner coder” components. Ex. 1005 at 1:63-2:10. In the coding
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`system described in the ’781 patent, it is clear that the signal to be encoded is first
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`operated on by the outer coder, whose output is then further processed by the inner
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`coder. For example, both the Abstract and Summary of the invention state that the
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`repeated and scrambled bits generated by the outer coder are then input to the inner
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`coder. Accordingly, a person of ordinary skill in the art would understand that the
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`“first encoding operation . . .” recited in claim 1 refers to the “outer coder”
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`discussed throughout the specification, while the “second encoding operation . . .”
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`discussed below corresponds to the “inner coder.”
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`22. A person of ordinary skill, upon reading the specification, would
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`understand that the outer coder must include irregular repetition of input bits.
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`Indeed, this is an essential aspect of the invention described in the ’781 patent, as
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`the specification consistently explains. For example, the Abstract contains just
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`three sentences. As mentioned above, the first sentence explains that the invention
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`“includes an outer coder and an inner coder.” Id. at Abstract. The second sentence
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`describes the outer coder while the last sentence describes the inner coder. Id.
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`With respect to the outer coder, the Abstract explains that irregular repetition is
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`one of two key functions it performs, along with bit scrambling: “[t]he outer coder
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`irregularly repeats bits in a data block according to a degree profile and scrambles
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`the repeated bits.” Id.
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`23. The Summary of the invention provides a bit more detail regarding
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`the repetition and scrambling operations performed by the outer coder, and
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`similarly shows that irregular repetition is an essential aspect. It explains that
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`“[t]he data block is apportioned into two or more sub-blocks, and bits in different
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`sub-blocks are repeated a different number of times according to a selected degree
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`profile.” Id. at 1:67-2:2. Nothing in the Summary mentions regular
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`repetition(such as repeating all bits the same number of times) or would lead a
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`person of ordinary skill in the art to believe that irregular repetition is an optional
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`aspect of the invention. Rather, it is clear that irregular repetition is a central
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`feature of the outer coder and of the invention itself.
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`-7-
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`24. The remaining portion of the specification supports the conclusion
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`that the “first encoding operation” must utilize irregular repetition. In fact, the
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`invention is referred to throughout the specification as an “Irregular Repeat and
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`Accumulate” (IRA) coder. For example:
`• “FIG. 3 is a Tanner graph for an irregular repeat and accumulate
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`(IRA) coder.” (2:24-25);
`• “FIG. 4 is a schematic diagram of an IRA coder according to an
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`embodiment.” (2:26-27);
`• “The serial concatenation of the interleaved irregular repeat code and
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`the accumulate code produces an irregular repeat and accumulate
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`(IRA) code.” (3:34-36);
`• “Two types of IRA codes are represented in FIG. 3, a nonsystematic
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`version and a systematic version.” (4:25-26);
`• “The IRA code may be represented by an alternate notation” (4:50-
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`51);
`• “‘Belief propagation’ on the Tanner Graph realization may be used to
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`decode IRA codes.” (5:13-14); and
`• “IRA codes may be implemented in a variety of channels, including
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`memoryless channels, such as the BEC, BSC, and AWGN, as well as
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`channels having a non-binary input, non-symmetric and fading
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`channels, and/or channels with memory.” (7:4-18).
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`25.
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`In light of the patentee’s decision to refer to the invention as an
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`Irregular Repeat and Accumulate code, a person of ordinary skill in the art would
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`understand that irregular repetition is a core component of the invention and would
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`not interpret the claims in a way that did not require irregular repetition.
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`26. Moreover, the described embodiments, Tanner graph representation,
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`and discussion of decoding the information after it is encoded all consistently refer
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`to the invention as utilizing irregular repetition in the outer encoder. For example,
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`the Detailed Description describes two primary embodiments of the coding system:
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`one where the outer coder includes a repeater and an interleaver (discussed at 2:39-
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`3:33) and an alternative one where those two elements are replaced by a low-
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`density generator matrix (discussed at 3:62-4:3). Each of these is discussed purely
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`in terms of requiring irregular repetition.
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`27. With respect to the repeater/interleaver embodiment, depicted in
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`Figure 2, the Summary states that the repeater repeats bits irregularly, explaining
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`that the outer coder in this embodiment utilizes “a repeater with a variable rate.”
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`Id. at 2:3-4. The specification also states that the repeater in this embodiment
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`“may be irregular, that is, the value of T0 is not constant, and may differ for sub-
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`blocks of bits in the data block.” (2:54-56). The specification goes on to explain
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`the irregular repetition operation in more detail:
`Since the repeater has an irregular output, different bits in the block
`may be repeated a different number of times. For example, a fraction
`of the bits in the block may be repeated two times, a fraction of bits
`may be repeated three times, and the remainder of bits may be
`repeated four times. These fractions define a degree sequence, or
`degree profile, of the code.”
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`Id. at 2:58-64.
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`28. While the discussion of the repeater/interleaver embodiment does
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`mention that the repeater “may” be irregular, this would not indicate to a person of
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`ordinary skill in the art that the invention claimed in the ’781 patent encompasses a
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`repeater lacking irregular repetition. Taking the specification as a whole into
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`consideration, it is clear that irregular repetition is a required aspect. Moreover, I
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`note that the block quote above states that a repeater with an irregular output
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`“may” repeat different bits in the block a different number of times. The
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`specification uses “may” to indicate that variable numbers of repeats are possible,
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`for example that two repeats may be possible, three repeats maybe possible, etc.
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`It does not appear to me that the specification uses “may” to indicate that the
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`irregular repetition aspect of the described invention itself is optional.
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`29. Turning to the embodiment that replaces the repeater and interleaver
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`with a low-density generator matrix, the specification again describes irregular
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`repetition as required, stating “[i]n an alternate embodiment, the outer coder 202
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`may be a low-density generator matrix (LDGM) coder that performs an irregular
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`repeat of the k bits in the block, as shown in FIG. 4.” Id. at 3:62-64. In the Brief
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`Description of the Drawings, the specification refers to this Figure 4 as “a
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`schematic diagram of an IRA coder.” Id. at 2:26-27. The specification does not
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`describe this invention as including, or even possibly including, regular repetition
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`instead of irregular repetition.
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`30.
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`In addition to the two primary embodiments, the specification
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`provides a Tanner graph, seen in Figure 3, in which the “IRA code is . . .
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`represented as a set of parity checks . . . in a bipartite graph.” Id. at 3:34-40. A
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`person of ordinary skill in the art would be familiar with Tanner graphs and their
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`use to depict the constraints that define a class of error correction codes. The ’781
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`patent presents a single Tanner graph for its invention, and that graph is for an
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`irregular repeat code where fractions of the overall number of information bits are
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`repeated different times:
`FIG. 3 shows a Tanner graph 300 of an IRA code with parameters (f1,
`. . . , fj; a) where fi≥0, ∑ifi=1 and “a” is a positive integer. . . . Each
`information node 302 is connected to a number of check nodes 304.
`The fraction of information nodes connected to exactly i check nodes
`is fi. For example, in the Tanner graph 300, each of the f2 information
`nodes are connected to two check nodes, corresponding to a repeat of
`q=2, and each of the f3 information nodes are connected to three check
`nodes, corresponding to q=3.
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`Id. at 3:40-55.
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`31. This irregular repetition is further seen in Figure 3 itself, which I have
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`annotated below:
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`As can be seen in this example, the figure depicts many example subgroups of
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`input bits corresponding to information nodes, called “variable nodes.” One such
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`example subgroup is designated as the fraction f2, in which the input bits are
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`repeated twice, such that each of the information nodes in the fraction f2 set are
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`connected to two check nodes. In another of the example subgroups, designated as
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`the fraction f3, each of the input bits corresponding to the information nodes in the
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`fraction set are repeated three times, such that each of those information nodes is
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`connected to three check nodes. This optionally continues on through additional
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`fractions of increased repetitions, as represented by the fraction fj whose nodes are
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`connected to “j” check nodes. The ’781 patent contains no other Tanner graphs,
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`nor does the description of Figure 3 mention utilizing regular repetition, which is
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`unsurprising given that the Figure presents “a Tanner graph 300 of an IRA code.”
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`Id. at 3:40-41.
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`32. The ’781 patent also refers exclusively to irregular repetition when
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`discussing decoding the output of the invention. The decoding discussion appears
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`at 5:13-7:4. The introduction to this section of the specification plainly states that
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`it pertains to irregular repetition codes: “‘Belief propagation’ on the Tanner graph
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`realization may be used to decode IRA codes.” The specification then goes on to
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`explain this belief propagation decoding method, without ever mentioning the
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`prospect of decoding a code utilizing regular repetition.
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`33. Similarly, the specification mentions an “iterative decoding” in the
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`context of a number of various “memoryless channel models,” including “a binary
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`erasure channel (BEC); a binary symmetric channel (BSC); and an additive white
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`Gaussian noise (AWGN) channel.” Id. at 5:61-65. The specification never
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`indicates the invention encompasses regular repetition when utilized with respect
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`to any of these channels, and in fact reiterates the irregular repetition aspect
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`regardless of channel: “IRA codes may be implemented in a variety of channels,
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`including memoryless channels, such as the BEC, BSC, and AWGN, as well as
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`channels having non-binary input, nonsymmetric and fading channels, and/or
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`channels with memory.” Id. at 7:14-18.
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`34. While the specification refers throughout to the irregular repetition
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`component of the invention, it mentions regular repetition just once, stating at
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`4:44-49 that “regular repeat and accumulate (RA) codes can be considered
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`nonsystematic IRA codes with a=1 and exactly one fi equal to say fq=1, and the rest
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`zero, in which case Rnsys simplifies to R=1/q.” A person of ordinary skill in the art
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`would not take this to be an indication that the invention described in the patent
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`extends to outer coders utilizing regular repetition. Instead, this passage serves to
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`highlight and explain the differences between IRA codes and a similar—but
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`significantly different—code lacking irregularity. This passage explains a
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`fundamental distinction between IRA and RA codes, by pointing out that
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`eliminating all information node fractions but one would necessarily result in a
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`code that repeats all information bits the same number of times (i.e., exactly one fi
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`equal to 1”).
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`35.
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`In sum, the ’781 patent specification consistently refers to the
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`invention as an Irregular Repeat and Accumulate (IRA) code and, consistent with
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`its name, describes the invention in a way that makes it clear to a person of
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`ordinary skill in the art that irregular repetition is a necessary core component of
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`the coding scheme. Specifically, the outer coder is described exclusively in terms
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`of utilizing irregular repetition. A person of ordinary skill in the art would not
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`interpret the claims in a way that did not include this essential component of the
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`invention. Accordingly, it is my opinion that the term “the first encoding operation
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`being a linear transform operation that generates L transformed bits” should be
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`construed to require an encoding operation that irregularly repeats bits in a data
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`block and scrambles the repeated bits.
`B.
`“the second encoding operation including an accumulation
`operation in which the L transformed bits generated by the first
`encoding operation are accumulated”
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`36. Claim 1 of the ’781 patent recites the term “the second encoding
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`operation including an accumulation operation in which the L transformed bits
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`generated by the first encoding operation are accumulated.” A person of ordinary
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`skill would look to the specification of the ’781 patent to understand what this term
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`means.
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`37. As discussed above (see ¶¶ 21-22), the specification consistently
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`refers to the invention as being comprised of an outer coder and an inner coder.
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`While the outer coder carries out the irregular repeat and bit scrambling functions
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`described in the specification, the Summary of the invention explains that “[t]he
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`repeated and scrambled bits are input to an inner coder that has a rate substantially
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`close to one.” Id. at 2:7-8. The Summary further describes the inner coder by
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`stating that it “may include one or more accumulators that perform recursive
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`modulo two addition operations on the input bit stream.” Id. at 2:8-10. This
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`description is consistent with the claim limitation requirement that the “L
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`transformed bits” generated by the first encoding operation (i.e., outer coder) be
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`“accumulated.” Accordingly, a person of ordinary skill would understand that this
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`limitation corresponds to the inner coder described in the specification.
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`38. The specification explains that the inner coder “is an accumulator,
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`which produces outputs that are the modulo two (mod-2) partial sums of its
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`outputs.” Id. at 3:3-5. It further explains that “[a]n advantage of this system is that
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`only mod-2 addition is necessary for the accumulator. The accumulator may be
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`embodied using only XOR gates, which may simplify the design.” Id. at 3:25-28.
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`A person of ordinary skill would understand, therefore, that the specific
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`accumulator design the specification discloses is a key element of the invention.
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`39. As with the outer coder, Figure 3 and the corresponding description
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`provides an example of the inner coder/accumulator aspect of the IRA code
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`invention. As I discussed above, the specification states that “FIG. 3 shows a
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`Tanner graph 300 of an IRA code with parameters (f1, . . . , fj; a) where fi≥0, ∑ifi=1
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`and ‘a’ is a positive integer.” Id. at 3:40-42. The accumulation operation is
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`represented by the “check nodes” depicted in Figure 3. These check nodes are
`
`“connected between the information nodes and parity nodes” (3:46-48) and,
`
`notably, each check node is connected to multiple information nodes:
`Each check node 304 is connected to exactly “a” information nodes
`302. In FIG. 3, a=3. These connections can be made in many ways,
`as indicated by the arbitrary permutation of the ra edges in joining
`information nodes 302 and check nodes 304 in permutation block 310.
`These connections correspond to the scrambling performed by the
`interleaver 204.
`
`3:56-61. In other words, the accumulation operation disclosed in the representative
`
`example in Figure 3 involves an accumulation of the values of, for example, three
`
`information nodes at each respective check node.
`
`-16-
`
`
`
`
`
`40. This can be further seen in Figure 3 itself, which I have further
`
`annotated below:
`
`
`41. As can be seen in this example, the first step of the accumulation
`
`operation involves a mod-2 or exclusive-OR addition of the values of the input bits
`
`corresponding to the information nodes connected to check node v1 (represented by
`
`the lines on the left side of the filled circle labeled v1), resulting in an output bit
`
`corresponding to parity node x1. Note that while no lines are drawn directly
`
`between the information nodes and check nodes due to the “arbitrary permutation
`
`of the ra edges in joining information nodes 302 and check nodes 304,” (3:58-60)
`
`provided by the “random permutation” element, the check nodes are in fact
`
`-17-
`
`
`
`
`
`connected to “a” information nodes, depicted here in this example as a=3. I also
`
`note that the elipses between the edges connected to the check nodes indicate to a
`
`person of ordinary skill that other values of “a” are possible, as discussed below
`
`with respect to Table 1of the ’781 patent, below.
`
`42. The second step of the accumulation operation performs an addition
`
`of the earlier output x1 and the values of the input bits corresponding to the
`
`additional information nodes connected to check node v2. This results in an output
`
`bit corresponding to parity node x2. The accumulation operation continues on in
`
`this fashion, each time adding the values of the bits corresponding to the
`
`information nodes connected to a particular check node to the previously generated
`
`output value.
`
`43. Aside from Figure 3 and its description, the specification elsewhere
`
`describes the accumulation operation as involving addition of multiple information
`
`bit values in each accumulation step. For example, Table 1 “shows degree profiles
`
`that have been found to produce good results for an AWGN channel model” of the
`
`IRA code (id. at 6:41-42):
`
`-18-
`
`
`
`
`
`
`44. The specification explains that Table 1 illustrates degree profiles
`
`involving connections between two, three, and four information nodes and a check
`
`node: “Table 1 shows degree profiles yielding codes of rate approximately 1/3 for
`
`the AWGN channel and with a=2, 3, 4.” Id. at 6:62-63. Importantly, the
`
`specification goes on to state that “[a]s the parameter ‘a’ is increased, the
`
`performance improves. For example, for a=4, the best code found has an iterative
`
`decoding threshold of Eb/No=-0.371 dB, which is only 0.12 dB above the Shannon
`
`limit.” Id. at 7:1-4.
`
`45. The specification’s disclosure that performance of the IRA code
`
`improves as the value of “a” increases demonstrates the benefit of adding multiple
`
`information bits at each step of the accumulation operation. Increasing the value
`
`of “a,” and thereby increasing the number of information bits involved in each
`
`addition operation during the accumulation, improves the distribution of potential
`
`errors in a way that makes it much more likely the error correction will work. In
`
`-19-
`
`
`
`
`
`practice, it is more likely that errors will occur in adjacent bits rather than spread
`
`evenly throughout the signal. The combination of the random permutation and
`
`multi-bit accumulation disclosed in the specification increases the likelihood that
`
`those errors will be detected.
`
`46. Not only does the specification state that higher values of “a” are
`
`preferable to lower values, but Table 1 does not even present a=1 as an option. In
`
`fact, the ’781 patent does not discuss an IRA code embodiment utilizing a=1
`
`anywhere in the specification. The only instance where the ’781 patent
`
`specification discusses a code utilizing a=1 is when it distinguishes the IRA code
`
`accumulation operation as described with respect to Figure 3 from an accumulation
`
`operation used in regular repeat and accumulate codes. An RA code would not
`
`utilize connections to multiple information nodes at each check node. Rather,
`
`“regular repeat and accumulate (RA) codes can be considered nonsystematic IRA
`
`codes with a=1 and exactly one fi equal to say fq=1, and the rest zero, in which case
`
`Rnsys simplifies to R=1/q.” Id. at 4:46-49. Having the parity bits used for error
`
`correction randomly scattered throughout a block of data helps to insure that a
`
`block or cluster of errors will be successfully detected and corrected. In other
`
`words, because in an RA code “a=1,” such a code differs from the IRA code
`
`described in the ’781 patent because each parity bit is merely the sum of the prior
`
`parity bit and a single information bit, rather than multiple information bits as in
`
`the IRA code.
`
`47. The specification consistently describes the IRA code invention as
`
`including an accumulation operation involving connections between multiple
`
`-20-
`
`
`
`
`
`information nodes and a single check node. It distinguishes this from an RA code,
`
`where the accumulation operation involves a single connection to an information
`
`node for each check node. Accordingly, a person of ordinary skill would
`
`understand the term “the second encoding operation including an accumulation
`
`operation in which the L transformed bits generated by the first encoding operation
`
`are accumulated,” in view of the specification, to require addition of a previously
`
`generated parity bit and more than one input bit in order to generate a second parity
`
`bit.
`
`VI. CLAIMS 1 AND 2 ARE NOT ANTICIPATED BY DIVSALAR
`
`48. As explained below, it is my opinion that neither claim 1 nor claim 2
`
`of the ’781 patent is anticipated by Divsalar because Divsalar does not disclose
`
`each and every feature of claim 1. In par
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