(12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT)
`
`(19) World Intellectual Property Organization
`International Bureau
`
`1111111111111111111111111111111111111111111111111111111111111111111111111111111111111
`
`(43) International Publication Date
`26 September 2002 (26.09.2002)
`
`peT
`
`(10) International Publication Number
`WO 02/075708 A2
`
`(51) International Patent Classification7:
`
`G09G 3/20
`
`(21) International Application Number:
`
`PCTIIB02/00903
`
`(22) International Filing Date: 19 March 2002 (19.03.2002)
`
`(25) Filing Language:
`
`(26) Publication Language:
`
`English
`
`English
`
`(72) Inventors: JANSSEN, Peter, J., M.; Prof. Holstlaan 6,
`NL-5656 AA Eindhoven (NL). ALBU, Lucian, R.; Prof.
`Holstlaan 6, NL-5656 AA Eindhoven (NL).
`
`(74) Agent: VAN DEN HOOVEN, Jan; Internationaal Oc(cid:173)
`trooibureau B.Y., Prof. Holstlaan 6, NL-5656 AA Eind(cid:173)
`hoven (NL).
`
`(81) Designated States (national): CN, JP, KR.
`
`(30) Priority Data:
`09/812,489
`
`20 March 2001 (20.03.2001) US
`
`(84) Designated States (regional): European patent (AT, BE,
`CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC,
`NL, PT, SE, TR).
`
`(71) Applicant: KONINKLIJKE PHILIPS ELECTRON(cid:173)
`ICS N.V. [NLINL]; Groenewoudseweg 1, NL-5621 BA
`Eindhoven (NL).
`
`Published:
`without international search report and to be republished
`upon receipt o/that report
`
`(54) Title: COLUMN DRNING CIRCUIT AND METHOD FOR DRIVING PIXELS IN A COLUMN ROW MATRIX
`
`[Continued on next page}
`
`(57) Abstract: A column driving circuit and method for driv(cid:173)
`ing pixels in a column row matrix. Specifically, the present in(cid:173)
`vention provides a circuit and method that generally includes an
`input for receiving a signal, a multiplexing circuit for receiving
`the signal from the input, and a first and a second column line,
`wherein each column line alternates in receiving the signal from
`the multiplexing circuit. By splitting the signal between two col(cid:173)
`umn lines, overall line capacitance is reduced, as are problems
`associated with delays in ramp retrace.
`
`--- ------------------------------------------------------------------------------------------
`-
`------!!!!!!!!
`
`62
`
`68
`
`72
`
`60
`
`/
`
`74
`
`78
`
`80A
`
`80B
`
`82A
`
`84A
`
`84B
`
`J
`
`J
`
`J
`
`Col (n·1)B
`
`Col(n) B
`
`Col (n+1) B
`
`Col (n-1)A
`
`Col (n) A
`
`Col (n+1) A
`
`<-94L
`
`Row (m+2)
`
`92
`
`!!!!!!!!
`
`- ----
`
`M -<
`
`QO
`Q
`t'-
`In
`t'-
`Q -.....
`M
`Q
`0
`~
`
`--!!!!!!!!
`
`SHARP EXHIBIT 1003
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`Page 1 of 18
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`

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`W 0 02/075708 A2
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`1111111111111111111111111111111111111111111111111111111111111111111111111111111111111
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`For two-letter codes and other abbreviations, refer to the "Guid(cid:173)
`ance Notes on Codes and Abbreviations" appearing at the begin(cid:173)
`ning of each regular issue of the PCT Gazette.
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`Page 2 of 18
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`

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`WO 02/075708
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`peT IIB02/00903
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`1
`
`Column driving circuit and method for driving pixels in a column row matrix
`
`The present invention generally relates to a column driving circuit and method
`
`for driving pixels in a column row matrix. More particularly, the present invention relates to
`
`an improved circuit and method for reducing the capacitive load on the columns ofthe matrix
`
`to provide improved pixel driving.
`
`5
`
`In video displays, matrices are commonly utilized in which pixels are oriented
`
`in a column row format. The column driving scheme currently employed to drive the pixels
`
`is based on a common analog ramp signal that is sampled by all columns in the display.
`
`Problems associated with this architecture include a high capacitive load that each column
`
`10
`
`presents to the column buffer, where a buffer amplifier is used in every column. Moreover,
`
`as the addressing frequency increases, as a result of a higher frame rate or a higher pixel
`
`count of the display, the fidelity of the sampled signal decreases.
`
`Another problem associated with the existing architecture is ramp retrace. In
`
`particular, the ramp signal in each column must retrace rapidly to an initial state in order to
`
`15 maximize the time available for sampling. Specifically, before the columns of the existing
`
`architecture can be driven with the analog signal, they must first be brought to an initial state
`
`or retraced. Thus, driving the pixels is at least a two step process in which each column
`
`must: (1) retrace to initial state; and (2) apply the analog signal. Since, a fast retrace requires
`
`large current capability of the driver(s), the associated large transients in the matrix could
`
`20
`
`cause undesired effects, e.g., activating unselected rows.
`
`In view of the foregoing, there exists a need for a column driving circuit and
`
`method for reducing the capacitive load in the columns ofthe matrix. Moreover, a need
`
`exists for a column driving circuit and method that reduces the problems associated with
`
`ramp retrace.
`
`25
`
`It is,~ object of the invention to provide an improved column driving circuit
`
`.-;-0·~C:
`
`-
`
`and method for ddvlng pixels in a column row matrix. Specifically, the present}invention
`
`provides ,a column driving circuit wherein each column is split into at least two column lines.
`Each column line'~oinmunicates with/is joined to a unique subset of rows in th€,,:lhatrix. By
`
`~
`
`.
`
`.
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`Page 3 of 18
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`

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`WO 02/075708
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`peT IIB02/00903
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`2
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`splitting the columns into multiple column lines, the capacitance of each line is a fraction of
`
`that required by a single column. In addition, because each column is split into at least two
`
`column lines, a first column line can be retraced to the initial state while the second column
`
`line is being driven by the analog signal thus, reducing the delays associated with ramp
`
`5
`
`retrace.
`
`To this end, a first aspect of the present invention provides a column driving
`
`circuit for driving pixels in a column row matrix. The circuit comprises: (1) a multiplexing
`
`circuit for receiving a signal; and (2) a first and a second column line, wherein the column
`
`lines receive the signal from the multiplexing circuit, and wherein the first column line is in
`
`10
`
`communication with different rows of the matrix than the second column line.
`
`A second aspect of the present invention provides a method for driving pixels
`
`in a column row matrix. The method comprises the steps of: (1) receiving a signal in a
`
`multiplexing circuit; (2) selectively sending the signal from the multiplexing circuit to a first
`
`and second column line; and (3) communicating the column lines with rows of the matrix to
`
`15
`
`drive the pixels, wherein the first column line communicates with different rows than the
`
`second column line.
`
`Therefore, the present invention provides a column driving circuit and method
`
`for driving pixels in a column row matrix. The present invention reduces the problems
`
`associated with high column capacitance and ramp retrace.
`
`20
`
`Further advantageous embodiments are defined in the dependent claims.
`
`These and other features and advantages of this invention will be more readily
`
`understood from the following detailed description of the various aspects of the invention
`
`taken in conjunction with the accompanying drawings in which:
`
`25
`
`Fig. 1 depicts a first prior art column driving circuit;
`
`Fig. 2 depicts a second prior art column driving circuit;
`
`Fig. 3-Gepicts a column driving circuit in accordance with the present
`
`invention;
`
`Fig." 4 qepicts a first alternative embodiment of a column driving circuit in
`
`30
`
`accordan~e with t~:R~esent invention;
`Fig.'I~tdepicts a multiplexing circuit in accordance with the present invention;
`·7-"~~;;~'"-
`"-'"--<
`Fig. f6.:depicts an alternative embodiment of a multiplexing circuit. in-
`
`-
`
`_.
`accorqancewith th~ present invention; and
`
`-_.
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`Page 4 of 18
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`WO 02/075708
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`peT IIB02/00903
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`3
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`Fig. 7 depicts a second alternative embodiment of a column driving circuit in
`
`accordance with the present invention.
`
`It is noted that the drawings of the invention are not necessarily to scale. The
`
`drawings are merely schematic representations, not intended to portray specific parameters of
`
`5
`
`the invention. The drawings are intended to depict only typical embodiments of the
`
`invention, and therefore should not be considered as limiting the scope of the invention. In
`
`the drawings, like ilUmbering represents like elements.
`
`As stated, the present invention comprises an improved column driving circuit
`
`10
`
`and method for driving pixels in a column row matrix. Generally, the present invention splits
`
`each column of the matrix into a plurality (preferably two) column lines. Each column line
`
`communicates with, or is joined, to a unique subset of rows in the matrix. Accordingly, the
`
`different column lines of a single column communicate with different (e.g., alternating) rows.
`
`An analog ramp signal then is alternately applied to the column lines within each column.
`
`15
`
`The resulting configuration reduces the capacitance on each column line. Moreover, as the
`
`analog signal is being applied to a first column line, a second column line can be retraced to
`
`an initial state. Therefore, there is negligible delay for a column line to retrace to the initial
`
`state.
`
`Referring first to Fig. 1, a prior art column driving circuit lOis depicted. The
`
`20
`
`circuit is for driving pixels in a column row matrix 11. As shown, the matrix comprises
`
`columns 24, 26, and 28 and rows 30, 32, 34, and 36. Digital input signals 12, 14, and 16 are
`
`received by each column via digital to analog converter (DACs) 18,20, and 22. Each DAC
`
`converts the digital signal to an analog signal, which is then used to drive a particular column
`
`within the matrix. Specifically, the analog signal exits each DAC 18,20, and 22 and is
`
`25
`
`received by columns 24, 26, and 28, respectively. Each column 24,26, and 28 includes a
`
`junction 40A-L to each row 30, 32, 34 and 36. Accordingly, each row controls one junction
`
`of each column. Each junction 40A-L generally comprises a pixel transistor 42, a capacitor
`
`44, a pixel 46 and a ground 48. It should be understood that the capacitor 44 represents a
`
`capacitance associated with pixel 46. Accordingly, pixels 46 are not explicitly shown for
`
`30
`
`eachjun~tion 40A .. L However, it should be understood that each junction 40A-L includes a
`
`pixeL46.-
`
`Whena video display that includes matrix 11 is refreshed, each piXel 46 must
`
`be driv~n. To accomplish this, each row will be individually activated for a brief period of
`
`time, This allows the analog signal in each column 24, 26 and 28 to pass througlkthe
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`Page 5 of 18
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`WO 02/075708
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`peT IIB02/00903
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`4
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`junctions 40A-L corresponding the activated row and drive the pixels. For example, if row
`
`30 is to be refreshed, it will first be activated. The analog signals will thenpass from
`
`columns 24, 26, and 28 through junctions 40A-C to drive the pixels in row 30. This will then
`
`be repeated for rows 32, 34, and 36.
`
`5
`
`As indicated above, however, this architecture presents many problems. In
`
`particular each column 24, 26, and 28 has a relatively high capacitance both from the lines
`
`and any un-activated pixel transistors, which requires more voltage, and results in reduced
`
`accuracy and bandwidth of the matrix. Moreover, before any column 24,26, and 28 can
`
`receive the analog signal, it must first be retraced to an initial state. This delay associated
`
`10 with retrace reduces the maximum time available for sampling by the rows, which is
`
`especially problematic in larger matrices.
`
`Fig. 2 shows a second prior art column driving circuit 50. This circuit 50
`
`includes similar elements as circuit 10 and drives column row matrix 51. Specifically, circuit
`
`50 receives digital signals 12, 14 and 16 in DACs 18,20, and 22 and converts the signals
`
`15
`
`from digital to analog. The analog signals are then passed to the columns 24, 26, and 28,
`
`which communicate with selectively activated rows 30, 32, 34 and 36. In embodiment of
`
`Fig. 2, however, each column communicates with pairs of rows instead of individual rows.
`
`For example, if row 30 is to be refreshed, it will first be activated. The analog signal will
`
`then pass through junctions 40A-C and drive the pixels therein.
`
`20
`
`The circuit 50 of Fig. 2 possesses the same drawbacks as circuit 10.
`
`Specifically, each column 24, 26, and 28 has a relatively high capacitance that requires more
`
`time to reach the capacity. This increase in time to reach capacity results in reduced accuracy
`
`and bandwidth of the matrix. Specifically, each un-activated transistor 42 has a parasitic
`
`capacitance slows the time to drive the column. Moreover, as indicated above, each column
`
`25 must be retraced to the initial state prior to communicating the analog signal through the
`
`junctions 40A-L This retrace causes delay in the cycle and thus, reduces the maximum time
`
`available for sampliBg by the rows.
`
`Referring now to Fig. 3, a column driving circuit 60 for driving pixels in a
`
`column row matrix 61 in accordance with the present invention is shown. As depicted,
`
`~~--:i-=~~
`
`··.;;r·:7::-~;.
`
`.
`
`30
`
`_~_~ __ ..r,;./_--
`
`__
`
`circuitt60 inclu<[tsjnput signals 62, 64, and 66, which are preferably digital signals. The
`signat~~<!tereceii~d in DACs 68, 70 and 72 where they are converted to analog signals. ()nce
`con"~ct~~(the~Tgp~ls are then communicated to multiplexing circuits 74, 76,J.td 78 .. The
`multitrlexing ciJ5Wts 74, 74, and 78 split each column into multiple column.lines.80A-B,
`82A·S{an:d 84A:-~: Thus, instead of each DAC outputting an analog signal int<r,a-singleline
`
`Page 6 of 18
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`peT IIB02/00903
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`5
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`(as shown in Figs. 1 and 2), the signal is outputted over mUltiple lines. Although each
`
`column is shown as being split into two column lines, it should be understood that any
`
`quantity of column lines could be formed (e.g., 4, 6,8, etc.).
`
`By splitting each column into two column lines, the capacitance of each
`
`5
`
`column line is approximately one-half that of each column of circuits 10 and 50. As will be
`
`described in further detail below, the multiplexing circuits 74, 76, and 78 alternate the
`
`respective analog signal between the two column lines in each pair. Thus, for example, while
`
`one column line 80A receives the analog signal, the corresponding column line 80B does not.
`
`Thus, under the present invention, it is not necessary for each column line to be in
`
`10
`
`communication with each row 86, 88, 90, and 92 thereby reducing the parasitic capacitance
`
`for each column line. Specifically, as shown in Fig. 3, each column line preferably includes
`
`junctions 94A-L to a unique subset of rows. For example, column lines 80A, 82A, and 84A
`
`are in communication with rows 86 and 90, while column lines 80B, 82B, and 84B are in
`
`communication with rows 88 and 92. By not requiring each column line to communicate
`
`15 with each row, the effects of the parasitic capacitance of each junction are reduced.
`
`As further shown in Fig. 3, the junctions generally comprise transistor 96,
`
`capacitor 98, pixel 100, and ground 102. It should be understood, however, that a pixel is
`
`shown only in junction 94A for clarity purposes, and all junctions include a pixel. To refresh
`
`the display on which the column row matrix 61 is implemented, each row is selectively
`
`20
`
`activated for a period of time, which allows the analog signal to pass from the column lines,
`
`through the junctions corresponding to the activated row, and drive the pixels therein. For
`
`example, if row 86 were activated, the analog signals would pass from column lines 80A,
`
`82A, and 84A, through junctions 94A-C, and drive pixels 100 (not shown in every junction).
`
`Contrary to the teachings of circuits 10 and 50, as column lines 80A, 82A, and
`
`25
`
`84A are driving the pixels on row 86, column lines 80B, 82B, and 84B are being retraced to
`
`an initial state. The switches in the multiplexing circuits 74, 76, and 78 (described below) are
`
`configured such that while one column line 80A is receiving the analog signal, the
`
`corresponding column line 80B is being retraced to the initial state (i.e., the analog signal is
`
`30
`
`'-7"~_~ ~
`
`-::""
`
`-~-;;'.,
`
`~~.,
`
`alternated between the column lines in each pair). Thus, when row 86 is later deactivated so
`thatto,¥;88 can b~i~~tivated, there is no delay in waiting lor retrace to occur (i.e., it has
`alreaa~'oc~urred),;;,~lAs indicated above, the elimination~otthis d",~lay improves:performance of
`the"at~~la;::AccQ~a~ngly:to refresh row 88,j(Wdijld~e;~aftiy~t~d:the;fmaIOcf~f~nals would
`pass from column'Iines 80B, 82B, and 84B throughjUllCtions 94D-F,and driv~ihe associated
`pixels "~~00\not sli~wn in 'every junction). ASC01:dr~gl~~,sNlittit}~~~a911'Gohjfijt#~to two (or
`
`.
`
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`.---~--'::--
`
`Page 7 of 18
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`6
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`more) column lines not only reduces the line capacitance and ramp retrace delay, but also
`
`reduces parasitic capacitance by allowing each column line in a single pair to communicate
`
`with different rows of the column row matrix 61.
`
`Fig. 4 shows an alternative embodiment of the present invention. Specifically,
`
`5
`
`column driving circuit 104 drives the pixels 100 in column row matrix 105. Although the
`
`components of circuit 104 are similar to that of circuit 60, the architecture thereof is distinct.
`
`In particular, digital signals 62, 62, and 66 are received in DACs 68, 70, and 72, where they
`
`are converted to analog signals. From the DACs 68, 70, and 72, the analog signals are
`
`communicated through multiplexing circuits 74, 76, and 78, which splits each column into
`
`10 multiple (preferably two) column lines 80A-B, 82A-B, and 84A-B. However, instead ofthe
`
`column lines of each pair communicating with alternating rows as shown in Fig. 3, the
`
`column lines of each pair communicate with pairs or adjacent subsets of rows. Thus, rows 86
`
`and 88 would be refreshed by a first column line 80A, 82A, and 84A while rows 90 and 92
`
`would be refreshed by a second column line 80B, 82B, and 84B. For example, for row 86
`
`15 was to be refreshed, it would first be activated. Then, the analog signals would pass from
`
`column lines 80A, 82A, and 84A through junctions 94A-C and drive the pixels 100.
`
`As indicated above, the analog signals are alternated between the column lines
`
`in each pair so that while one column line is receiving the signal, the corresponding column
`
`line can be retraced back to the initial state. Once row 86 has been refreshed, it would be
`
`20
`
`deactivated and, for instance, row 90 would be individually activated. Thus, the analog
`
`signal would be received by column lines 80B, 82B, and 84B and pass through junctions
`
`940-1 to drive the pixels therein. Because retrace occurred while the signal passed through
`
`column lines 80A, 82A, and 84A, there is no delay in waiting for column lines 80B, 82B, and
`
`84B to be retraced before driving the pixels.
`
`25
`
`Referring now to Fig. 5, a first embodiment of the multiplexing circuit 74 is
`
`depicted. As shown, a digital signal 62 is received and converted by DAC 68 to analog. The
`
`muLtiplexiI1gieircuit 74 then receives the analog signal from DAC 68. As indicated above,
`
`the mu1tipl€~dJ;1g circuit alternates the analog signal between column line 80A and 80B.
`
`30
`
`_. "~ _ .-~_':- ,.-- ;.it.:l'-c--....~-;_ Z'.~~::~;;;:!~~j:3'~.
`
`.
`
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`'$» "
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`~_~
`
`Moreover, w~i!e one column line is receiving the analog signal, the other will receive a
`refet:"~nce":'yq-\1a:~~ 112 for simultaneous retracing to the initial state. These functions are
`pr~~~'1i,ld~byt~~~~istor signal switches 104 and 106 and transisto~ voltagesxVitc,hes 108 and
`IJ(}:~,[~t~~ifi~~f&, when signal switch 104 is "on," signal switblil106is"6ff'~d the analog
`.
`sign~l-wjllpas~through column line 80A. Moreover, \Vhensig~a,l swi,~ch_I04is "on,"
`volt~ge ~~itc:h;~~11 o corresponding to column line 80B will als~':~~"Qn:"'o~?l~i1i~opermits the
`
`-=-,."
`
`, .
`
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`
`Page 8 of 18
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`7
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`reference voltage 112 to pass through column line 80B to retrace column line 80B to the
`
`initial state while column line 80A is receiving the analog signal. The switches 104, 106,
`
`108, and 110 are controlled by signals 114, 116, 118, and 120, respectively. These signals
`
`activate the transistors in each switch to connect the column lines to the analog signal or
`
`5
`
`voltage.
`
`Once the rows corresponding to column line 80A have been refreshed and are
`
`deactivated, the rows corresponding to column line 80B can be activated for refreshing. As
`
`this occurs, signal switch 104 and voltage switch 110 will be turned "off' while signal switch
`
`106 and voltage switch 108 are turned "on." This allows for the pixels ofthe rows
`
`10
`
`corresponding to column line 80B to be driven with the analog signal while column line 80A
`
`is retraced to the initial state by reference voltage 112. As indicated above, this architecture
`
`and method eliminate the delay and problems associated with ramp retrace.
`
`Referring now to Fig. 6, an alternative embodiment of the multiplexing circuit
`
`122 is shown. Similar to Fig. 5, the multiplexing circuit 74 receives a digital signal 62 and
`
`15
`
`includes DAC 68, transistor signal switches 104 and 1 06 (controlled by signals 114 and 116),
`
`transistor voltage switches 112 (controlled by signals 118 and 120), and column lines 80A
`
`and 80B. However, multiplexing circuit 122 also includes hold signals 128 and 130 and
`
`"AND" gates 124 and 126. The hold signals 118 and 120 originate from the DAC 68, which
`
`in this embodiment is a "track and hold" DAC. By including a hold signal, the sampling
`
`20
`
`switch is opened at the moment sampling is to occur. The difference between a "track and
`
`hold" and "sample and hold" is the duration the sampling switch is closed. Specifically, in a
`
`"sample and hold" embodiment, the sampling switch is closed for the shortest possible time.
`
`In "track and hold," the switch is closed from the very beginning of each cycle until it opens
`
`at "hold." Similar to the multiplexing circuit 74 of Fig. 5, the multiplexing circuit 122 will
`
`25
`
`alternate the analog signal between the column lines 80A and 80B. The column line that is
`
`not receiving the analog signal will receive the reference voltage 112 for retracing to the
`
`initial state.
`
`Referring now to Fig. 7, it should be appreciated a circuit according to the
`
`30
`
`1.;1"-_""'",€,:.
`
`present invention need not require a DAC to drive the pixels. Specifically, if analog signals
`152,))~~,oangj~:6 are provided directly to the multiplexing circuits 74, 76, and 78, there is no
`needtb:utilize~Jl'"pAC. Thus, column driving circuit 150 (used to drive pix~lsin column row
`n1atri~;f5 d:~iit1eceive input (analog) signals 152, 154, and 156 directly a(rnultiplexing
`circuits 74, 76, and 78. Multiplexing circuits 74, 76, and 78 will then selectively apply the
`
`-
`
`:-~~.;:-..:":"e::-:
`
`.
`
`sigr\at$:to cQbJttm lines 80A-B, 82A-B, and 84A-B by alternating the sign.aj~betweenthe two
`
`Page 9 of 18
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`8
`
`column lines of each column. Pixel driving will then occur as described above in conjunction
`
`with Figs. 3 and/or 4.
`
`The foregoing description of the preferred embodiments of this invention has
`
`been presented for purposes of illustration and description. It is not intended to be exhaustive
`
`5
`
`or to limit the invention to the precise form disclosed, and obviously, many modifications and
`
`variations are possible. Such modifications and variations that may be apparent to a person
`
`skilled in the art are intended to be included within the scope of this invention as defined by
`
`the accompanying claims.
`
`Page 10 of 18
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`

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`WO 02/075708
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`CLAIMS:
`
`9
`
`peT IIB02/00903
`
`1.
`
`A column driving circuit [60] for driving pixels [100] in a column row matrix
`
`[61], comprising:
`
`a multiplexing circuit [74] for receiving a signal [62 or 152]; and
`
`a first and a second column line [80A and 80B], wherein the column lines
`
`5
`
`[80A and 80B] receive the signal [62 or 152] from the multiplexing circuit [74], and wherein
`
`the first column line [80A] is in communication with different rows [86, 88, 90, and 92]of the
`
`matrix [61] than the second column line [80B].
`
`2.
`
`The circuit of claim 1, wherein the multiplexing circuit [74] receives the signal
`
`10
`
`[62 or 152] from a digital to analog converter (DAC) [68].
`
`3.
`
`The circuit of claim 1, wherein the multiplexing circuit [74] comprises a
`
`plurality of signal switches [104 and 106] for alternating the signal [62 or 152] between the
`
`first and second column lines [80A and 80B].
`
`15
`
`4.
`
`The circuit of claim 3, wherein the multiplexing circuit [74] further
`
`comprising a plurality of voltage switches [118 and 120] for alternating a reference voltage
`
`[112] between the first and second column lines [80A and 80B].
`
`20
`
`5.
`
`The circuit of claim 4, wherein the multiplexing circuit [74] further
`
`comprising a hold signal [130] for maintaining voltage in the first and second column lines
`
`[80A and 80B].
`
`6.
`
`The circuit of claim 3, wherein when the first column line [80A] is receiving
`
`25
`
`the signal [~,2or 152], the second column line [80B] is receiving the refere,nce voltage [112].
`
`7.
`
`steps'ot: _
`
`A m~thod for driving pixels [100] in a column row matri,:,~[61], comprising the
`.,--... :-
`
`"',-
`
`~-
`
`reGeiying a signal [62 or 152] in a multiplexing cir~_uit"H4J;
`
`Page 11 of 18
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`

`

`WO 02/075708
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`peT IIB02/00903
`
`10
`
`selectively sending the signal [62 or 152] from the multiplexing circuit [74] to
`
`a first and second column line [SOA or SOB]; and
`
`communicating the column lines [SOA and SOB] with rows [S6, SS, 90, and
`
`92] of the matrix [61] to drive the pixels [100], wherein the first column line [SOA]
`
`5
`
`communicates with different rows [S6, SS, 90, and 92] than the second column line [SOB].
`
`S.
`
`The method of claim 7, wherein the column lines [SOA and SOB] communicate
`
`with the rows [S6, SS, 90, and 92] through junctions [94A, 94D, 94G, 94J], and wherein each
`
`junction [94A, 94D, 94G, 94J] joins one of the column lines [80A or SOB] to one of the rows
`
`10
`
`[S6, SS, 90, and 92].
`
`9.
`
`The method of claim S, wherein each junction [94A, 94D, 94G, 94J]
`
`comprises:
`
`a transistor [96];
`
`a pixel [100]; and
`
`a ground [102].
`
`to.
`signal [62 or 152] from a DAC [6S].
`
`The method of claim 9, wherein the multiplexing circuit [74] receives the
`
`15
`
`20
`
`11.
`
`The method of claim 10, wherein the multiplexing circuit [74] further
`
`comprIses:
`
`a plurality of signal switches [104 and 106] for alternating the signal [62 or
`
`152] between the first and second column lines [SOA and 80B]; and
`
`25
`
`a plurality of voltage signals [lOS and 110] for alternating a reference voltage
`
`[112] between the first and second column lines [SOA and SOB].
`
`Page 12 of 18
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`

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`WO 02/075708
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`peT IIB02/00903
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`1/6
`
`18
`
`12
`
`DAC (n-1)
`
`20
`
`DAC (n)
`
`24
`
`/40A
`42
`
`I
`-
`-
`
`I
`
`-
`-
`
`I
`
`/AOJ
`
`14
`
`26
`
`I
`
`I
`
`-
`-
`
`I
`-
`-
`
`I
`
`16
`
`22
`
`DAC(n+1)
`
`40B
`/
`Tp (m-1)
`
`28
`
`I
`
`I
`
`-
`
`I
`
`-
`-
`
`I
`
`Col (n-1)
`
`Col (n)
`
`Col (n+1)
`
`FIG. 1
`
`/10
`
`40C
`I
`
`Row (m-1)
`
`30
`
`Row (m)
`
`32
`+-11
`
`Row (m+ 1)
`40L
`
`34
`
`I
`
`Row (m+2)
`
`36
`
`Page 13 of 18
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`WO 02/075708
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`peT IIB02/00903
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`12
`
`DAC (n-1)
`
`20
`
`DAC (n)
`
`24
`
`30
`
`2/6
`
`14
`
`26
`
`16
`
`22
`
`DAC (n+1)
`
`/50
`
`28
`
`~40A r- ~40B r- ~40C
`
`Row (m-1)
`
`~40D
`
`~40G
`
`~40J
`
`32
`
`I
`
`-
`-
`
`34 r-
`
`36
`
`I
`
`-
`Col (n-1 )
`
`I
`-
`-
`
`r-
`
`I
`
`-
`Col (n-1)
`
`~40E
`
`~40H
`
`~40K
`
`FIG.2
`
`I
`-
`
`~40F
`
`Row (m)
`~51
`
`r- Row (m+1)
`
`~ 40I
`
`~40L
`
`Row (m+2)
`
`I
`
`-
`-
`Col (n-1)
`
`. , -
`
`Page 14 of 18
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`

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`WO 02/075708
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`peT IIB02/00903
`
`62
`
`68
`
`74
`
`3/6
`
`70
`
`76
`
`60
`
`I
`
`72
`
`78
`
`80A
`
`80B
`
`82A
`
`82B
`
`84A
`
`84B
`
`96
`
`+-94A
`
`+-940
`
`+-94G
`
`+- 94J
`
`-
`-
`
`I
`
`-
`-
`
`I
`
`-
`-
`
`I
`-
`
`Col W~) B
`
`.;--
`
`' -
`
`:~.~- .;.
`:<;:::".
`
`I
`
`-
`-
`
`I
`-
`-
`
`I
`
`-
`-
`
`I
`
`-
`
`+-948
`
`+-94E
`
`+-94H
`
`+-94K
`
`I
`
`-
`
`I
`
`-
`-
`
`I
`-
`-
`
`I
`
`-
`-
`
`+-94C
`
`Row (m-1)
`
`86
`
`+- 94F
`+- 61
`Row (m)
`
`88
`
`+- 941
`
`Row (m+1)
`
`90
`
`+-94L
`
`Row (m+2)
`
`Col(n) B
`
`Col (n+1)B
`
`9~~
`
`tol (n'-l)A'~
`
`Col (n) A
`
`Co\(n+1)A
`
`FIG. 3
`
`Page 15 of 18
`
`

`

`WO 02/075708
`
`peT IIB02/00903
`
`68
`
`74
`
`80A
`86
`
`808
`
`82A
`
`4/6
`
`70
`
`76
`
`828
`
`104
`/
`
`72
`
`78
`
`848
`
`84A
`
`Row (m-1)
`
`~94A
`
`~ .-948
`
`~ <-94C
`
`~94D
`
`I
`
`~94E
`
`I
`
`~94F
`
`~105
`Row (m)
`
`90 ~ <-94G
`
`Row (m+1)
`
`~ 941
`
`I -
`
`92
`
`:;,
`
`----,,-
`. Cpl (n-1) B
`
`Col (n-'l)A
`
`~94K
`
`~94J
`
`I --
`
`I --
`
`~94L
`
`Row (m+2)
`
`Col (n) B
`
`Col (n) A
`
`FIG.4
`
`Col (n+1) B
`
`Col (n+ 1) A
`
`Page 16 of 18
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`

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`peT IIB02/00903
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`5/6
`
`104 -:--l
`
`~ r:==-62
`I-------~------------,
`i
`!-,- 68
`,
`I
`~------- --------, ~ 74
`,
`I
`~ 106
`! CTR B J 116
`114 '- CTR A:
`,
`I
`'
`I
`,
`I
`118'--CTR A!
`'CTR Sf 120
`
`108
`
`110
`
`Vref ----112
`
`,
`L_
`
`80A
`
`80B
`
`FIG.5
`
`!~28 --- u= --6~-:;;~-r-'-68
`
`114"\..CTRA l_~_H
`
`H.J' CTRSJ116
`
`~122
`
`,
`
`I
`.
`118'--CTR A '
`- -4 - - - f - - - - "
`,
`
`108
`
`110
`CTR Sf 120
`1---1------1-__
`
`Vref~112
`:
`,
`L _____________
`80A
`
`_--1
`
`80B
`
`FIG.6
`
`Page 17 of 18
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`

`

`WO 02/075708
`
`peT IIB02/00903
`
`152-i
`
`154-i
`
`6/6
`
`156~
`
`74
`
`76
`
`80A
`
`808
`
`82A
`
`828
`
`84A
`
`848
`
`150
`/
`
`78
`
`+-94A
`
`+-940
`
`+-94G
`
`+- 94J
`
`--
`
`I -
`
`I -
`
`I --
`
`I
`-
`
`I
`-
`-
`
`I
`
`-
`
`I
`
`-
`-
`
`+-948
`
`+- 94E
`
`+-94H
`
`+-94K
`
`I
`
`-
`
`I
`-
`-
`
`I
`
`-
`-
`
`I
`-
`
`+-94C
`
`Row (m-1)
`
`86
`
`+- 94F
`
`+-151
`Row (m)
`
`88
`
`+- 941
`
`Row (m+1)
`
`90
`
`+- 94L
`
`Row (m+2)
`
`Col (n-1) B
`
`Col (n-1)A
`
`Col (n) B
`
`Col (n) A
`
`Col (n+ 1) B
`
`92
`
`Col (n+1) A
`
`FIG.7
`
`Page 18 of 18
`
`