IEEE JOURNAL 0N SELECTED AREAS l'N COMMUNICATIONS, VOL. SAC-5, ND. 3. APRIL 1933‘
`
`329
`
`256 QAM Modem for Multicarrier 400 Mbit/s
`Digital Radio
`
`YASUHISA NAKAMURA, YOICHI SAITO, MEMBER,
`
`tans, AND SATORU AIKAWA
`
`Abstract—This paper describes the performance of a 256 QAM mo-
`dem with 400 Mbit /5 transmission capacity. A variety of novel tech-
`niques are introduced as ways to achieve good performance. Key tech-
`niques include 1) an accurate 256 QAM modulator employing a new
`monolithic multiplier 1C. 2) a carrier recovery circuit which satisfl8s
`such requirements: good phase jitter performance and no false lock
`phenomenon, 3) a highly stable high-level decision circuit. and 4) a
`forward error correcting code. As an overall modem performance, BER
`characteristics and signatures are presented. The equivalent CNR deg-
`radations of 1 dB (at BER of III") and 2 dB {at BER of 10") are
`obtained using a single Lee-error correcting code and a seven-tap
`baseband transversal equalizer. The residual bit errors are decreased
`below the order of 10"". The performance of a 256 QAM multicarrier
`modern has given prospect for the development of 400 Mblt / 5 digital
`microwave radio system.
`
`I.
`
`INTRODUCTION
`
`NE of the most important criteria in the design of
`digital radio systems is the transmission capacity per
`RF bandwidth,
`i.c., bits/second/Hertz. High-level
`modulation schemes for increasing spectrum utilization ef-
`ficiency are now a major subject in the dcvelomncnt of.
`digital microwave radio. In recent years, several digital
`radio systems with 16 QAM. and even with as high as 64
`QAM modulation have been developed and are in opera—
`tion in the microwave frequency band [11—[4]. The trend
`to increase spectrum utilization efficiency may continue
`[5].
`As the modulation level increases, the system becomes
`more sensitive to multipath induced waveform distortion
`and interference noise. It was already demonstrated [8]
`that the multicarrier transmission method is effective fur
`
`high-level modulation schemes in a multipath environ-
`ment. On the basis of the above considerations, this paper
`describes a 25.6 QAM multicarrier modem for the 400
`Mbit/s digital microwave radio (BM-400M) system [6],
`[1'].
`First. the performance of a newly developed monolithic
`multiplier 1C for 256 QAM modulation and demodulation
`is described. Next, two principal techniques employed in
`a demodulator are stated. One is “a carrier recovery PLL
`with control mode selection function" which satisfies such
`
`requirements as good phase jitter performance and no false
`lock phenomenon. Another is “automatic gain and deci-
`
`Manuscript received September 15. 1936: revised December 12. 1986.
`The authors are with NTT Electrical Communication Laboratories, Nip-
`pon Telegraph and Telephone Corporation, KanagaWa, 233-03 Japan.
`IEEE Log Number 3613242.
`
`sion threshold control (AGTC) circuits." Due to these
`circuits. an excellent 256 QAM BER performance can be
`obtained. Forward error correction (FEC) is one of the
`key techniques for high-level modulatioa systems, be-
`cause it eliminates residual bit errors. A single Lee—error
`correcting code with low redundancy is employed.
`Finally, the 256 QAM BER performance, and signature
`with and without adjacent channel interference are pre-
`sented. The equivalent CNR degradations of 1 dB at BER
`of 10‘“ and of 2 dB at BER of 10‘9 are obtained. The
`residual bit errors are decreased below the order of 10‘ ‘0.
`
`11. GENERAL Descarnrrors
`
`A. Outline of 256 QAM Four-Carrier Modem
`
`For the realization of a digital radio system having a
`transmission capacity of 400 Mbits / 5 within 80 MHz
`bandwidth, 3 256 QAM modulation using the Nyquist
`spectral shaping (or = 0.5) is required. This enables the
`frequency utilization efficiency of 10 bits I s / Hz when the
`orthogonal dual polarization is employed.
`In a high-level modulation system such as 64 QAM or
`256 QAM, the multipath fading causes large degradation
`of BER performance. A multicarrier system is considered
`to be a promising method for high—level signal transmis-
`sion in a fading channel. From the 256 QAM transmission
`characteristics estimation. a four-carrier system with 12.5
`MBaud data rate and rollofl‘ factor of 0.5 was found nec-
`
`essary to achieve 400 Mbits f s [8]. In this situation, the
`frequency spacing between adjacent carriers is 20 MHz
`and the radio channel is composed of four modems. The
`modern block-diagram and major system parameters are
`shown in Fig. l and Table I.
`The transmitting terminal equipment converts 400
`Mbit/s data into 32 rails of 12.5 MBaud binary signals.
`These 32 binary bit streams are fed to the four modulator
`circuitry. In each modulator, eight binary streams are dif-
`fercntially encoded (quadrant symmetry encoding) and re-
`dundant bits for error correcting are added by an FEC
`coder circuit. These streams are converted by DlA con-
`verters to form iii-phase and quadrature 16 level signals.
`Each 16 level signal modulates a local oscillator. The 256
`QAM signals with cosine rolloif spectrum shaping (or =
`0.5) are then combined by a hybrid circuit and supplied
`to the transmitter. The 256 QAM four-carrier spectrum is
`shown in Fig. 2.
`At a demodulator, the 256 QAM four-carrier signals are
`
`0733—871618710400-0329$01.00 © 1981If IEEE
`
`TM01009
`
`TMO1009
`
`

`

`330
`
`IEEE JOURNAL 0N SELECTED AREAS IN COMMUNICATIONS. VOL. sac-5, No. 3. APRIL 198'!
`
`Demodulator'
`
`Fig. 1. Block diagram of ”256 0AM four-carrier modem.
`
`TABLE 1
`_
`MAIN PARAMETERS or 256 QAM 400 Mhit / s MULTICARRIER Movers
`man-«mum»
`ham-mama
`
`
`
`
`Spun-sun shaping
`
`ammwumummm
`HIE lwlth orthogonal dual polarization
`
`distributed by a hybrid circuit and coherently detected to
`produce tWo orthogonal 16 level baseband signals. The
`seven-tap baseband transversal equalizers are employed
`to equalize both in-phase and quadrature waveform dis-
`tortions. In order to improve pull-in performance, ZF
`(zero forcing) with MLE {maximum level error) algo*
`rithm is employed [6}. Demodulated 16 level signals are
`regenerated by AID converters to produce eight rails of
`12.5 MBaud binary signals. Error connection is then car-
`ried out in the FEC decoder circuit.
`
`lDdB/div.
`v :
`H i lOMHz/div.
`
`'lF SW 2 IOOKHz
`
`Video BW I 300H2
`
`Fig. 2. Four—carrier spectrum.
`
`B. Key Techniques for an Accurate 256 QAM Modem
`
`In order to realize an accurate 25o QAM modem, the
`following novel techniques are applied.
`1) monolithic multiplier 1C for the modulator and the
`phase detector,
`' 2) high-level decision circuit with automatic gain and
`decision threshold control (AGTC circuit).
`3) carrier recovery with control mode selection func—
`tion,
`
`4) forward error correction (FEC) technique.
`
`III. Ciscurr DESCRIPTION
`
`A. Modulation Section
`
`The degradation factors arising at various parts in a mo-
`dem, such as waveform distortion. phase error, carrierjit-
`ter. etc. , Were categorized and the effects of these factors
`on 256 QAM equivalent CNR degradation were presented
`
`in [5]. Concerning the modulation section, it was revealed
`that the allowable maximum modulation phase error is
`1:05" to Satisfy the requirement for an equivalent CNR
`degradation of 0.6 dB at a BER of 10—6 for 256 QAM.
`Therefore, a new monolithic multiplier IC capable of
`reducing the modulation phase and amplitude errors has
`been developed for the 256 QAM [9]. The main perfor-
`mance of the multiplier itself is presented in Table II. The
`new IC has a baseband input voltage linearity of more
`than 1.5 V and modulation phase error is less than 0.2”,
`which are extremely superior to the conventional ring
`modulators and to multiplier lC developed for a lo QAM
`system. Third—order intermodulation products (IMS) of
`more than 55 dB at the average output power level is ob-
`tained. These performances are achieved with the aid of
`the latest device technology: SST (super self—aligned pro-
`cess technology) [10]. The modulation phase error ob-
`
`2
`
`

`

`NAKAMURA at 1.11.: 256 QAM MODEM FOR MULTICARRIER 400 Mbit/s DIGITAL RADIO
`
`331
`
`Points -l —.a
`NortherofSignal
`
`1
`
`0.5
`o
`Phase mr [dell
`*deviloped for IscaM
`
`Fig. 3. Modulation phase error distributions comparing new monolithic IC
`and convention] modulator.
`
`
`
`Fig. 4. 256 QAM signal constellation.
`
`TABLE ll
`Monourmc MULTIPLIER 1C PERFORMANCE
`
`
`
`
`
`
`
`
`
`
`
`.......................
`.
`-
`“creme”
`
`...............
`
`amplitudzdeviationhotween
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`..............-.....,......
`[MS ithirdqn-der tnbemndulntiou more than 5563
`products)
`uh are the output beck-ed is 'i'rlB
`
`fabrication pr:
`
`
`
`331’ {Super Self-aligned process
`bet-rheology}
`
`
`
`
`
`
`
`
`
`tained from the new monolithic multiplier IC and conven-
`tional one deveIOped for a 16 QAM system are measured.
`Fig. 3 shows the number of signal points versus modu-
`lation phase error comparing the two multiplier IC’s- The
`number of signal points of the quadrature multiplier with
`phase error of less than :l:l'.l.5D are 238 by using the new
`monolithic IC’s. The measured maximum phase error of
`less than 11" has been obtained.
`
`It is concluded from experimental results that the newly
`developed monolithic multiplier IC almost satisfies the re-
`quirements for 256 QAM modulator. Fig. 4 shows the
`measured 256 QAM signal space diagram.
`
`B. Demodulafion Section
`
`1) Carrier Recovery with Control Mode Selection
`Function: A variety of carrier tracking loops for the QAM
`signal have been proposed [11], [12]. One of the most
`effective methods for 16 QAM carrier recovery was a se»
`lective gated phase locked loop (PLL), which uses only
`the error signal derived from the same phases of a 4-PSK
`signal. The recovered carrier jitter of more than 35 dB for
`a 16 QAM signal was obtained by this method [11]. How-
`
`I
`
`0.3
`[1.6
`
`£04
`9.2
`ll
`-fl_2
`
`D
`
`CNR =EUdB
`
`5 I015 20 2530 3510 #5
`Phase ermr Eden.)
`
`Fig. 5. Phase comparator characteristic.
`
`ever, the required carrier jitter for 256 QAM is more than
`45 dB when the equivalent CNR degradation of 0.3 dB is
`permitted. Therefore,
`it is necessary to design a carrier
`recovery circuit which satisfies such requirements: a) good
`phase jitter performance and b) no false lock phenome-
`non.
`
`The received 256 QAM signal is demodulated into 16-
`level baseband signals at iii-phase and quadrature chan-
`nels. The regenerated first-bit signal sets (a1, 1),), which
`are the most significant bit (MSB) of AD converters, and
`the fifth-bit signal sets (as, b5), which are error polarity
`signals, are multiplied and is used as the VCO control
`signal. The phase control voltage V(B) is obtained as fol-
`lows.
`
`VW) = d. 55 — 5155-
`
`(I)
`
`The reduction of a PLL noise bandwidth and the im-
`
`provement of VCO phase jitter are necessary to obtain a
`recovered carrier jitter of more than 45 dB. The carrier
`jitter of more than 45 dB has been achieved by designing
`RF local oscillator frequency stability of the order of 10'
`and employing a voltage controlled crystal Oscillator
`(VCXO) in the demodulator. In spite of a good carrier
`jitter performance,
`it has been clarified from the phase
`comparator characteristic that the carrier recovery circuit
`has a false-lock point in the same frequency when input
`CNR is sufiiciently high [5].
`The selective gating of VCXO control signal during the
`course of an acquisition is effective in order to prevent the
`false-lock phenomenon.
`After locking into a normal phase, the operation of se-
`lecting the control signal
`is inhibited. The switching is
`performed by monitoring the intersymbol
`interference
`which is easily estimated from the multiplication of the
`fifth and the sixth bits of AID converter. This technique
`simultaneously enables the improvement of pull-in and
`carrier jitter performance.
`The phase comparator characteristic in a selective gat- .
`ing mode is obtained as follows.
`Let Dsi be the probability that the signal point i is in;
`volved in a selective area. Dsr‘ is shown as
`-
`
`'
`
`Dsi = SSmUfiPi(x,y)dxdy
`
`(2)
`
`where, Pr'(x, y) is a Gaussian pdf
`
`(i = 1 ~ 256).
`
`3
`
`

`

`332
`
`lEEE JOURNAL ON SELECTED AREAS 1N COMMUNICATIONS. VOL. SAC-5. Na 3‘ RPRIL "JET
`
`Pro. y) = Pi(x) - Pi(y)
`21w KP [
`2‘72
`
`1
`= --'—v- e
`
`2
`
`1
`
`(.r ~ Six)
`-—-— I ex
`
`2
`
`p[
`
`(y - Siy)
`— ——
`
`202
`
`_
`Sir = in-phase component of signal point i
`Sty = quadrature component of signal point r'
`02 = white Gaussian noise power
`26 = minimum distance between signal points.
`
`(3)
`
`The average CNR (carrier to noise ratio) of 256 QAM
`can be obtained as
`
`CNR = 35 62/02 = 1:5.
`
`(4)
`
`In (2), Rs means the positive area producing correct
`control voltage “+1" and Er means the negative area
`producing error control voltage “ — 1." When the signal
`point i is involved in a selective area, the phase control
`voltage VHS) is shown as
`
`14(6) = 5L Pie. y) dx dy
`
`— SL3 Pi(x.y)drdy.
`
`(5)
`
`When the signal point i is involved in a nonselective
`area, the phase control voltage 14(6) is put into “hold"
`condition by a sample and hold circuit. Then, the follow-
`ing equations are introduced.
`256
`
`Pe(9) = 2 {name + Pe(6) (1 - Dst)}/256
`
`Pew) = phase comparator characteristic.
`
`(6)
`
`Fran-i (6), Pew) can be written as
`3.56
`
`256
`
`Pe(8) = a V(9)Dsr' 1;] 051'.
`
`(7)
`
`The phase comparator characteristic in a selective gat-
`ing mode is shown in Fig. 5. The number of error signals
`used in the selective gating in Fig. 5 is 96 out of 256.
`Note that the loop exhibits no false lock point. The re-
`covered carrier spectrum is shown in Fig. 6. The mea-
`sured carrier jitter was 45.5 dB and the pull-in frequency
`range of more than 8 kHz was obtained.
`2) High-Level Decision Circuit with Automatic Gain
`and Decision Threshold Control
`(AGTC): In order to
`achieve a good BER performance, an automatic gain and
`decision threshold control (AGTC) circuit is employed
`[14]. It uses the first and fifth bits of A!D converter as the
`feedback signals for the amplitude variation and dc drift
`of demodulated signals. These degradations are mainly
`caused by a local leak of the modulator, AGC level vari—
`ation and temperature characteristic of amplifiers. The'
`feedback signals are fed to the dc amplifier which is lo—
`cated before the AID converter. Fig. 7 shows the circuit
`configuration.
`
`
`
`HOMHZ
`
`V I
`
`lUdB/div.
`
`H I
`
`lOKHz/div.
`
`IF BWI lKHz
`
`Video BW I
`
`lODHz
`
`Fig. 6. Recovered can'ier spectrum.
`
`
`
`
` a Equivalentrmdegradation(dB)
`
`Ilth
`Warnluutlei
`control
`|
`
`Input
`
`level vorlotlon ldBII
`
`Fig. 7. Feedback circuit configuration.
`
`'255 MM
`
`Fig. 8. Equivalent C {N degradation due to input level variation.
`
`Let the input signal to the AID converter be u(t) and
`applying Laplacian "s" to u( t), in dc drift compensation
`feedback loop [5]:
`
`U(s) = V(s) + Hui/(1+ lde(s)).
`
`When F(s) is supposed to be a perfect integrator.
`
`F(s) = K's/s.
`
`then,
`
`S
`= V
`E .
`cm (s) + 3 + K“ . M (v)
`
`.
`
`(8)
`
`(9)
`
`(10)
`
`In amplitude variation compensation feedback loop (see
`Appendix),
`
`4
`
`4
`
`

`

`NAKAMURA et aL: 256 0AM MODEM FOR MULTICARRJER IlflO Mbit/s DIGITAL RADIO
`
`333
`
`{1(5) = V(s) + A(s)/ng F(s)
`
`(1'1)
`
`therefore, (ll)becomes
`
`up) = V(s) + M: K Am
`
`(12)
`
`where
`
`V(s) = 256 QAM demodulated signal
`E ( s) = dc drift
`A(s) = amplitude variation
`F (s) = low—pass filter transmitting function
`Kd, Kg = the linearized gain constants of the loop
`or = gain constant of a dc amplifier.
`
`The mathematical model of the feedback system indi-
`cated in (9), (10) has shown that it has a high—pass fre—
`quency characteristic for both amplitude variation and dc
`drift. The high-pass frequency characteristic of the feed
`back loops enables suppression of low frequency com-
`ponents of these degradations. Fig. 8 shows one experi-
`ment example of the input level variation compensation.
`This figure gives equivalent CNR degradation versus in-
`piit level variation at BER of 10'6 for 256 QAM. Even a
`small level variation causes a large degradation in case of
`no control, while the CNR degradation is suppressed
`within 0.3 dB for the input level variation of i1 (113 by
`employing the amplitude control.
`_
`A fifth bit of the AID converter is used as the feedback
`
`signal for the dc drift compensation, and an exclusive-or
`output of a first and fifth bits is used for amplitude vari—
`ation compensation. However it is revealed that, in both
`cases, if the dc drift or amplitude variation exceeds a half
`of the minimum distance between signal points. the com-
`pensated signal is locked to the incorrect voltage. Once
`the situations occur, burst bit errors are continually pro-
`duced. This phenomenon is called “faISe-lock" and the
`calculation of the control voltage characteristics also prove
`its existences [5]. The dc leveliamplitude monitor circuits
`and gate circuits shown in Fig. 7 are used to slip out from
`this ”false-lock" situation. It is effective to change the
`feedback signals. For example, the first and fifth bits of
`the AID converter are exchanged for the dc drift compen-
`sation and the exclusive-or output of the first and second
`bits is selected for the amplitude variation compensation
`once the “false-lock" occurs.
`
`C. Forward Error Correction {FEC}
`
`An application of FEC codes to high-level modulation
`systems greatly improves BER performance, particularly
`useful for the elimination of residual bit errors. Gener—
`
`ally, in high-level modulation schemes, the symbol error
`probability between the adjacont symbols is much larger
`than that between the separate symbols. Therefore,
`it is
`effective to select an FEC code which can mainly correct
`the error propagations to adjacent symbols. The represen-
`tative one is Lee-error correcting code [15]. The theoret—
`ical symbol error rate (SER) improvement due to the sin-
`
`ll"
`H Iwithout FEC
`
`I----o : ui-th
`FEC
`Modem back to bank
`Clack .’ 12.51MB
`
`BER
`
`
`
`
`
`”man in
`
`a:
`
`34
`
`as
`
`as
`
`.o
`
`4; “
`
`CNH {dB}
`
`Fig. 9. 256 QAM BER performance.
`
`gle Lee-error correcting code (72, 70) is shown as
`
`Fe _= 107 - P3
`
`Pa = SER after FEC
`
`P = SER before FEC.
`
`(13)
`
`The rate overhead of this code is only about 3 percent.
`The differential decoding is performed after error correc-
`tion.
`
`IV- OVERALL PERFORMANCE
`
`The 256 QAM signal has 16 baseband levels. The
`baseband signal is obtainiéd by Dr‘A converters as
`
`Sl=23'a1+22'02+2'a3+a4
`
`32:23-b1+22-b2+2-b3+b4.
`
`- (04. b4) are binary codes and
`'
`Signal sets (an bi), ‘
`categorized as ”Path 1” to "Path 4" indicating the first
`to fourth bit. The BER of 256 QAM is obtained as the
`average of the BER’s'of each path. Considering a quad-
`rant symmetry differential encoding, the average BER of
`256 QAM becomes
`
`P8 = 19/64 drew/J27 o)
`
`= 19/64 erfc(kD/~/l70)
`
`(14)
`
`25 = minimum distance between signal points,
`02 = white Gadssian noise power.
`
`The 256 QAM BER's for Path 4 (modern back to back)
`are shown in Fig. 9. The single Lee-error correcting code
`and a seven-tap baseband transversal equalizer are imple—
`mented in this system. The equivalent CNR degradation
`of 1 dB (at a BBB. of 10“) and 2 dB (at a BER of 10‘”)
`are obtained. The measured coding gain by the FEC at a
`BER of 10“ is about 2.5 dB. The residual bit errors have
`been reduced below the order of 1 x 10"“. The de-
`
`modulated e'ye pattern is presented in Fig. 10.
`The overall filter system should be designed to mini—
`mize intersymbol and interchannel (adjacent carrier) in-
`
`5
`
`

`

`334
`
`lEEE IOURerL 0N SELECTED AREAS IN COMMUNICATIONS. VOL. SAC-5. N0. 3. APRIL I98?
`
`a! .fi—
`.Pl
`‘-
`'r.
`__
`
`-3.‘5'-..L
`
`_
`--.
`fl.
`-.
`
`:—
`
`
`H: IDMHz/div, v : lOdB/div
`
`lF BW : 300kHz
`
`Video BW : 300Hz
`
`(b)
`
`H I 2MHz/div, V I IOdB/div
`
`IF BW: lOOkHz
`
`Video SW 1 IOOHz
`
`Fig. 1!. Spectmm characteristics. (a) BPF output spectrum. (b) Dcmod—
`ulated Spectrum.
`
`terferences. From these requirements, overall spectrum
`shaping of the system is designed to be Nyquist‘s cosine
`rollofihx = 0.5).
`
`The transmitting and receiving filters are designed as
`
`Hllf) = JRoMfl/SU)
`
`H2ffl = JRoMfl/Btf)
`
`(15)
`
`(16}
`
`where
`
`Roi! (f) = Rollofi‘ filter transfer function
`S(_ f)
`NR2 amplitude spectrum
`ii
`Bi f) Multicarrier branch filter transfer function.
`
`newno
`n:u-
`
`BER=1X10"
`r=lflns
`
`- wit hem adjacent
`carrier interference
`' with adjacent
`”carrier interference
`
`.
`
`{d3} MI: 10
`Notchdmth
`
`10
`5
`—15—10 ‘5 fl
`Relative notch Ioeatian {MHz}
`r ' delay difference between direct and
`interfering rats
`
`IS
`
`Fig. ll. Equipment signatures for 256 QAM.
`
`Multicarrier branch filter B( f) is designed as the five
`stage Butterworth filter with 3 dB bandwidth normalized
`by clock frequency, RT, of 1.6.
`The BPF output spectrum and demodulated spectrum of
`256 QAM signals are shown in Fig. I]. The measured
`D/U of the adjacent carrier interference at EFF output
`under normal conditions is 18 dB. The 256 QAM signal
`is coherently detected, and then rolloff filtered by the re—
`ceiving low-pass filter shown in (16). The measured 0/ U
`at the decision circuit input under normal conditions is
`54.9 dB, which satisfies almost the design criteria, 55 dB.
`To clarify the effect of adjacent carrier interference, the
`equipment signatures at BER of 10‘“ are measured using
`a two-ray fading simulator with 10 ns delay difference.
`Fig. 12 shows the measured results. The transversal
`equalizer is a seven-tap baseband type with MLE (maxi-
`mum level error) algorithm [6]. [7]. As shown in this fig-
`ure, there is a small difference between two signatures
`with and without the adjacent carrier interference.
`
`V. CONCLUSION
`
`This paper has presented the 256 QAM multicarrier
`modem configuration and several hardware techniques.
`New techniques presented here have become powerful
`tools to improve the modem performance. Particularly, 1)
`an accurate 256 QAM modulator employing the newly de-
`veloped monolithic multiplier IC, 2) the carrier recovery
`circuit with control mode selection, 3) high«1evel decision
`circuit and 4) PEG coding, have described in detail.
`Moreover,
`the BER characteristic and signatures have
`been presented as an overall modem perfon-nance. The
`equivalent CN‘R degradation of 1 dB (at 3 BER of 10—4)
`and 2 dB (at a BER of 10‘9} have been obtained by the
`FEC and seven-tap baseband transverse] equalizer. The
`residual bit errors have been reduced below the order of
`10“". The comparison between twu signatures with and
`without adjacent carrier interference has indicated that the
`degradation due. to this interference is negligible.
`
`APPEN DIX
`
`In Fig. 7, the AID converter input signal aft) is written
`
`as
`
`u(t)=a(r) ' r.l(t)
`
`(l7)
`
`6
`
`

`

`NAKAMURA et a!.: 256 QAM MODEM FOR MULTICARRIER 400 Mbit/s DIGITAL RADIO
`
`335
`
`where
`
`Cam =f(!) * sen Wt) ' IM!)
`V50) = W) - t«‘(r)
`
`= [a(t) — 1] - y(:)‘
`
`(18)
`
`(19)
`
`fl!) = low-pass filter impulse response
`* = convolution.
`
`From (18) and (19).
`Ca(t) =f(t) a: sgn {1710) - [ch] - 1] - 00)}.
`(20)
`
`Nonlinear function; sgn ( ). followed by a low-pass fil-
`ter can be linearized as follows.
`
`Ca(r) :- Kg -f(r) - [a(t) — 1] - v(t).
`
`(21)
`
`Japanese)
`[10] T. Sakai et .31.. "Gigabit logic bipolar technology: Advanced super
`self-aligned process technology." Electron. Lena. vol. 19. pp. 283—
`284. Apr. 1983.
`'
`[[1] I. Horikawa er 131.. “Design and performance ofa 200M!) {s 16 OM
`digital radio system.“ JEEE Trans. Con-imam. vol. COM~2'J. pp.
`1953-1953. Dec. 1979.
`112] A. Leclert er alt. "Universal carrier recovery loop for QASK and
`PSK signal sets.” IEEE Trans. Cornmnn.. vol. COM-31. pp. 130-
`136. Jan. 1983.
`[13] M. Mattie at at. "Characteristic of 16 QAM carrier recovery phase
`locked loop with control mode selection function," Trans. JECE Ja-
`pan, vol. 168-3, no. 3. pp. 337-394, 1985 {in Japanese)
`[14] 'Y. Nakamura et (11.. “Characteristics of multi-level decision circuit
`with automatic threshold control for 256 QAM digital radio system."
`Paper Tech. Group. TGCS Ell-'12. IECE Japan. 1934 {in Japanese)
`[15] K. Nakamura. “A class of error correcting codes for DPSK chan-
`nels." in Proc. Int. Conf. Comman.. 1979. pp. 45.4.1—4S.4.S.
`
`By applying Laplacian “s” to (I?) and (21),
`
`17(3) = 14(5) ° V0?)
`
`(30(3) = Kg ' FU) ' [Am - 1] ' V(S)-
`
`Therefore,
`
`on) = m) + kgl—Hs) (30(3)
`
`when the dc amplifier operates linearly,
`
`21(5) = m - Cn(s)
`m = gain constant.
`
`From (24) and (25). (11) can be derived.
`
`ACKNOWLEDGMENT
`
`(22)
`
`(23)
`
`(24)
`
`(25)
`
`
`
`Yasuhisa Nakamura was born in Yokohama. Ja-
`pan. on December 3. 1956. He received the 13.8.
`degree in applied physics from Tokyo University.
`Tokyo. Japan. in 1930.
`He joined the NTT Electrical Communications
`Laboratories. Nippon Telegraph and Telephone
`Corporation. Tokyo, Japan. in 1930. From 1980
`to 1933. he was engaged in research concerning
`modulation techniques on subseriber digital radio.
`Since 1983 he has been Working on development
`of 256 QAM modem.
`Mr. Nakamura is a member of the Institute of Electronics and Com-
`munications Engineers of Japan.
`
`The authors wish to express their appreciation to Dr.
`M. Shinji. Dr. K. Kohiyama. and Dr. 0. Kurita for their
`fruitful advice and suggestions. Dr. S. Kornaki, Mr. T-
`Murase, and Mr. N. lrnai provided many ideas and sug-
`gestions throughout the course of this study.
`
`REFERENCES
`
`[1] Y. Sailo at 01.. “SL-Dl digital radio system." in Proc. Int. Cortf.
`Contra-lam. 1932. pp. 2B.l.l-2B.l.7.
`[2] P. Dupuis era!” "16 QAM modulation for high capacity digital radio
`system." IEEE Trans. Comm. . vol. COM—27. pp. 1771-1782. Dec.
`1979.
`
`[3] T. Noguchi at at. “fiGHz 135 MBPS digital radio system with 64
`QAM modulation." in Proc. Int. Cnnfi Common. 1983. pp. F2.4.l-
`F2.4.6.
`[4] J. D. McNicol er oi. . "Design and application of the RD-4A and RD-
`6A 64QAM digital radio systems.“ in Proc.
`int. Can}: Commem.
`1984. PP. 646-652.
`[5] "r'. Saito at o!.. "256 QAM modem for high capacity digital radio
`systgm.“ JEEE Trans. Con-imam. vol. COM—34. pp. 799-805. Aug.
`193 .
`[6]. ——-—. ”400W / s 256 QAM digital microwave radio system perfor-
`mance" in Proc. Int. Conf. Commun.. 1986. pp. 456—465.
`[7] H. lchikawa at £11.. “256 QAM multi-carrier 400Mb/ s microwave
`radio system field tests,“ in Proc. Int. Con}: Comman.. 1987. to be
`published.
`_
`[8] Y. Saito at of., “Feasibility considerations of high-level QAM multi-
`carrier system." in Proc. Int. Conf. Commun.. 1934. pp. 665-671.
`[9] N. [run] at 31.. "Design of monolithic multiplier IC for 256 QA‘M
`system." Paper Tech. Group. TGCS 85-27. IECE Japan. 1985 [in
`
`_
`
`
`
`Yoichi Salto (M'SZ) was born in Chiba. Japan.
`on February 7, 1949. He received the 3.8. degree
`in electrophysics engineering from Tokyo Insti~
`lute of Technology. Tokyo, Japan. in 19'12.
`Since joining the NW Electrical Communica—
`tions Laboratories, Nippon Telegraph and Tele-
`phone Corporation. Tokyo. in 1972. he has been
`engaged in research and development on l6 and
`256 QAM modem and transversal equalization for
`digital microwave radio system.
`Mr. Saito is a member of the Institute of Elec-
`tronics and Communications Engineers of Japan.
`
`
`
`Salon! Aikawa was born in Tokyo. Japan. on
`January 8. 1962. He receivedthe 3.5. degree in
`electrical engineering from Yokohama National
`University in 1984.
`Since joining the NT’I‘ Electrical Communica-
`tions Laboratories. Nippon Telegraph and Tele-
`phone Corporation. Tokyo. Japan. 1984. he has
`been engaged in research and development on 256
`QAM modern.
`Mr. Aikawa is a member of the institute of
`Electronics and Communications Engineers of
`Japan.
`
`7
`
`