Technology Tutorial
`
`Progressive Semiconductor Solutions LLC v. Qualcomm Technologies, Inc.
`8:13-cv-01535 ODW (JEMx)
`
`Progressive Semiconductor Solutions LLC v. Marvell Semiconductor, Inc.
`8:14-cv-00330 ODW (JEMx)
`
`July 16, 2014
`
`1
`
`Qualcomm Exhibit 1009
`IPR Petition - USP 6,862,208
`
`Page 1
`
`
`
`Progressive Semiconductor Solutions LLC v. Qualcomm Technologies, Inc.
`8:13-cv-01535 ODW (JEMx)
`
`Progressive Semiconductor Solutions LLC v. Marvell Semiconductor, Inc.
`8:14-cv-00330 ODW (JEMx)
`
`July 16, 2014
`
`1
`
`Qualcomm Exhibit 1009
`IPR Petition - USP 6,862,208
`
`Page 1
`
`
`
`Introduction to Memory
`
`Introduction to Memory
`
`Page 2
`
`2
`
`Page 2
`
`
`
`Semiconductor Memory
`
`Memory is found in all sorts of well-known electronic devices
`
`3
`
`Page 3
`
`
`
`Memory Chips
`
`Inside electronic devices are semiconductor chips
`
`Memory Chip
`
`4
`
`Page 4
`
`
`
`Forms of Memory
`
`Some memory is in the form of a dedicated memory chip
`
`5
`
`Page 5
`
`
`
`Forms of Memory
`
`Other memory is integrated into other chips such as processors
`
`Processor
`
`Integrated Memory
`
`6
`
`Page 6
`
`
`
`Memory Stores Data
`
`• Memory’s purpose in electronic
`devices is to store data for later use
`
`• There are many types of memory,
`such as ROM, RAM, flash, and others
`
`• Data is stored in binary form
`
`7
`
`Page 7
`
`
`
`Binary Data
`
`Electronic data is represented as strings of 0s and 1s
`
`
`Text Message
`
`Image
`
`8
`
`Page 8
`
`
`
`Binary Data
`
`Electronic data is represented as strings of 0s and 1s
`
`
`00101001010010101
`01010101110000010
`10010100101010101
`01011100000101001
`01001010101010101
`11000001010101010
`11100000100010101
`
`Text Message
`
`0010100101
`0010101010
`1010111000
`0010100101
`0010101010
`1010111000
`0010100101
`
`Image
`
`0010100101001010101
`0101011100000101001
`0100101010101010111
`0000010100101001010
`1010101011100000101
`0010100101010101001
`0010100101011010101
`
`9
`
`Page 9
`
`
`
`Binary Data in Electronics
`
`•
`
`•
`
`‘0’ may be represented by a low voltage level
`
`‘1’ may be represented by a high voltage level
`
`1
`
`0
`
`1
`
`1
`
`0
`
`0
`
`0
`
`1
`
`1
`
`0
`
`V
`
`0
`
`10
`
`Page 10
`
`
`
`Writing and Reading Data From Memory
`
`Writing Data Into Memory
`
`Memory
`
`Document
`
`0010100101001010101
`0101011100000101001
`0100101010101010111
`0000010100101001010
`1010101011100000101
`0101010111000001000
`1010110101010111000
`0010101010101110000
`
`11
`
`Page 11
`
`
`
`Writing and Reading Data From Memory
`
`Reading Data From Memory
`
`Memory
`
`Document
`
`0010100101001010101
`0101011100000101001
`0100101010101010111
`0000010100101001010
`1010101011100000101
`0101010111000001000
`1010110101010111000
`0010101010101110000
`
`12
`
`Page 12
`
`
`
`Memory Array
`
`Semiconductor memory has a basic array structure
`
`13
`
`Page 13
`
`
`
`Memory Array
`
`An array is divided into individually addressed cells
`
`00
`
`01
`
`02
`
`03
`
`04
`
`05
`
`06
`
`07
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`Cell
`
`20
`
`21
`
`22
`
`23
`
`24
`
`25
`
`26
`
`27
`
`30
`
`31
`
`32
`
`33
`
`34
`
`35
`
`36
`
`37
`
`40
`
`41
`
`42
`
`43
`
`44
`
`45
`
`46
`
`47
`
`14
`
`Page 14
`
`
`
`Memory Array
`
`Each address in the memory array has a column identifier and a row identifier
`
`0
`00
`
`1
`01
`
`2
`02
`
`Columns
`3
`4
`03
`04
`
`5
`05
`
`6
`06
`
`7
`07
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`20
`
`21
`
`22
`
`23
`
`24
`
`25
`
`26
`
`27
`
`30
`
`31
`
`32
`
`33
`
`34
`
`35
`
`36
`
`37
`
`40
`
`41
`
`42
`
`43
`
`44
`
`45
`
`46
`
`47
`
`0
`
`1
`
`2
`
`3
`
`4
`
`Rows
`
`15
`
`Page 15
`
`
`
`16
`
`Memory Array
`
`Each cell stores one bit (0 or 1) of data
`
`Columns
`3
`4
`03
`04
`
`0
`
`13
`
`0
`
`23
`
`0
`
`33
`
`1
`
`43
`
`1
`
`1
`
`14
`
`1
`
`24
`
`1
`
`34
`
`0
`
`44
`
`1
`
`5
`05
`
`1
`
`15
`
`0
`
`25
`
`0
`
`35
`
`0
`
`45
`
`1
`
`6
`06
`
`1
`
`16
`
`1
`
`26
`
`1
`
`36
`
`0
`
`46
`
`0
`
`7
`07
`
`0
`
`17
`
`0
`
`27
`
`0
`
`37
`
`1
`
`47
`
`0
`
`1
`01
`
`1
`
`11
`
`0
`
`21
`
`0
`
`31
`
`0
`
`41
`
`1
`
`2
`02
`
`0
`
`12
`
`1
`
`22
`
`1
`
`32
`
`0
`
`42
`
`0
`
`0
`00
`
`0
`
`10
`
`0
`
`20
`
`1
`
`30
`
`1
`
`40
`
`1
`
`0
`
`1
`
`2
`
`3
`
`4
`
`Rows
`
`Page 16
`
`
`
`Memory Access
`
`Addressing circuitry is used to access a desired memory cell for a read or write
`Column Address
`Bit lines
`2
`02
`
`Row
`Address
`Word line
`
`0
`00
`
`1
`01
`
`Columns
`
`3 3
`4
`03
`04
`
`5
`05
`
`6
`06
`
`7
`07
`
`1
`
`0
`
`Selected Cell
`11
`12
`
`0
`
`21
`
`0
`
`31
`
`0
`
`41
`
`1
`
`1
`
`22
`
`1
`
`32
`
`0
`
`42
`
`0
`
`0
`
`13
`
`0
`
`23
`
`0
`
`33
`
`1
`
`43
`
`1
`
`1
`
`14
`
`1
`
`24
`
`1
`
`34
`
`0
`
`44
`
`1
`
`1
`
`15
`
`0
`
`25
`
`0
`
`35
`
`0
`
`45
`
`1
`
`1
`
`16
`
`1
`
`26
`
`1
`
`36
`
`0
`
`46
`
`0
`
`0
`
`17
`
`0
`
`27
`
`0
`
`37
`
`1
`
`47
`
`0
`
`17
`
`0
`
`10
`
`0
`
`20
`
`1
`
`30
`
`1
`
`40
`
`1
`
`
`
`0 0
`
`1
`
`2
`
`3
`
`4
`
`Rows
`
`Page 17
`
`
`
`Memory Operation
`
`Memory Operation
`
`Page 18
`
`18
`18
`
`Page 18
`
`
`
`Read Operation
`
`Address
`
`Read Address: A
`
`Read Address A
`(Row 3, Column 5)
`
`Addressing
`Circuitry
`
`Memory
`Array
`
`Sense
`Amplifier
`
`Latch
`
`Data
`
`19
`
`Page 19
`
`
`
`Read Operation
`
`Address
`
`Read Address A
`(Row 3, Column 5)
`
`Addressing
`Read Address: A
`Circuitry
`
`Memory
`Array
`
`Sense
`Amplifier
`
`Latch
`
`Data
`
`20
`
`Page 20
`
`
`
`Read Operation
`
`Address
`
`Read Address A
`(Row 3, Column 5)
`
`Addressing
`Circuitry
`
`Read Address: A
`
`Memory
`Array
`
`Sense
`Amplifier
`
`Latch
`
`Data
`
`21
`
`Page 21
`
`
`
`Read Operation
`
`1
`
`Data at Address: A
`
`Addressing
`Circuitry
`
`Memory
`Array
`
`Address
`
`Read Address A
`(Row 3, Column 5)
`
`Sense
`Amplifier
`
`Latch
`
`Data
`
`22
`
`Page 22
`
`
`
`Read Operation
`
`1
`
`Data at Address: A
`
`Addressing
`Circuitry
`
`Memory
`Array
`
`Address
`
`Read Address A
`(Row 3, Column 5)
`
`Sensing and
`Amplifying
`
`Sense
`Amplifier
`
`Latch
`
`Data
`
`23
`
`Page 23
`
`
`
`Address
`
`Read Address A
`(Row 3, Column 5)
`
`Addressing
`Circuitry
`
`Read Operation
`
`1
`
`Memory
`Array
`
`Amplifying
`
`Sense
`Data at Address: A
`Amplifier
`
`Latch
`
`Data
`
`24
`
`Page 24
`
`
`
`Address
`
`Read Address A
`(Row 3, Column 5)
`
`Addressing
`Circuitry
`
`Read Operation
`
`1
`
`Memory
`Array
`
`Sense
`Amplifier
`
`Data at Address: A
`Latch
`
`Data
`
`25
`
`Page 25
`
`
`
`Memory Read Circuitry
`
`Memory Read Circuitry
`
`Page 26
`
`26
`26
`
`Page 26
`
`
`
`Specialized Circuitry
`
`Memory operations depend upon
`several specialized components:
`
`Memory
`Array
`
`• Memory cells
`
`• Sense amplifier
`
`• Latch
`
`Sense
`Amplifier
`
`Latch
`
`Data
`
`27
`
`Page 27
`
`
`
`Specialized Circuitry
`
`Memory operations depend upon
`several specialized components:
`
`Memory
`Array
`
`• Memory cells
`
`• Sense amplifier
`
`• Latch
`
`Sense
`Amplifier
`
`Latch
`
`Data
`
`28
`
`Page 28
`
`
`
`Memory Cell
`
`• The cell stores either a
`relatively large voltage (a
`ONE) or a relatively small
`voltage (a ZERO).
`
`• The value is “written” into
`the cell as a voltage level
`
`• The cell, like many
`components in the memory
`circuit, has transistors as
`a basic building block
`
`Word line
`
`Basic RAM Cell
`
`Bit line
`
`Bit line
`
`29
`
`Page 29
`
`
`
`Memory Cell
`
`• Generally, data stored in the
`memory cell is sent in
`differential form along the bit
`lines.
`
`• The differential signals are
`referred to here as “bit line”
`and “bit line” bar. The “bar”
`indicates that the signal is the
`complement of the non-bar
`signal.
`
`Word line
`
`Bit line
`
`Bit line
`
`30
`
`Page 30
`
`
`
`Differential signals
`
`• Differential signals are complementary – so if one bit line is slightly
`below a reference voltage, the complementary bit line will be slightly
`above that same reference voltage. This allows the sense amplifier to
`more easily sense a small positive or negative voltage.
`
`Voltage
`
`bit
`
`Differential
`
`
`Vref
`
```bit
`
`Time
`
`31
`
`Page 31
`
`
`
`Transistor
`
`Commonly has three terminals
`
`Drain (D)
`
`Gate (G)
`
`Source (S)
`
`32
`
`Page 32
`
`
`
`Transistor Operation
`
`Operated as switches controlled by voltage on the gate
`
`Drain (D)
`
`Gate (G)
`
`LOW
`VOLTAGE
`
`OFF
`
`Source (S)
`
`33
`
`Page 33
`
`
`
`Transistor Operation
`
`Operated as switches controlled by voltage on the gate
`
`Drain (D)
`
` 2 VOLTS
`
`Gate (G)
`
`HIGH
`VOLTAGE
`
`ON
`
`Source (S)
`
`34
`
`Page 34
`
`
`
`Types of Transistors
`
`There are two common types of transistors
`
`N Type
`
`P Type
`
`35
`
`Page 35
`
`
`
`Specialized Circuitry
`
`Memory operations depend upon
`several specialized components:
`
`Memory
`Array
`
`• Memory cells
`
`• Sense amplifier
`
`• Latch
`
`Sense
`Amplifier
`
`Latch
`
`Data
`
`36
`
`Page 36
`
`
`
`Sense Amplifier (Sense Amp)
`
`• A sense amp is a circuit that can
`sense small voltages output from
`the memory and amplify them
`
`• Commonly can be built of
`transistors
`
`• A common configuration is a
`differential sense amp
`
`BL
`
`BL
`
`(Large Positive Voltage)
`Vdd
`
`
`Sense
`Signal
`
`GND
`(Generally Zero Volts)
`
`37
`
`Page 37
`
`
`
`Reading Through Sensing
`
`• The sense amp detects a voltage
`difference between the bit lines
`and amplifies it
`
`• The sense amp outputs the stored
`memory cell value
`
`Memory Cell
`
`BL
`
`BL
`
`Sense
`Amp
`
`Sense Signal
`
`38
`
`Page 38
`
`
`
`Specialized Circuitry
`
`Memory operations depend upon
`several specialized components:
`
`Memory
`Array
`
`• Memory cells
`
`• Sense amplifier
`
`• Latch
`
`Sense
`Amplifier
`
`Latch
`
`Data
`
`39
`
`Page 39
`
`
`
`Latches
`
`• A latch is a circuit that stores one bit of data. There are
`many kinds of clocked and unclocked latches.
`
`• A clocked latch will rely on a clock signal for timing
`purposes.
`
`• An unclocked latch does not depend on a clock signal
`for timing purposes (*Subject to further clarification).
`
`Clocked
`
` Un-Clocked
`
`needs an additional signal to
`instruct it to store new data
`
`will store new data when it sees it.
`No additional signals required.
`
`D
`Clock
`D
`
`S
`
`EN
`
`R
`
`Q
`
`Q
`
`D
`
`D
`
`S
`
`R
`
`Q
`
`Q
`
`40
`
`Page 40
`
`
`
`Unclocked Latches
`
`• Examples of unclocked latches
`
`
`
`Cross-Coupled
`D
`Inverters
`
``D
`
`D
`
``D
`
`D
`
``D
`
`Cross-Coupled
`NAND Gates
`(SR Latch)
`
`Cross-Coupled
`NOR Gates
`(SR Latch)
`
``Q
`
`Q
`
``Q
`
`Q
`
`41
`
`Page 41
`
`
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