(12)
`
`United States Patent
`Snyder et al.
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 6,338,109 B1
`*J an. 8, 2002
`
`US006338109B1
`
`(54) MICROCONTROLLER DEVELOPMENT
`SYSTEM AND APPLICATIONS THEREOF
`FOR DEVELOPMENT OFA UNIVERSAL
`
`SERIAL BUS MICROCONTROLLER
`
`(75) Inventors: Warren S. Snyder, Snohomish;
`Frederick D. J accard, Woodinville,
`bOth Of WA (US)
`
`5,319,754 A * 6/1994 Meinecke et a1. ........ .. 710/130
`5,329,471 A * 7/1994 Swoboda et a1. ........... .. 703/23
`5,426,421 A * 6/1995 Gray ................... .. 395/200.53
`
`.
`.
`(List continued on next page.)
`
`FOREIGN PATENT DOCUMENTS
`
`W0
`
`WO 97/36230
`
`10/1997
`
`(*) Notice:
`
`OTHER PUBLICATIONS
`
`(73) Assignee: Cypress Semiconductor Corp., San
`J
`CA US
`Universal Serial Bus Speci?cation, Revision 1.0, pp. 1—268,
`056’
`(
`)
`Jan‘ 15> 1996'
`This patent issued on a continued pros-
`Universal Host Controller Interface (UHCI) Design Guide,
`ecution application ?led under 37 CFR
`Revision 1.1, Intel, pp. 1—41, Mar. 1996.
`1,53(d), and is subject to the twenty year
`Patent term Provisions of 35 USC Warren Snyder, “Dual ROM Microprogrammable Micro
`154(a)(2)~
`processor and Universal Serial Bus Microcontroller Devel
`_
`_
`_
`_
`opment System”, US. Serial No. 08/705,807, Filed Aug. 30,
`sublectto any dlsclalmeri the term ofthls
`1996. (NOW US. Patent No. 5,859,993—Issued Jan. 12,
`patent is extended or adJusted under 35
`1999)
`U.S.C. 154(b) by 0 days.
`
`(21) Appl- NO-I 08/711,419
`(22) Filed:
`Aug- 30’ 1996
`
`(51) Int. Cl.7 .............................................. .. G06F 13/00
`(52) US. Cl. ..................... .. 710/129; 710/100; 710/126;
`710/127; 711/103; 714/29; 395/500
`(58) Field of Search ..................... .. 395/18305, 200.53,
`395/500, 306, 309, 307, 280; 703/23, 28;
`711/103; 714/29; 709/223; 710/ 129, 127,
`100, 126
`
`(56)
`
`References Cited
`U'S' PATENT DOCUMENTS
`
`9/1974 Stafford et al.
`3,833,888 A
`7/ 1977 Dummermuth
`4,038,533 A
`8/1977 Grllnef et a1-
`4,042,972 A
`EgeTh-_-t~-~t~~~1 ~~~~~~~~~~~~ " 395/280
`2 *
`4/1985 Fencsik et a1‘
`4,511,968 A
`5,047,926 A * 9/1991 K110 et al. ........... .. 395/183.05
`5,241,631 A * 8/1993 Smith et al. .............. .. 395/306
`5,313,618 A * 5/1994 Pawloski ................... .. 703/28
`
`,
`
`,
`
`nos 1 a e a .
`
`Primary Examiner—AyaZ R. Sheikh
`Assistant Examiner—FrantZ Blanchard Jean
`Attorney, Agent, or Firm—Christopher P. Maiorana,
`
`ABSTRACT
`(57)
`Amicrocontroller including a system bus; a microprocessor
`coupled to the system bus and con?gured to transfer data and
`control signals over the system bus; a memory device
`coupled to the microprocessor and mapped to the system bus
`and con?gured to store microprogram instructions for
`execution by the microprocessor; a controller coupled to the
`system bus and con?gured to transfer data and control
`'signals to the microprocessor over the system bus; a host
`interface coupled to the system bus and con?gured to
`interface to a host computer and receive the data and the
`control signals over the system bus from the microprocessor;
`and an I/O interface coupled to the system bus and con?g
`ured to interface to at least one I/O device and receive the
`data and the control signals over the system bus from the
`mlcroprocessor'
`
`-
`
`23 Claims, 2 Drawing Sheets
`
`mums
`
`DATA
`
`USE 1m 1
`
`‘2:
`12s
`REGESTFRS
`
`BLACKBERRY Ex. 1015, page 1
`
`

`

`US 6,338,109 B1
`Page 2
`
`US. PATENT DOCUMENTS
`
`5,495,593 A * 2/1996 Elmer 9t a1~ -------------- -- 711/103
`5546562 A * 8/1996
`--
`5,664,123 A * 9/1997 Lee et a1. ................. .. 395/309
`5,675,813 A 10/1997
`5,684,721 A * 11/1997 Swoboda et a1. ......... .. 364/578
`
`5,689,684 A * 11/1997 Mulchandani et a1. ...... .. 703/23
`5,691,994 A * 11/1997 Acosta et a1. ............ .. 371/40.1
`5,758,107 A * 5/1998 Robles et a1. ............. .. 395/307
`5,805,792 A * 9/1998 Swoboda 618.1. .
`703/23
`5941979 A * 8/1999 LentZ _____________ u
`_ 712/33
`
`* cited by examiner
`
`BLACKBERRY Ex. 1015, page 2
`
`

`

`U.S. Patent
`
`Jan. 8, 2002
`
`Sheet 1 of 2
`
`US 6,338,109 B1
`
`
`
`
`2
`
`INSTRUCTION
`RAM
`
`
`
`SYSTEM
`STATE
`REG ESTERS
`
`10a
`
`100
`
`(D
`3
`E g
`o I
`
`%:E’\
`
`
`
`SYSTEM BUS LOGIC
`
`so
`TRACE REGESTER
`
`
`
`|
`I
`L ------------------------- “‘
`CONTROL SIGNALS
`(SOI, IOW, IOR. MW, MR,&BRQ)
`
`-II 10b
`
`
`
`USB INTERFACE
`
`
`
`12 -
`12b
`3 I--
`REGESTERS
`
`
`
`F I G _ 1
`
`BLACKBERRY EX. 1015, page 3
`
`6
`
`USB
`
`17
`
`I/O PORTS
`
`19
`
`I
`1
`:
`
`II
`
`II
`
`l
`
`16
`
`USB
`
`HOST
`
`18
`I/O
`
`DEVICE
`
`7
`
`DEVELOPER
`ACCESS
`DEVICE
`
`
`
`KEYBOARD
`
`BLACKBERRY Ex. 1015, page 3
`
`

`

`U.S. Patent
`
`Jan. 8,2002
`
`Sheet 2 0f 2
`
`US 6,338,109 B1
`
`50\
`BITNUMBER: 7 6 5 4 3 21 0
`X X X X X X
`
`SINGLE / \KRUN
`STEP52
`51
`FIG. 2
`
`o (RUN 51=1)
`N
`200\
`EXECUTE ONE
`INSTRUCTION
`
`300
`
`(SINGLE STEP 52=o)
`
`SINGLE STEP 52=1
`40D \YES (
`)
`CLR/ RESET
`(RUN 51=o)
`
`FIG. 3
`
`BLACKBERRY Ex. 1015, page 4
`
`

`

`US 6,338,109 B1
`
`1
`MICROCONTROLLER DEVELOPMENT
`SYSTEM AND APPLICATIONS THEREOF
`FOR DEVELOPMENT OF A UNIVERSAL
`SERIAL BUS MICROCONTROLLER
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`This invention relates to microprocessor development
`systems, and more particularly to a Universal Serial Bus
`(“USB”) microcontroller development system con?gured to
`aid in the design, debug, and testing of USB compliant
`devices and ?rmware.
`2. Discussion of Background
`USB is a peripheral bus standard that alloWs computer
`peripherals to be attached to a personal computer Without the
`need for specialiZed cards or other vendor speci?c hardWare
`attachments. The USB standard speci?es a common con
`?guration for the connection of Well knoWn peripherals such
`as CD-ROM, tape and ?oppy disk drives, scanners, printers,
`keyboards, joysticks, mice, telephones, modems, etc. In
`addition to Well knoWn peripheral devices, the USB standard
`has ?exibility to accommodate less knoWn and neWly devel
`oped technologies. Information about the USB standard,
`including the speci?cation for building USB compliant
`devices, is currently available free of charge over the Inter
`net.
`Developers Wishing to implement USB devices must
`build that device to the USB standard. Prior to fabricating
`IC’s for USB standard devices, a developer Will spend a
`signi?cant amount of resources in testing and re?nement of
`prototypes. An ef?cient method for testing USB compliant
`devices is needed to reduce the costs associated With pro
`totype development and testing of those devices.
`The design and manufacture of electronic devices such as
`counters, state machines, specialiZed registers, and micro
`processors is currently aided by technologies that alloW
`engineers to specify design characteristics of a circuit, such
`as storage device siZe, register types, connections and asso
`ciated logic, in a HardWare Description Language (“HDL”).
`This source code or HDL is then compiled, alloWing the
`electronic device to be simulated and debugged While imple
`menting the speci?ed circuit characteristics. Once the opera
`tion of device is veri?ed, the compiled source code can be
`mapped to a speci?c architecture such as Application Spe
`ci?c Integrated Circuits (“ASICs”) or Field Programmable
`Gate Arrays (“FPGAs”). This alloWs the system designer to
`produce a device With design ?exibility and portability into
`various architecture families.
`As an example, a 3-bit shift register can be implemented
`in a HDL such as Register Transfer Language (“RTL”) With
`the folloWing RTL statements:
`
`ENTITY shifter3 IS port (
`clk :
`IN BIT;
`x
`:
`IN BIT;
`(10
`OUT BIT;
`ql
`OUT BIT;
`(12
`OUT BIT;
`END shifter3;
`ARCHITECTURE struct OF shifter3 IS
`SIGNAL qOitemp, qlitemp, qZftemp : BIT;
`BEGIN
`d1 : DFF PORT MAP (x,clk,q0ftemp);
`d2 : DFF PORT MAP (qOitemp,clk,q1itemp);
`d3 : DFF PORT MAP (q1itemp,clk,q2itemp);
`
`-continued
`
`qO <= qOitemp;
`q1 <= qlitemp;
`q2 <= qZitemp;
`END struct;
`
`Which de?nes the inputs and outputs of the shifter and then
`maps those bits to a series of D Flip-Flops. After compiling
`the source code and debugging the circuit, a netlist can be
`generated for a speci?c family of FPGA or ASIC devices to
`produce the circuit With the desired functionality.
`
`15
`
`25
`
`35
`
`45
`
`55
`
`65
`
`SUMMARY OF THE INVENTION
`
`Accordingly, one object of the present invention is to
`provide a ?exible USB microcontroller development system
`that alloWs for testing of USB compliant devices. The
`microcontroller includes a microprocessor With instruction
`RAM, a controller With a computer interface (e.g., RS-232)
`to a personal computer or other external computing device,
`data RAM, USB logic and registers for interfacing to a USB
`host computer, and I/O logic and registers for interfacing to
`an I/O device. The USB microcontroller development sys
`tem includes the microcontroller, an external computer, a
`USB host computer, and an I/O device. The USB micro
`controller development system alloWs both the micropro
`cessor or an attached external computer to control the
`microcontroller. This is accomplished by mapping the USB
`microcontroller system state Which includes the contents of
`the data RAM, the microprocessors system state registers
`including system state registers corresponding to the con
`tents of the instruction RAM, the USB logic registers, and
`the I/O logic registers to a system bus. The controller or
`microprocessor places address, data, and control signals on
`the system bus Which are decoded by various logic to alloW
`reading or Writing of the system state. The controller reads
`or Writes the instruction RAM by reading or Writing a
`program counter and an instruction register, included as part
`of the microprocessor’s system state registers, via the sys
`tem bus. Accordingly, the external computer connected to
`the controller via the RS-232 bus can read or Write the USB
`microcontroller system state to aid in the design, debug, and
`testing of USB compliant devices and ?rmWare.
`It is also an object of the present invention to provide a
`development access device on the external computer for
`providing a user a graphical interface for controlling the
`USB microcontroller. The development access device dis
`playing menus, buttons, text boxes etc. corresponding to the
`microprocessor’s system state registers, the contents of the
`instruction RAM, the USB logic registers, and the I/O logic
`registers. The user, after selecting the appropriate menu,
`button, or ?lling in the appropriate text box, can read or
`Write the corresponding microprocessor’s system state
`registers, the contents of the instruction RAM, the USB
`logic registers, and the I/O logic registers via the external
`computer and computer interface to control the USB micro
`controller.
`It is yet another object of the present invention to provide
`a method for implementing the above USB microcontroller
`development system utiliZing a HardWare Description Lan
`guage. By utiliZing a HardWare Description Language, the
`design engineers are free to concentrate on the design of
`important features of the system and it’s functionality rather
`than a gate level implementation of the system. After deter
`mining top level characteristics and functional blocks of the
`system, an HDL program describing those characteristics
`
`BLACKBERRY Ex. 1015, page 5
`
`

`

`US 6,338,109 B1
`
`3
`and functional blocks is developed and debugged. In the
`present invention, HDL implemented processes are used in
`designing various functional blocks of the USB microcon
`troller development system. The USB microcontroller
`development system designed using HDL is then mapped to
`FPGAs and packaged onto a single printed circuit board
`along With minimal additional logic such as EEPROMs and
`RAM.
`The above and other objects are achieved according to the
`present invention by providing a neW and improved micro
`controller including a system bus; a microprocessor coupled
`to the system bus and con?gured to transfer data and control
`signals over the system bus; a memory device coupled to the
`microprocessor and mapped to the system bus and con?g
`ured to store microprogram instructions for execution by the
`microprocessor; a controller coupled to the system bus and
`con?gured to transfer data and control signals to the micro
`processor over the system bus; a host interface coupled to
`the system bus and con?gured to interface to a host com
`puter and receive the data and the control signals over the
`system bus from the microprocessor; and an I/O interface
`coupled to the system bus and con?gured to interface to at
`least one I/O device and receive the data and the control
`signals over the system bus from the microprocessor.
`According to a second aspect of the present invention,
`there is provided a method of fabricating a microcontroller
`including steps of determining functional microprocessor
`requirements that Will at least provide execution control of
`the microprocessor; determining functional control circuit
`requirements that Will at least provide control of the micro
`processor; determining functional host interface require
`ments that Will at least provide an interface to a host
`computer; determining functional I/O interface requirements
`that Will at least provide an interface to at least one I/O
`device; de?ning the functional requirements of the
`microprocessor, the control circuit, the host interface and the
`I/O interface in an HardWare Description Language (HDL);
`compiling the HDL language to derive a circuit representa
`tion of the microcontroller; and mapping the circuit repre
`sentation onto one or more devices.
`According to a third aspect of the present invention, there
`is provided a microcontroller development system including
`a system bus; a microprocessor coupled to the system bus
`and con?gured to transfer data and control signals over the
`system bus; a memory device coupled to the microprocessor
`and mapped to the system bus and con?gured to store
`microprogram instructions for execution by the micropro
`cessor; an external computing device; a controller coupled to
`the system bus and con?gured to transfer data and control
`signals to the microprocessor over the system bus including
`a computer interface coupled to the system bus and con?g
`ured to transfer commands from the external computing
`device to the controller, the commands used by the controller
`to generate the data and the control signals for controlling
`the microprocessor; a host interface coupled to the system
`bus and con?gured to interface to the external computing
`device and receive the data and the control signals over the
`system bus from the microprocessor; at least one I/O device;
`and an I/O interface coupled to the system bus and con?g
`ured to interface to the at least one I/O device and receive the
`data and the control signals over the system bus from the
`microprocessor.
`According to a fourth aspect of the present invention,
`there is provided a method of development of a microcon
`troller in a microcontroller development system, including
`steps of loading a set of microprocessor instructions into a
`memory device coupled to a microprocessor of the
`
`10
`
`15
`
`25
`
`35
`
`45
`
`55
`
`65
`
`4
`microcontroller, the instructions loaded from an external
`computer coupled to a computer interface of the
`microcontroller, the external computer directed to load the
`microprocessor instructions by a developer access device
`running on the external computer;retrieving the set of micro
`processor instructions from the memory device for execu
`tion by the microprocessor; and controlling a starting,
`stopping, and single step execution of the microprocessor
`instructions by the microprocessor by the developer access
`device reading and Writing at least one register of system
`state registers of the microprocessor.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`A more complete appreciation of the invention and many
`of the attendant advantages thereof Will be readily obtained
`as the same becomes better understood by reference to the
`folloWing detailed descriptions When considered in connec
`tion With the accompanying draWings, Wherein:
`FIG. 1 is a block diagram implementing the USB micro
`controller development system according to the present
`invention;
`FIG. 2. is a bit-diagram of a trace register used on the USB
`microcontroller of FIG. 1; and
`FIG. 3. is a logic ?oW diagram shoWing the run/single step
`operations of the USB microcontroller development system
`of FIG. 1.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`Referring noW to the draWings, Wherein like reference
`numerals designate identical or corresponding parts
`throughout the several vieWs, and more particularly to FIG.
`1 thereof, the present invention includes a USB microcon
`troller development system 100, Which alloWs 100% testing
`of USB ?rmWare before the fabrication of ?nal ICs. The
`USB microcontroller development system 100 is designed
`using FPGAs, EEPROMs and RAMs, but may be imple
`mented in other electronic con?gurations including ASICs
`and/or microprocessor systems having a computing device
`With appropriately mapped system states and I/O interfaces,
`as described herein.
`The operation of the USB microcontroller development
`system Will be discussed With reference to FIGS. 1—3.
`In FIG. 1, FPGA1 1 and EEPROMs 3 implement a
`microprocessor 9. Within the microprocessor 9 is provided
`circuit block 11 including ALU 22, sequencer logic 34, and
`system state registers 11a. System state registers 11a are
`mapped to a system bus 10 through system bus logic 15
`Which includes a trace register 50. Microprocessor 9 is
`connected to instruction RAM 2 Which is used to store USB
`?rmWare under development.
`FPGA2 6 includes USB logic 12 Which provide an
`interface to a USB host computer 16 via USB bus 17 and
`includes registers 12a; I/O logic 13 Which provides an
`interface to an I/O device 18 via I/O ports 19 and includes
`registers 13a; and controller 5 Which provides a PC interface
`5a to the PC 7 (or other external computing device) via
`RS-232 bus 14. The USB logic 12, the I/O logic 13 and the
`controller 5 are coupled to the system bus logic 15 of
`microprocessor 9 via the system bus 10. In addition, system
`bus logic 15 includes trace register 50 Which is mapped to
`the system bus and can be accessed by either the controller
`5 or the microprocessor 9 to control the execution of
`?rmWare running in instruction RAM 2.
`As previously discussed, the purpose of the USB micro
`controller development system is to aid engineers in the
`
`BLACKBERRY Ex. 1015, page 6
`
`

`

`US 6,338,109 B1
`
`5
`design, debug and development of USB compliant devices
`and USB ?rmware. This is accomplished by providing a
`?exible USB microcontroller development system that
`alloWs data gathering and stimulation of the USB micro
`controller system state by providing the system state as
`addressed I/O, provides a computer interface to the USB
`microcontroller and alloWs a user to load and control execu
`tion of USB ?rmWare, an d provides an interface to a USB
`host computer and USB device under development.
`The data gathering and stimulation of the USB microcon
`troller system state Will noW be described.
`The USB microcontroller system state is determined by
`providing access to the folloWing registers: System state
`registers 11a of microprocessor 9 including (not shoWn): a
`program counter Which holds the address of the instruction
`RAM 2, an instruction register Which holds the data corre
`sponding to the program counter, stack pointers Which are
`addresses into data RAM 4, and temporary registers Which
`are used during execution of instructions from instruction
`RAM 2 by microprocessor 9. In addition the USB micro
`controller system state includes data memory contents in
`data RAM 4, USB logic registers 12a, I/O logic registers
`13a, and trace register 50 of system bus logic 15.
`The above registers are I/O mapped to the system bus 10,
`so that When an address is placed on the system bus the
`system bus logic 15, USB logic 12 and I/O logic 13 decode
`this address to determine Which logic block and Which
`register Within the logic block is being addressed.
`In addition, system bus 10 includes several control signals
`10a that are provided by microprocessor 9 or controller 5.
`From the microprocessor 9:
`SOI (start of instruction): tells the USB logic 12, U0 logic
`13, and controller 5 that a neW instruction is about to
`execute in instruction RAM 2;
`IOW (I/O Write): tells the USB logic 12, U0 logic 13, and
`controller 5 that the microprocessor 9 Wishes to Write to
`system state registers 11a, USB logic registers 12a, I/O
`logic registers 13a, or trace register 50;
`IOR (I/O read): tells the USB logic 12, U0 logic 13, and
`controller 5 that the microprocessor 9 Wishes to read
`system state registers 11a, USB logic registers 12a, I/O
`logic registers 13a, or trace register 50;
`MW (memory Write): tells the USB logic 12, U0 logic 13,
`and controller 5 that the microprocessor 9 Wishes to
`Write data to data RAM 4;
`
`15
`
`25
`
`35
`
`6
`Control signals IOW, IOR, MW and MR of control
`signals 10a are the same as from the microprocessor 9,
`except from the point of vieW of the controller 5, they share
`the same physical Wire/signal paths but the scope is deter
`mined by a master bus request (“BRQ”) control signal of
`control signals 10a. BRQ alloWs the controller 5 to preempt
`the microprocessor 9 and have the controller 5 control
`signals replace those of the microprocessor 9. The value/
`states of the controller 5 control signals 10a are generated
`from a ?nite state machine (not shoWn) in controller 5 that
`also communicates With the PC 7 using an RS-232 serial
`data protocol. In this Way controller 5 can take over control
`of the system from microprocessor 9 and read and Write the
`contents of the system state.
`The computer interface and execution control and loading
`of USB ?rmWare Will noW be described.
`In FIG. 1, PC 7 includes developer access device 7a Which
`is a graphical user interface (“GUI”) or other softWare
`running on PC 7 for displaying menus, buttons, text boxes
`etc. (not shoWn) on display 7b corresponding system state
`registers 11a, trace register 50, USB logic registers 12a, and
`I/O registers 13a and for commanding PC 7 to transfer
`appropriate commands over the RS-232 bus 14 to PC
`interface 5a of controller 5. Thus, the user, after selecting the
`appropriate menu, button, or ?lling in the appropriate text
`box With mouse 7c and keyboard 7d, can read or Write the
`corresponding system state registers 11a, trace register 50,
`USB logic registers 12a, and I/O registers 13a via PC 7,
`RS-232 bus 14 and PC interface 5a to control the USB
`microcontroller 8.
`On command from developer access device 7a, as previ
`ously described, PC 7 sends a series of three 8-bit data bytes
`as serial data to PC interface Sa of controller 5 in a command
`structure over RS—232 bus 14. The PC interface 5a includes
`a UART function for providing the RS-232 function. The
`?rst byte sent by PC 7 is either an I/O (system state registers
`11a, USB logic registers 12a, I/O logic registers 13a, or
`trace register 50) or data RAM 4 address; the second byte is
`a command; and the third byte is a data value that together
`With the address byte and the command byte identi?es and
`supports data read and Write operations to either an I/O or
`data RAM 4 address location. The U0 and data RAM 4
`command structure is outlined in Table A.
`
`TABLE A
`
`Command Structure
`
`Command
`Byte
`(hex)
`
`Data
`Byte
`x = don’t
`care
`
`O0
`
`02
`01
`
`03
`
`DATA
`
`DATA
`XX
`
`XX
`
`Function
`
`Write the Data Byte to
`the location identi?ed by
`the Address Byte.
`Read the data byte at the
`location identi?ed by the
`address byte an transmit
`the byte read to PC 7.
`
`Command
`Name
`
`WRITE DATA
`BYTE
`
`READ DATA
`BYTE
`
`Address Byte
`
`Data RAM 4
`Address
`*I/O Address
`Data RAM 4
`Address
`*I/O Address
`
`*I/O includes system state registers 11a, USB logic registers 12a, I/O logic registers 13a, and
`trace register 50.
`
`MR (memory read): tells the USB logic 12, U0 logic 13,
`and controller 5 that the microprocessor 9 Wishes to
`read data from data RAM 4; and
`
`65
`
`From the Controller 5:
`
`Trace register 50 of system bus logic 15 has tWo status bits
`(see FIG. 2) that can be read or Written to by using the
`previously mentioned command structure, control of the
`USB microcontroller development system 100 can be facili
`tated by either PC 7 or microprocessor 9 Which have access
`
`BLACKBERRY Ex. 1015, page 7
`
`

`

`US 6,338,109 B1
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`10
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`15
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`25
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`35
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`7
`to data RAM 4, system state registers 11a, and trace register
`50 via the command structure of Table A.
`FIG. 2. is a bit-diagram of a trace register 50 provided in
`system bus logic 15 to implement the above function. The
`contents of the trace register 50 can be modi?ed by the
`microprocessor 9 or the PC 7 via the command structure of
`Table A. RUN 51 (bit 0) of trace register 50, if set (bit 0=1),
`causes the microprocessor 9 to execute instructions from
`instruction RAM 2, and if reset or cleared (bit 0=0), causes
`the microprocessor 9 to stop executing instructions from
`instruction RAM 2. SINGLE STEP 52 (bit 1) of trace
`register 50, along With the RUN 51 control hoW many
`instructions from instruction RAM 2 microprocessor 9
`executes.
`FIG. 3. is a logic ?oW diagram shoWing the RUN/
`SINGLE STEP operations outlined above.
`At step 100 the microprocessor 9 is stopped (RUN 51=0).
`As long as RUN 51 is set to Zero, by either the micropro
`cessor 9 or the controller 5, the microprocessor Will not
`execute instructions in instruction RAM 2. HoWever, if RUN
`51 is set to one, by the controller 5, the logic How goes to
`step 200.
`At step 200 one instruction is executed by microprocessor
`9 from instruction RAM 2 and the logic ?oWs to step 300.
`At step 300 the contents of the SINGLE STEP 52 is
`checked. If SINGLE STEP 52 is set to Zero (SINGLE STEP
`52=0), by either the microprocessor 9 or the controller 5,
`single step mode is not being selected and the logic ?oWs
`back to step 100 Where steps 100—300 are executed until
`either the microprocessor 9 or the controller 5 sets RUN 51
`to Zero causing the microprocessor 9 to stop executing
`instructions from instruction RAM 2. If SINGLE STEP 52
`is set to one (SINGLE STEP 52=1), by either the micropro
`cessor 9 or the controller 5, single step mode is being
`selected and the logic ?oWs to step 400.
`At step 400 RUN 51 is set to Zero, the logic ?oWs to step
`100, and the microprocessor 9 is stopped at step 100 since
`RUN 51 Was set to Zero at step 400.
`In this Way, during single step mode only one instruction
`is executed at steps 100—400, the microprocessor 9 is
`stopped at step 100 since RUN 51 is set to Zero at step 400,
`and the PC 7 must issue an I/O Write command to set RUN
`51 to one at step 100 in order for microprocessor 9 to execute
`the next instruction from instruction RAM 2. If single step
`mode is not set, then microprocessor 9 continuously
`executes instructions from instruction RAM 2 until either
`the microprocessor 9 itself or the PC 7 issues a Write data
`byte command to clear RUN 51 to Zero. At any time the PC
`7 can modify/read the USB microcontroller system state, as
`described previously, to assist in debugging ?rmWare stored
`in instruction RAM 2.
`In addition, since PC 7 can Write the system state registers
`11a of microprocessor 9, as described previously, Which
`include the program counter (not shoWn) Which is the
`address of the instruction RAM 2, an instruction register (not
`shoWn) Which holds the data corresponding to the program
`counter, PC 7 can be used to load ?rmWare into instruction
`RAM 2 for execution by microprocessor 9.
`The program counter holds the address of instruction
`RAM 2 and instruction register holds the data corresponding
`to the program counter. Thus, by PC 7 Writing to the
`program counter and the instruction register and the
`sequencer logic 34 issuing a Write command to instruction
`RAM 2, the entire contents of instruction RAM 2 may be
`Written to by PC 7. Similarly, by Writing an address to the
`program counter and the sequencer logic 34 issuing a read
`command to instruction RAM 2, the entire contents of
`instruction RAM 2 may be read.
`
`45
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`55
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`65
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`8
`The interface to a USB host computer and USB device
`under development Will noW be described.
`A USB host computer 16 is connected to USB interface
`12b of USB logic 12 via USB 17. USB interface 12b
`complies With the USB standard. The USB logic 12 decodes
`addresses on the system bus 10, alloWing microprocessor 9
`or controller 5 to read or Write contents of the USB logic
`registers 12a via the command structure, as previously
`described.
`Sensors, potentiometer, motors, LEDs, memories, data
`collecting or other input output devices of an I/O device 18
`are connected to I/O interface 13b via I/O ports 19. The U0
`logic 13 decodes addresses on the system bus 10, alloWing
`microprocessor 9 or controller 5 to read or Write contents of
`the I/O logic registers 13a via the command structure, as
`previously described.
`As an example, the USB microcontroller development
`system 100 could be used to debug ?rmWare for a USB
`mouse or joystick, etc. In this case, the mouse or joystick
`sensors, potentiometer, etc. Would be attached to I/O inter
`face 13b via I/O ports 19, and the USB host computer 16
`Would be attached to USB interface 12b via USB 17. The
`?rmWare could be loaded from PC 7 to instruction RAM 2
`by Writing to the system state registers 11a and then
`debugged using the trace register 50 function and the ability
`to read/modify the microcontroller system state, as previ
`ously described. In this Way, the USB mouse or joystick
`function etc. could implemented to run on USB host com
`puter 16 via the USB microcontroller development system
`100.
`The present invention may be implemented via a Hard
`Ware Description Language, as previously described.
`As an example, the Writing operation of the system state
`registers 11a can be implemented in HDL With statements
`such as:
`
`always @ (posedge REGW)
`begin
`case (LA)
`'rA:
`'rTl:
`'rTZ:
`'rDSP:
`'rPSP:
`'rPCL:
`endcase
`
`a = DI;
`t1 = DI;
`t2 = DI;
`dsp = DI;
`psp = DI;
`pcl = DI;
`
`end
`
`and mapping of the system state registers 11a can be
`implemented in HDL With statements such as:
`
`always @ (LA or a or t1 or t2 or ID or IR or dsp or psp or
`pcl or pch)
`begin
`#5;
`case (LA)
`‘rA:
`'rT1:
`'rTZ:
`'rDSP:
`'rPSP:
`'rPCL:
`'rPCH:
`'rID:
`endcase
`
`LD = a;
`LD = t1;
`LD = t2;
`LD = dsp;
`LD = psp;
`LD = pcl;
`LD = pch;
`LD = ID;
`
`end
`
`BLACKBERRY Ex. 1015, page 8
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`US 6,338,109 B1
`
`9
`and HDL statements such as:
`
`assign #1 regSelect = (DA[7:3] == 5'b1110);
`assign #1 idSelect = (DA[7:3] == 5'b1111);
`
`implement the address decode for the system state registers
`11a and data RAM 4.
`In the present invention, HDL implemented processes are
`used in designing various components of the USB micro
`controller 8 to achieve the various objects of the invention.
`The various components of the USB microcontroller 8,
`When appropriately programmed in HDL, are mapped to
`FPGAs and packaged onto a single printed circuit board
`along With minimal additional logic such as EEPROMs and
`RAM.
`Although in the preferred embodiment the USB micro
`controller 8 includes several FPGAs, RAM and EEPROMs
`packaged onto a circuit board, this invention may be imple
`mented using a conventional general purpose digital com
`puter or microprocessor programmed according to the teach
`ings of the present speci?cation, as Will be apparent to those
`skilled in the computer art. Appropriate softWare coding can
`readily be prepared by skilled programmers based on the
`teachings of the present disclosure, as Will be apparent to
`those skilled in the softWare art. The invention may also be
`implemented by the preparation of application speci?c inte
`grated circuits or by interconnecting an appropriate netWork
`of conventional component circuits, as Will be readily appar
`ent to those skilled in the art.
`Although the preferred embodiment of the USB micro
`controller development system 100 is described in terms of
`a USB development system, the present invention could be
`adapted for other device standards such as NeWbus, PCI,
`VESA, etc. by simply modifying the USB logic 12 and I/O
`logic 13 functional blocks, as Will be apparent to those
`skilled in the art.
`Although the preferred embodiment of the USB micro
`controller development system 100 is described in terms of
`providing a PC interface via an RS-232 bus, the present
`invention could be adapted to interface to various types of
`personal computers, Workstations, etc. by simply modifying
`controller 5 functional block to include t