TECHNOLOGY
`
`Convert all your synchro channels
`to digital with a single ~P-based system. For low speeds~
`you get an accurate, inexpensive, efficient and small unit.
`
`Using a micrQprQceSSQr, yQU can cQnvert eight
`synchrQ Qr resQlver channels to. digital angles
`with fQur-are-minutes accuracy in a package
`rQughly the same size as a single-chami"el cQnverter
`system-with Qnly a bit mOore PQwer cQnsumptiQn
`and at nearly the samecQst. FQr example, in a
`cQmplete mQdular system, the MN7200 frQm
`Micro. N etwQrks, a microprocessQr controls se­
`quencing and perfQrms data cQnversiQns. The re­
`sult is a cQnverter capable Qf handling UP .to. eight
`synchrQ Qr resQlver inputs, whQse accuracy is
`guaranteed Qve'r the full operating temperature
`range Qf 0 to. 70 C.
`There is Qne drawback, hQwever. The ,/LP-based
`instrument is limited to. maximum transducer
`speeds of 10 deg/ s.
`
`Synchro/ resolver converter basics
`The cQnventiQnal cQnverter system (Fig. 1) re­
`quires six distinct steps to' CQnvert either a syn­
`chro Qr resQlver signal intO' digital angles :
`• CQnverting the three-phase synchrQ signal
`into. a two-phase resQlver signal with either a
`Scott-T transformer O'r O'P amps. One phase Qf the
`resQlver 'signal is proPO'rtiQnal to. the angle's sine,
`and the Qther phase to the angle's cQsine.
`• DemO'dulating bOoth these signals with re­
`spect to' the synchrO"s ac reference signal with an
`ac/ dc · cO'nverte,r, to' get dc levels p'roPOortiQnal to.
`the sine and cQsine Qf the input angle.
`• Detecting, frQm the dc signal, the quadrant
`Qr octant in which the input angle lies, and digi­
`tizing the angle. Table 1 shO'WS the bit weights
`fOor a binary sequence Oof angles.
`• Feeding the binary-angle infO'rmatiQn to an
`up~dQwn counter.
`• Multiplying the cOounter's output by the dc
`signals with two. multiplying d/ a converters­
`one fQr the sine signal and Qne fQr the cosine
`sig nal-to, get two res ults: sin () COos cp, and cos
`() sincp, where () is the angle in the counter and
`cp the input angle.
`
`Binary weights of angles in the coding
`method employed in the MN7200
`'Radians
`Bit number Degrees Degrees minutes
`180
`3.141593
`1
`180
`0
`90
`1.570796
`2
`90
`0
`45
`45
`0.785398
`0
`3
`4
`22.5
`22 30
`0.392699
`0.196349
`11 15
`5
`11.25
`5 37.5
`6
`5.625
`0.098L75
`2 48.75 0.049087
`7
`2.812.5
`1.40625
`'1 24.38 0.024544
`8
`o 42,.19 0.012272
`9
`0.70312
`10
`0.35156
`0 21.09 0.006136
`0,17578
`0 10.55 0.003068
`11
`0 .08789
`5.27 0.001534
`12
`0
`2.64 0.000767
`13
`0.04395
`0
`0.02197
`14
`0
`1.32 0.000383
`0, 0.66 0.000192
`15
`0.01099
`0.00549
`16
`0
`0.33 0.'000096
`
`v
`
`(
`
`R
`
`~~ MSB
`' 1/2 ..fiR
`R r::""l
`FROM SYNCHRO OUTPUTS 0
`
`
`,'-----:l~r----=---:.....!..I
`TO AC/DC
`~ CONVERTERS
`
`Arthur Berg, Project Engineer, Micro Networks, Worces­
`ter, MA 01606.
`
`1. Conventional multichannel converters (a) use many
`linear components. You can repla'ce the Scott-T trans­
`former with an electronic Scott·T converter (b).
`
`78
`
`ELECTRONIC DESIGN 25, December 6, 1976
`
`1
`
`Micro Motion 1044
`
`

`

`• Subtracting, in an op amp, to get the dif­
`ference between the two converter outputs, and
`adjusting the frequency of a gated voltage-con­
`trolled oscillator (VCO) with the result. The
`VCO's output pulses the up-down counter to the
`correct digital angle-the digital equivalent of
`nulling in an analog system. When the counter
`contains the exact input angle, the subtraction
`result is zero, and the process is complete.
`The disadvantages inherent in this six-step
`process are obvious. Too much circuitry is re-
`
`SYNCHROS
`
`REFER­
`
`ENCE
`
`TRANS­
`FORMER
`
`I
`
`OUTPUT
`
`DIGITAL
`
`ANGLE
`
`2. The popular tracking converters are accurate but
`limited to converting only a few channels. Successive­
`approximation sampling converters are useful for con­
`verting several channels in a multiplexed system, but
`have serious accuracy problems.
`.
`
`quired, principally for quadrant or octant selec­
`tion and angle determination, and analog signals
`are carried toO' far-right up to the final counter.
`
`No,w there are three
`
`The new p,P technique competes with two other
`methods for cO'nverting synchro and resolver sig­
`nals to digital angle data that, hitherto, have
`been used. These older types are the tracking ·con­
`.verter and the successive-approximation sam­
`pling converter.
`The tracking converter (Fig. 2) is noted for
`its high accuracy even with noisy signals. Noise
`"cancels out because of ratio rather than ampli­
`tude detection. But, even though . some recently
`available si d and r i d tracking converters have
`improved operating speeds, most tracking cO'n­
`verters can't track a synchro or resolver rotating
`at more than four rev/ s, On the other hand, the
`successive-apprO'ximation sampling converter, al­
`though a higher-speed circuit than the tracking
`converter, becomes
`inaccurate with noise or
`distortion.
`Tracking converters are used primarily when a
`limited number of channels is to be converted ac-
`
`curately, and sampling converters when six or
`more multiplexed channels are to be converted at
`high speed.
`The third method for si d conversion, the micro­
`processor-based system, as . used in the MN7200
`is intended for multichannel applications. Accu­
`racy (even in the presence ' of noise), low CO'st,
`small size and low power consumption make the
`,uP-based system attra.ctive for ' many applica­
`tions, in spite of its low speed.
`. The new circuit (Fig. 3) is made up of eight
`dual acl dc converters, a 16-channel data-acquisi­
`tion system, and a microprocessor.
`The microprocessor, a Fairchild Semiconduc­
`tor F8, is a two~ehip unit that consists of the
`CPU, and the Program Storage Unit (PSU). Be­
`sides being/LP-based, the MN7200 circuitry differs
`from conventional sid and ri d circuits because it
`has a minimum number of custom-linear circuits
`and, thus, is cheaper. Octant selection (0 to 45
`degrees) is performed digitally with the micro­
`processor. And the hybrid circuits used, such as
`the acl dc demodulators, multiplexers, and ai d
`converters are all standard products.
`The system converts eight re,solver (or with
`the addition of Scott-T transformers, synchro)
`channels into 14-bit digital form.
`
`Multiplexing the inputs
`
`While conventional multichannel converters
`typically require an a/ d for each channel, only a
`single ai d is used in this circuit: It accepts up to
`eight pairs of sequential inputs from the multi­
`plexer.
`Synchro outputs from the Scott-T transformers
`or resolver outputs V" ac and Vy ac are converted
`to de voltages Vx and Vy by two ac/ dc demodula­
`tors-one ' each for sine and cosine (Fig. 3). A
`multiplexer connects these de signals sequentially
`-one per conversion period (approximately 2 ms)
`-to the ai d converter that converts them into
`the binary signals X and Y. After conversion, the
`binary X and Y signals are stored in RAM. The
`microprocessor
`then executes
`the conversion
`equation,
`
`Y
`()= tan-! - ,
`X
`and the result is placed on the output-data lines
`and stored in RAM. Up to 8 channels are thus
`converted and stored in 16 RAM locations. A con­
`version cycle takes 2 ms.
`A fetch cycle takes 50 i/LS from the time the
`data-output line is triggered. The system has two
`externally controlled channel-selection modes. In
`the sequential mode, a counter is incremented
`after each channel is converted. In the random
`mode, each channel may be selected by the chan­
`nel~select inputs. and triggered by the load line.
`The circuit differs from conventional s/ d and
`
`ELECTRONIC DESIGN 25, December 6, 1976
`
`79
`
`2
`
`

`

`INTERRUPT
`RESET
`
`ENABLE
`STROBE
`
`AID.
`CONVERTER
`
`8 BITS
`
`BUFFER
`A .
`
`3 BITS
`
`3 BITS
`
`0
`0
`
`I­
`::>
`ll.
`!!:
`
`CPU
`
`, - - - - - , B BITS
`
`ROM ·
`
`BBITS
`
`INTERFACE
`
`BIT 3
`
`BITB
`
`3 BITS
`
`ENABLE
`
`ENABLE
`
`BUFFER
`
`C
`
`BIT B
`
`CHANNEL ADDRESS BUS
`
`CHANNEL
`
`SELECT
`
`BUS
`
`
`LOAD
`
`CLEAR
`
`3. The MN7200 resolver-to-digital converter circuit dif­
`fers from conventional ones in that it allows for low-cost
`
`multichannel (eight. in this case) conversions in a com­
`pact. low-power-dissipating configuration.
`
`r / d converters in that all its data are converted to
`digital form at the input ai d converters, whereas
`much of the information in conventional designs
`remains subject to error in analog form, right up
`to the final digital counter.
`
`Canceling nonlinearities
`
`The 12-bit a i d converter in the circuit (Fig. 3)
`performs both sine-proportional and cosine-pro­
`portional signal conversions, so errors caused by
`using separate a/ d's are eliminated. By ratioing,
`the microprocessor eliminates the potential error
`source due to amplitude changes of the sine or
`cosine-input signals.
`Two data I/O ports connect the 12-bit aid con­
`verter's output and the microprocessor's CPU.
`Two 8-bit ports deliver 12 bits to the CPU in 2
`bytes. One port inputs eight bits,the other only
`four.
`With buffer A on and buffers Band C off, aid
`data goes to the CPU. With buffers A & C off and
`B on, the address of the channel being converted
`is sent to the CPU. When operating in the inter­
`ruptor data-fetch modes with C on and A and B
`off, an external address can be sent to the CPU
`to address the memory for data.
`In addition to the data bus that links the: PSU
`and the CPU, two other 8-bit I/ O ports are used
`as a single 14-bit output port, with all eight bits
`activ.e in one and only six active in the other.
`
`This arrangement allows simple interfacing with
`either 16-bit minicomputers or 8-bit microcom­
`puters.
`After the synchro or resolver angle is com­
`puted, the microprocessor system stores the re­
`sulting14-bit word in the registers of the PSU's
`two I / O ports, until the word is replaced by a
`new result.
`The 4-bit programmable counter, which ad­
`dresses the input multiplexers sequentially, is
`connected to the channel-select bus to receive
`direct-set inputs from an external channel-selec­
`tor circuit. The 3-bit, channel-address bus links
`the input multiplexers
`to
`the programmable
`counter and the CPU via buffer B.
`
`It all · starts with reset input
`
`Operation begins when a reset input initializes
`the CPU. The system is clocked by bit 7 of the
`CPU's I/O port, which drives the start input of
`the a/ d. The ai d then outputs EOC (end of
`clock), which drives the programmable address
`counter. Bit 8 enables the input multiplexers to
`pass the channel addressed by the programmable
`counter. In all, 6 bits are used for data entry to
`the CPU.
`The multiplexer's sine inputs are enabled by
`bit 8. Its complement, bit 8, enables the cosine in­
`puts so only one set of inputs, either sine or
`cosine, is active at a given time.
`
`80
`
`ELECTRONIC DESIGN 25, December 6, 1976
`
`3
`
`

`

`1'1 I '2 I 13 I 14
`r-----------'~--~--~--~~--_.-------~-"--~--~----~-.--~--~I------'-­
`110+11
`Im+1
`15
`t6
`In
`1m
`CPURESET -W
`
`CHANNEL {MSB ---,
`OUTPUT CODE
`(CHANNEL
`ADDRESS
`BUS)
`
`-,1..__ _ ___ _....:...__-::-_-;::===========:;-....:.....____
`
`- "
`1..._ ___ __ ____ _---'
`
`2
`3
`
`CHANNEL
`
`SELECTION {
`BUS
`
`
`SB
`
`
`2
`
`
`3
`
`INTERRUPT
`
`LOAD
`
`I6-BIT OUTPUT {
`(ROM OUTPUT
`REGISTER PORT)
`
`"" "'""{:
`
`LJ
`-----------------------------------------------,~r-----­
`~ DATA
`------------------~~
`LJi'--__
`~__________~r____
`
`~-­
`~ DATA
`~ CHANGE
`
`u
`
`"END OF CONVERSION"OUTPUT
`
`ENABLE
`
`_____________________~r_l~_____
`
`4. The converter's six timing states ' are repeated as it
`cycles through each of eight channels. For fewer than
`
`eight channels, the last active channel is followed by
`channel 0 and the sequence repeats.
`
`The CPU's enable-output line indicates that an
`interrupt signal has ' been received or data are
`changing. NOormally, this line (loow) disables buf­
`fers Band C. Buffer Ais enabled after the aid
`conversion is finished (EOC high). (An enabled
`buffer A permits data transfer from the ai d con­
`verter to the mIcrOprOoCessO'r's CPU.) .
`After an interrupt signal, the enable goes high,
`which activates buffers Band C and disablesbuf­
`fer A. The interrupt stops the normal O'peration
`of the micrO'prO'cessO'r and requests that stored
`data from .the addressed channel be transferred
`tOo the output lines.
`The reset line to' the CPU resets the program
`counter in the PSu. The load line allows the pro­
`grammable counter ' to' be set to the channel
`chosen by the Channel-select data bus. The clear
`line resets the programmable counter.
`
`Look at the timing diagram
`
`Operation starts at tl with a pulse on the
`. CPU's reset line (and the programmable count­
`er's clear line). This pulse clears both the pro­
`gram counter in the ROM and the prO'grammable
`cO'unter to' ZERO (see Fig. 4). The ROM's pro­
`gram counter is started by CPU clock signals.
`The channel-select line is still inactive, ' and all
`three bits on the channel-address bus are ZEROs.
`.The sine input of channel 0 then passes from
`its dedicated demO'dulator
`through the input
`multiplexer intO' the aid converter.
`At t 2 , the ai d converter's start line and the
`programmable counter's clock line are pulsed,
`which starts conversion in the aid converter and
`
`blocks buffer stage A. During t z, the EOe line
`clocks the programmable counter, but dOoes not
`change the address tOo the multiplexers. This line
`changes .Oonly the LSB, which is. not O'n the chan­
`nel-address bus.
`.
`When the cO'unter first accesses a channel, the
`address LSB is always ZERO. The multiplexer,
`therefore, alwa.ys samples ' the selected channel's
`sine input first. The LSB is then tO'ggled to' a
`ONE,and the cO'sine input sampled. The LSB is
`then retO'ggled tOo ZERO. This time the 3-bit ad­
`dress is incremented, which accesses the next
`channel, starting with its sine input.
`AlsOo during t 2 , the PSU's internal timer is set
`for a time interval slightly longer than the cO'n­
`version time needed by thel al d. This timer stops
`the prOogram cO'unter in the CPU and restarts it
`at the end O'f the preset time interval. Meanwhile,
`the a/ dcO'nverter cO'mpletes its conversiO'n cycle,
`and the EOC enables buffer A.
`The ai d cO'nverter's 12 bits are routed in two
`parts--,eight bits throughdata-PO'rt 1,and four
`bits thrOough data-port 2. The first bit (MSB) in­
`dicates signal polarity. The remaining three bits
`are amplitude data and ' are stored in RAM by a
`prO'gram in ROM.
`At t 3 , bit 8 changes state, which bO'th disables
`the sine mUltiplexer and enablesth~cosine multi­
`plexer.
`At t" conversion starts in the aid and the EOC
`output blO'cks ·bufferstage A. The multiplexer COon­
`nects the de analog Oof the cO'sine input to the ai d
`converter, and an all-ZERO address is again con­
`nected to the multiplexer. The ROM's internal
`timer starts again, and the ai d converts the
`
`ELECTRONIC DESIGN 25, December 6, 1976
`
`81
`
`4
`
`

`

`cosine analog of input-channel 0 to digital form.
`At the conversion's end, EOC reverses the state
`of the buffers so that the cosine isai the CPU's
`I / O ports. At the end of the timer's interval, the
`program is restarted, and the cosine goes into
`RAM. Therefore, after i" values for both the sine
`and cosine. ofa channel's input angle are in the
`RAM.
`
`A branch point can occur
`
`Next, theJLP computes the angle (answer)
`from its sine and cosine values. The MSBs of the
`sine and the answer are the same. For a ' ZERO
`MSB, the ariswer is between 0 and .180 degrees,
`and here the program has a branch point. If the
`sine's MSB is ZERO (sine positive), the cosine's
`MSB becomes the answer's next bit. For the sine's
`MSB, a ONE (sine negative), the complement
`of the cosine's l\iSBis the second MSB in the
`answer.
`The answer's third MSB is determined by sub­
`trading the sine's 11 amplitude bits from the
`cosine's. A positive result makes the third MSB
`a ONE, a negative result ZERO.
`Now the "LPcan divide the larger ll-bit num­
`ber into the smaller to get the angle's tangent.
`The ROM contains a tangent-to-angle table. To
`minimize the size of this table, only 64 values
`and the slopes to the next value are provided for
`the tangent function. Therefore, only the tan­
`gent's six MSBs are used to address the table; the
`remaining five bits are multiplied by the slope.
`The final answer is the sum of two values; the
`first an ll-bit word that the tangent's six MSBs
`fetch from ROM: The second summed value is the
`product of the five remaining bits multiplied by
`a slope value that is also accessed by the six
`MSBs.
`The enable line is held high to indicatechang­
`ing output data. Buffers Band C are enabled,
`buffer A is disabled. The channel address,along
`with the program's instructions, select a pair of
`RAM addresses in which to store the 14-bit
`answer. The 14-bit answer also remains at the
`ROM's output register port.
`At tn, the programmable counter is clocked,
`which changes the second LSB of the three-bit
`addre3s. The multiplexers pass to the next chan­
`nel. The a / d converter starts, which · begins the
`sequence
`for
`the next
`input · channel. This
`process continues until the digital angles ' for all
`inputs are in storage, when the CPU's main pro-.
`gram counter and the programmable counter are
`zeroed and started over again. Words stored in
`RAM are replaced by updated words as new in­
`formation is processed and received.
`The digital-angle data are in binary-angle form
`rather than in degrees. The MSB indicates which
`half-circle the angle is in, the next MSB indicates
`
`5. The entire ,/LP-based . rId converter consists of 32
`DIPs on a 6 x 8-in. board.
`
`which quarter, the next MSB indicates which oc­
`tant, and so on. Code conversion, say, to binary
`or degrees is easily added here.
`At til
`(Fig. 4), an interrupt signal inhibits
`buffer A, enables buffers Band C, and stops the
`ROM's program counter. The three bits that are
`now manually entered onto the ' channel-select bus
`address the RAM through buffer C and port 2.
`This 3-bit code addresses one of eight 14-bit
`angles in the RAM. The addressed angle appears
`at the ROM's output-register port. At the end
`of the interrupt, the main program counter picks
`up again, and the program continues from where
`-it was interrupted.
`At tm' a load signal jams the address on the
`channel-select bus into the programmable count­
`er. The CPU's reset line then resets the CPU and
`clears the main program counter to ZERO. The
`program then picks up by using the channel se­
`lected on the channel-selecti bus as the first chan­
`nel, and proceeds in sequence thereafter.
`Interrupt, therefore, provides the latest stored
`data fora selected channel, while load and reset
`cause new data to be processed starting with the
`selected channel.
`The Scott-T transformers and ac/ dc demodu­
`lators in the input circuit are conventional com­
`ponents. So are the IC multiplexers. The 12-bit
`a/ d converter needs only a parallel output, some­
`thing available in a variety of commercial com­
`ponents. Three-state buffers A, B, and Care
`merely used as on-off switches in the data paths
`to permit time-sharing of the CPU I/O ports.
`While the programmable counter is shown in Fig.
`3 as a 4-bit unit,a 3-bit unit is adequate. The
`fourth bit is used to divide by 2, thereby main- .
`taining the same ch~nnel address as the sine and
`cosine input multiplexers are successively en­
`abled.
`In the two-chip F8 microprocessor, one chip
`houses the CPU (including the control logic f()r
`RAM and ALU) and dock-generating circuitry,
`and the other chip, the PSU, houses the ROM.
`For a description of the F8 ,/LP see "Microproces­
`sor Basics, Part 3" (ED, No. 12, June 7, 1976,
`p. 126). A look-up table, for converting the tan­
`gent function to angular data, is burned into the
`microprocessor's nonvolatile ROM . ••
`
`82
`
`FOR .BURNDYCORP. INSERT, CIRCLE 246.
`
`5
`
`