Chapter 10 General Programmable Interface (GPIF)
`
`10.1 Introduction
`
`The General Programmable Interface (GPIF) is an internal master to the FX2’s endpoint FIFOs. It
`replaces the external “glue” logic which might otherwise be required to build an interface between
`the FX2 and the outside world.
`
`At the GPIF’s core is a programmable state machine which generates up to six “control” and nine
`“address” outputs, and accepts six external and two internal “ready” inputs. Four user-defined
`Waveform Descriptors control the state machine; generally (but not necessarily), one is written for
`FIFO reads, one for FIFO writes, one for single-byte/word reads, and one for single-byte/word
`writes.
`
`“Read” and “Write” are from the FX2’s point of view. “Read” waveforms transfer data from the
`outside world to the FX2; “Write” waveforms transfer data from the FX2 to the outside world.
`
`FX2 firmware can assign the FIFO-read and -write waveforms to any of the four FIFOs, and the
`GPIF will generate the proper strobes and handshake signals to the outside-world interface as data
`is transferred into or out of that FIFO.
`
`As with external mastering (see Chapter 9 "Slave FIFOs"), the data bus between the FIFOs and
`the outside world can be either 8 or 16 bits wide.
`
`The GPIF is not limited to simple handshaking interfaces between the FX2 and external ASICs or
`microprocessors; it’s powerful enough to directly implement such protocols as ATAPI (PIO and
`UDMA), IEEE 1284 (EPP Parallel Port), Utopia, etc. An FX2 can, for instance, function as a single-
`chip interface between USB and an IDE hard disk drive or CompactFlash™ memory card.
`
`This chapter provides an overview of GPIF, discusses external connections, and explains the oper-
`ation of the GPIF engine. Figure 10-1 presents a block diagram illustrating GPIF’s place in the FX2
`system.
`
`GPIF waveforms are generally created with the Cypress GPIFTool utility, a Windows™-based
`application which is distributed with the Cypress EZ-USB FX2 Development Kit. Although this
`
`Chapter 10. General Programmable Interface (GPIF)
`
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`chapter will describe the structure of the Waveform Descriptors in some detail, knowledge of that
`structure is usually not necessary. The GPIFTool simply hides the complexity of the Waveform
`Descriptors; it doesn’t compromise the programmer’s control over the GPIF in any way.
`
`8051
`
`XDATA
`
`G PIF
`
`Device Pins
`
`XG PIFSG LDATH/L
`
`EP2FIFO BUF
`EP4FIFO BUF
`EP6FIFO BUF
`EP8FIFO BUF
`
`Slave FIFO s
`W O RDW IDE=1
`
`EP2
`EP4
`EP6
`EP8
`
`CLK
`
`EPxEF
`EPxFF
`EPxPF
`
`SLO E
`SLRD
`SLW R
`
`INPKTEND
`
`FIFO ADR[1:0]
`
`FD[15:0]
`
`30/48MHz
`
`IFCLK
`
`5 - 48MHz
`
`G PIFADR[8:0]
`
`CTL[5:0]
`
`RDY[5:0]
`
`8051
`
`W aveform Descriptors
`
`W F0
`W F1
`W F2
`W F3
`
`G PIF
`
`G STATE[2:0]
`
`XG PIFSG LDATLX
`
`G PIFTRIG
`
`8051 INTRDY
`
`G PIF DO NE
`
`G PIFW F
`
`PO RT I/O
`
`Figure 10-1. GPIF’s Place in the FX2 System
`
`Figure 10-2 shows an example of a simple GPIF transaction. For this transaction, the GPIF gener-
`ates an address (GPIFADR[8:0]), drives the FIFO data bus (FD[15:0]), then waits for an exter-
`nally-supplied handshake signal (RDY0) to go low, after which it pulls its CTL0 output low. When
`the RDY0 signal returns high, the GPIF brings its CTL0 output high, then floats the data bus.
`
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`
`S0
`
`S1
`
`S2
`
`S3
`
`S4
`
`S5
`
`S6
`
`GADR[8:0]
`
`A
`
`A+1
`
`FD[15:0]
`
`Z
`
`VALID
`
`Z
`
`CTL0
`
`RDY0
`
`Figure 10-2. Example GPIF Waveform
`
`10.1.1 Typical GPIF Interface
`
`The GPIF allows the EZ-USB FX2 to connect directly to external peripherals such as ASICs,
`DSPs, or other digital logic that uses an 8- or 16-bit parallel interface.
`
`The GPIF provides external pins that can operate as outputs (CTL[5:0]), inputs (RDY[5:0]), Data
`bus (FD[15:0]), and Address Lines (GPIFADR[8:0]).
`
`A Waveform Descriptor in internal RAM describes the behavior of each of the GPIF signals. The
`Waveform Descriptor is loaded into the GPIF registers by the FX2 firmware during initialization,
`and it is then used throughout the execution of the code to perform transactions over the GPIF
`interface.
`
`Figure 10-3 shows a block diagram of a typical interface between the EZ-USB FX2 and a periph-
`eral function.
`
`Chapter 10. General Programmable Interface (GPIF)
`
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`G P IF A D R [8 :0 ]
`
`IF C L K
`
`F D [1 5 :0 ]
`
`C T L [5 :0 ]
`
`R D Y [5 :0 ]
`
`P O R T I/O
`
`F X 2
`M a s te r
`M o d e
`
`P e rip h e ra l
`
`G S T A T E [2 :0 ]
`
`D e b u g
`
`Figure 10-3. EZ-USB FX2 Interfacing to a Peripheral
`
`The following sections detail the features available and steps needed to create an efficient GPIF
`design. This includes definition of the external GPIF connections and the internal register settings,
`along with FX2 firmware needed to execute data transactions over the interface.
`
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`10.2 Hardware
`
`Table 10-1 lists the registers associated with the GPIF hardware; a detailed description of each
`register may be found in Chapter 15, "Registers."
`
`Table 10-1. Registers Associated with GPIF Hardware
`
`GPIFIDLECS
`GPIFIDLECTL
`GPIFCTLCFG
`PORTCCFG
`PORTECFG
`GPIFADRH/L
`GPIFTCB3:0
`GPIFWFSELECT
`EPxGPIFFLGSEL
`EPxGPIFPFSTOP
`GPIFREADYCFG
`GPIFREADYSTAT
`
`IFCONFIG
`FIFORESET
`EPxCFG
`EPxFIFOCFG
`EPxAUTOINLENH/L
`EPxFIFOPFH/L
`
`EPxTRIG
`GPIFABORT
`XGPIFSGLDATH/LX/LNOX
`GPIFSGLDATH/LX/NOX
`GPIFTRIG
`
`Note: The “x” in these register names represents 2, 4, 6, or 8; endpoints 0 and 1
`are not associated with the GPIF.
`
`10.2.1 The External GPIF Interface
`
`The GPIF provides many general input and output signals with which external peripherals may be
`interfaced gluelessly to the FX2.
`
`The GPIF interface signals are shown in Table 10-2.
`
`Table 10-2. GPIF Pin Descriptions
`
`PIN
`CTL[5:0]
`RDY[5:0]
`FD[15:0]
`GPIFADR[8:0]
`IFCLK
`GSTATE[2:0]
`
`IN/OUT
`O / Hi-Z
`I
`I / O / Hi-Z
`O / Hi-Z
`I / O
`O / Hi-Z
`
`Description
`Programmable control outputs
`Sampleable ready inputs
`Bidirectional FIFO data bus
`Address outputs
`Interface clock
`Current GPIF State number (for debug)
`
`The Control Output pins (CTL[5:0]) are usually used as strobes (enable lines), read/write lines, etc.
`
`Chapter 10. General Programmable Interface (GPIF)
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`The Ready Input pins (RDY[5:0]) are sampled by the GPIF and can force a transaction to wait
`(inserting wait states), continue, or repeat until they’re in a particular state.
`
`The GPIF Data Bus is a collection of the FD[15:0] pins.
`
`An 8-bit wide GPIF interface uses pins FD[7:0].
`
`A 16 bit-wide GPIF interface uses pins FD[15:0].
`
`The GPIF Address lines (GPIFADR[8:0]) can generate an incrementing address as data is trans-
`ferred. If higher-order address lines are needed, other non-GPIF I/O signals (i.e., general-purpose
`I/O pins) may be used.
`
`The Interface Clock, IFCLK, can be configured to be either an input (default) or an output interface
`clock for synchronous interfaces to external logic.
`
`The GSTATE[2:0] pins are outputs which show the current GPIF State number; they are typically
`used only when debugging GPIF waveforms.
`
`10.2.2 Default GPIF Pins Configuration
`
`The FX2 comes out of reset with its I/O pins configured in “Ports” mode, not “GPIF Master” mode.
`To configure the pins for GPIF mode, the IFCFG1:0 bits in the IFCONFIG register must be set to
`10 (see Table 13-10, “IFCFG Selection of Port I/O Pin Functions" for details).
`
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`10.2.3 Six Control OUT Signals
`
`The 100- and 128-pin FX2 packages bring out all six Control Output pins, CTL[5:0]. The 56-pin
`package brings out three of these signals, CTL[2:0]. CTLx waveform edges can be programmed to
`make transitions as often as once per IFCLK clock (once every 20.8 ns if IFCLK is running at
`48MHz).
`
`By default, these signals are driven high.
`
`10.2.3.1 Control Output Modes
`
`The GPIF Control pins (CTL[5:0]) have several output modes:
`
`CTL[3:0] can act as CMOS outputs (optionally tristatable) or open-drain outputs.
`
`CTL[5:4] can act as CMOS outputs or open-drain outputs.
`
`If CTL[3:0] are configured to be tristatable, CTL[5:4] are not available.
`
`Table 10-3. CTL[5:0] Output Modes
`
`TRICTL
`(GPIFCTLCFG.7)
`0
`0
`1
`
` GPIFCTLCFG[6:0]
`
` CTL[3:0]
`
` CTL[5:4]
`
`0
`1
`X
`
`CMOS, Not Tristatable
`Open-Drain
`CMOS, Tristatable
`
`CMOS, Not Tristatable
`Open-Drain
`Not Available
`
`10.2.4 Six Ready IN signals
`
`The 100- and 128-pin FX2 packages bring out all six Ready inputs, RDY[5:0]. The 56-pin package
`brings out two of these signals, RDY[1:0].
`
`The RDY inputs can be sampled synchronously or asynchronously. When the GPIF is in asynchro-
`nous mode (SAS=1), the RDY inputs are unavoidably delayed by a small amount (approximately
`24 ns at 48 MHz IFCLK). In other words, when the GPIF “looks” at a RDY input, it actually “sees”
`the state of that input 24 ns ago.
`
`10.2.5 Nine GPIF Address OUT signals
`
`Nine GPIF address lines, GPIFADR[8:0], are available. If the GPIF address lines are configured as
`outputs, writing to the GPIFADRH:L registers drives these pins immediately. The GPIF engine can
`then increment them under control of the Waveform Descriptors. The GPIF address lines can be
`tristated by clearing the associated PORTxCFG bits and OEx bits to 0 (see Section 13.3.3, "Port C
`Alternate Functions" and Section 13.3.4, "Port E Alternate Functions").
`
`Chapter 10. General Programmable Interface (GPIF)
`
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`10.2.6 Three GSTATE OUT signals
`
`Three GPIF State lines, GSTATE[2:0], are available as an alternate configuration of PORTE[2:0].
`These default to general-purpose inputs; setting GSTATE (IFCONFIG.2) to 1 selects the alternate
`configuration and overrides PORTECFG[2:0] bit settings.
`
`The GSTATE[2:0] pins output the current GPIF State number; this feature is typically used only
`while debugging GPIF waveforms.
`
`10.2.7 8/16-Bit Data Path, WORDWIDE = 1 (default) and WORDWIDE = 0
`
`When the FX2 is configured for GPIF Master mode, PORTB is always configured as FD[7:0].
`
`If any of the WORDWIDE bits (EPxFIFOCFG.0) are set to 1, PORTD is automatically configured
`as FD[15:8]. If all the WORDWIDE bits are cleared to 0, PORTD is available for general-purpose
`I/O.
`
`10.2.8 Byte Order for 16-bit GPIF Transactions
`
`Data is sent over USB in packets of 8-bit bytes, not 16-bit words. When the FIFO Data bus is 16
`bits wide, the first byte in every pair sent over USB is transferred over FD[7:0] and the second byte
`is transferred over FD[15:8].
`
`10.2.9 Interface Clock (IFCLK)
`
`The GPIF interface can be clocked from either an internal or an external source. The FX2’s inter-
`nal clock source can be configured to run at either 30 or 48 MHz, and it can optionally be output on
`the IFCLK pin. If the FX2 is configured to use an external clock source, the IFCLK pin can be
`driven at any frequency between 5 MHz and 48 MHz. On power-on reset, the FX2 defaults to the
`internal source at 48 MHz, normal polarity, with the IFCLK output disabled. See Figur e10-4.
`
`IFCONFIG.7 selects between internal and external sources: 0 = external, 1 = internal.
`
`IFCONFIG.6 selects between the 30- and 48-MHz internal clock: 0 = 30 MHz, 1 = 48 MHz. This bit
`has no effect when IFCONFIG.7 = 0.
`
`IFCONFIG.5 is the output enable for the internal clock source: 0 = disable, 1 = enable. This bit has
`no effect when IFCONFIG.7 = 0.
`
`IFCONFIG.4 inverts the polarity of the interface clock (whether it’s internally or externally
`sourced): 0 = normal, 1 = inverted. IFCLK inversion can make it easier to interface the FX2 with
`certain external circuitry; Figure 10-5, for example, demonstrates the use of IFCLK inversion in
`order to ensure a long-enough setup time for reading peripheral signals.
`
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`When IFCLK is configured as an input, the minimum external frequency that can be applied to it is
`5 MHz.
`
`IFCFG .4
`
`IFCFG .5
`
`0 1
`
`IFCFG .6
`
`0 1
`
`30 M Hz
`48 M Hz
`
`IFCLK
`Pin
`
`IFCFG .4
`
`0 1
`
`IFCFG .7
`
`1 0
`
`Internal
`IFCLK
`Signal
`
`Figure 10-4. IFCLK Configuration
`
`Internal IFCLK Signal
`
`Inverted IFCLK Output
`
`Peripheral Signal
`
`Signal
`Asserted
`
`Signal
`Sampled
`
`ts
`
`Figure 10-5. Satisfying Setup Timing by Inverting the IFCLK Output
`
`Chapter 10. General Programmable Interface (GPIF)
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`10.2.10 Connecting GPIF Signal Pins to Hardware
`
`The first step in creating the interface between the FX2’s GPIF and an external peripheral is to
`define the hardware interconnects.
`
`1. Choose IFCLK settings. Decide whether to use an asynchronous or synchronous interface.
`If synchronous, choose either the internal or external interface clock. If internal, choose either
`30 or 48 MHz; if external, ensure that the frequency of the external clock is in the range 5-48
`MHz.
`2. Determine the proper FIFO Data Bus size. If the data bus for the interface is 8 bits wide, use
`the FD[7:0] pins and set WORDWIDE=0. If the data bus for the interface is 16 bits wide, use
`FD[15:0] and set WORDWIDE=1.
`3. Assign the CTLx signals to the interface. Make a list of all interface signals to be driven
`from the GPIF to the peripheral, and assign them to the CTL[5:0] inputs. If there are more out-
`put signals than available CTL outputs, non-GPIF I/O signals must be driven manually by FX2
`firmware. In this case, the CTLx outputs should be assigned only to signals that must be
`driven as part of a data transaction.
`4. Assign the RDYn signals to the interface. Make a list of all interface signals to be driven
`from the peripheral to the GPIF, and assign them to the RDY[5:0] inputs. If there are more
`input signals than available RDY inputs, non-GPIF I/O signals must be sampled manually by
`FX2 firmware. In this case, the RDYn inputs should be used only for signals that must be sam-
`pled as part of a data transaction.
`5. Determine the proper GPIF Address connections. If the interface uses an Address Bus,
`use the GPIFADR[8:0] signals for the least significant bits, and other non-GPIF I/O signals for
`the most significant bits. If the address pins are not needed (as when, for instance, the periph-
`eral is a FIFO) they may be left unconnected.
`
`10.2.11 Example GPIF Hardware Interconnect
`
`The following example illustrates the hardware connections that can be made for a standard inter-
`face to a 27C256 EPROM.
`
`Table 10-4. Example GPIF Hardware Interconnect
`
`Step
`1. Choose IFCLK settings.
`2. Determine proper FIFO
`Data Bus size.
`3. Assign CTLx signals to
`the interface.
`4. Assign RDYn signals to
`the interface.
`5. Determine the proper
`GPIFADR connections.
`
`Result
`Internal IFCLK, 48MHz, Async, GPIF.
`8 bits from the EPROM.
`
`Connection Made
`No connection.
`FD[7:0] to D[7:0]. Firmware
`writes WORDWIDE=0.
`CS and OE are inputs to the EPROM. CTL0 to CS.
`CTL1 to OE.
`No connection.
`
`27C256 EPROM has no
`output ready/wait signals.
`16 bits of address.
`
`GPIFADR[8:0] to A[8:0] and
`other I/O pins to A[15:9].
`
`The process is the same for larger, more-complicated interfaces.
`
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`
`10.3 Programming the GPIF Waveforms
`
`Each GPIF Waveform Descriptor can define up to 7 States. In each State, the GPIF can be pro-
`grammed to:
`
`Drive (high or low) or float the CTL outputs
`
`Sample or drive the FIFO Data bus
`
`Increment the value on the GPIF Address bus
`
`Increment the pointer into the current FIFO
`
`Trigger a GPIFWF (GPIF Waveform) interrupt
`
`Additionally, each State may either sample any two of the following:
`
`The RDYx input pins
`
`A FIFO flag
`
`The INTRDY (internal RDY) flag
`
`The Transaction-Count-Expired flag
`
`then AND, OR, or XOR the two terms and branch on the result to any State
`
`or:
`
`Delay a specified number [1-256] of IFCLK cycles
`
`States which sample and branch are called “Decision Points” (DPs); States which don’t are called
`“Non-Decision Points” (NDPs).
`
`
`
`State 7
`
`IDLE
`
`CPU
`
`trig
`
`(A LFunc B)
`
`where:
`Y
`
`6
`
`NDP
`
`DP
`
`State X
`
`State Y
`
`1
`
`and
`GPIF State Machine
`X = Y-1
`(up to 7 programmable states)
`
`{AND,
`OR,
`XOR}
`
`Done
`
`IDLE
`
`State 7
`(reserved)
`
`CPU GPIF
`
`Event
`INTRDY bit
`GPIFWF ISR
`
`Firmware Hooks
`
`Figure 10-6. GPIF State Machine Overview
`
`Chapter 10. General Programmable Interface (GPIF)
`
`Page 10-11
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`(cid:127)
`(cid:127)
`(cid:127)
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`10.3.1 The GPIF Registers
`
`Two blocks of registers control the GPIF state machine:
`
`GPIF Configuration Registers — These registers configure the general settings and
`report the status of the interface. Refer to Chapter 15, "Registers," and the remainder of
`this chapter for details.
`
`(cid:127) Waveform Registers — These registers are loaded with the Waveform Descriptors that
`configure the GPIF state machine; there are a total of 128 bytes located at addresses
`0xE400 to 0xE47F. It is strongly recommended that the GPIFTool utility be used to create
`Waveform Descriptors.
`
`GPIF transactions cannot be initiated until the Configuration Registers and Waveform Registers
`are loaded by FX2 firmware.
`
`Access to the waveform registers is only allowed while the FX2 is in GPIF mode (i.e., IFCFG1:0 =
`10). The waveform registers may only be written while the GPIF engine is halted (i.e., DONE = 1).
`
`If it’s desired to dynamically reconfigure Waveform Descriptors, this may be accomplished by writ-
`ing just the bytes which change; it’s not necessary to reload the entire set of Waveform Descrip-
`tors in order to modify only a few bytes.
`
`10.3.2 Programming GPIF Waveforms
`
`The “programs” for GPIF waveforms are the Waveform Descriptors, which are stored in the Wave-
`form Registers by FX2 firmware.
`
`The FX2 can hold up to four Waveform Descriptors, each of which can be used for one of four
`types of transfers: Single Write, Single Read, FIFO Write, or FIFO Read. By default, one Wave-
`form Descriptor is assigned to each transfer type, but it’s not necessary to retain that configuration;
`all four Waveform Descriptors could, for instance, be configured for FIFO Write usage (see the
`GPIFWFSELECT register in Chapter 15 "Registers").
`
`Each Waveform Descriptor consists of up to seven 32-bit State Instructions that program key tran-
`sition points for GPIF interface signals. There’s a one-to-one correspondence between the State
`Instructions and the GPIF state-machine States. Among other things, each State Instruction
`defines the state of the CTLx outputs, the state of FD[15:0], the use of the RDYn inputs, and the
`behavior of GPIFADR[8:0].
`
`Transitions from one State to another always happen on a rising edge of the IFCLK, but the GPIF
`may remain in one State for many IFCLK cycles.
`
`10.3.2.1 The GPIF IDLE State
`
`A Waveform consists of up to seven programmable States, numbered S0 to S6, and one special
`Idle State, S7. A Waveform terminates when the GPIF program branches to its Idle State.
`
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`
`To complete a GPIF transaction, the GPIF program must branch to the IDLE State, regardless of
`the State that the GPIF program is currently executing. For example, a GPIF Waveform might be
`defined by a program which contained only 2 programmed States, S0 and S1. The GPIF program
`would branch from S1 (or S0) to S7 when it wished to terminate.
`
`The state of the GPIF signals during the Idle State is determined by the contents of the
`GPIFIDLECS and GPIFIDLECTL registers.
`
`Once a waveform is triggered, another waveform may not be started until the first one terminates.
`Termination of a waveform is signaled through the DONE bit (GPIFIDLECS.7 or GPIFTRIG.7) or,
`optionally, through the GPIFDONE interrupt.
`
`If DONE = 0, the GPIF is busy generating a Waveform.
`
`If DONE = 1, the GPIF is done (GPIF is in the Idle State) and ready for firmware to start
`the next GPIF transaction.
`
`Important: With one exception (writing to the GPIFABORT register in order to force the current
`waveform to terminate) it is illegal to write to any of the GPIF-related registers (including the Wave-
`form Registers) while the GPIF is busy. Doing so will cause indeterminate behavior likely to result
`in data corruption.
`
`10.3.2.1.1 GPIF Data Bus During IDLE
`During the Idle State, the GPIF Data Bus (FD[15:0]) can be either driven or tristated, depending on
`the setting of the IDLEDRV bit (GPIFIDLECS.0):
`
`If IDLEDRV = 0, the GPIF Data Bus is tristated during the Idle State.
`
`If IDLEDRV = 1, the GPIF Data Bus is actively driven during the Idle State, to the value last
`placed on the bus by a GPIF Waveform.
`
`10.3.2.1.2 CTL Outputs During IDLE
`During the IDLE State, the state of CTL[5:0] depends on the following register bits:
`
`TRICTL (GPIFCTLCFG.7), as described in Section 10.2.3.1, "Control Output Modes".
`
`(cid:127) GPIFCTLCFG[5:0]
`
`(cid:127) GPIFIDLECTL[5:0].
`
`The combination of these bits defines CTL5:0 during IDLE as follows:
`
`If TRICTL is 0, GPIFIDLECTL[5:0] directly represent the output states of CTL5:0 during
`the IDLE State. The GPIFCTLCFG[5:0] bits determine whether the CTL5:0 outputs are
`CMOS or open-drain: If GPIFCTLCFG.x = 0, CTLx is CMOS; if GPIFCTLCFG.x = 1, CTLx
`is open-drain.
`
`Chapter 10. General Programmable Interface (GPIF)
`
`Page 10-13
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`Exhibit 2058 - Page 203 of 460
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`(cid:127)
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`(cid:127)
`(cid:127)
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`
`EZ-USB FX2 Technical Reference Manual
`
`If TRICTL is 1, GPIFIDLECTL[7:4] are the output enables for the CTL[3:0] signals, and
`GPIFIDLECTL[3:0] are the output values for CTL[3:0]. CTL4 and CTL5 are unavailable in
`this mode.
`
`Table 10-5 illustrates this relationship.
`
`Table 10-5. Control Outputs (CTLn) During the IDLE State
`
`TRICTL
`
`0
`
`1
`
`Control Output
`CTL0
`CTL1
`CTL2
`CTL3
`CTL4
`CTL5
`CTL0
`CTL1
`CTL2
`CTL3
`CTL4
`CTL5
`
`Output State
`GPIFIDLECTL.0
`GPIFIDLECTL.1
`GPIFIDLECTL.2
`GPIFIDLECTL.3
`GPIFIDLECTL.4
`GPIFIDLECTL.5
`GPIFIDLECTL.0
`GPIFIDLECTL.1
`GPIFIDLECTL.2
`GPIFIDLECTL.3
`
`Output Enable
`
`N/A
`(CTL Outputs are always
`enabled when TRICTL = 0)
`
`GPIFIDLECTL.4
`GPIFIDLECTL.5
`GPIFIDLECTL.6
`GPIFIDLECTL.7
`N/A
`(CTL4 and CTL5 are not available when TRICTL = 1)
`
`10.3.2.2 Defining States
`
`Each Waveform is made up of a number of States, each of which is defined by a 32-bit State
`Instruction. Each State can be one of two basic types: a Non-Decision Point (NDP) or a Decision
`Point (DP).
`
`For “write” waveforms, the data bus is either driven or tristated during each State. For “read” wave-
`forms, the data bus is either sampled/stored or not sampled during each State.
`
`10.3.2.2.1 Non-Decision Point (NDP) States
`For NDP States, the control outputs (CTLx) are defined by the GPIF instruction to be either 1, 0, or
`tristated during the entire State. NDP States have a programmable fixed duration in units of IFCLK
`cycles.
`
`Figure 10-7 illustrates the basic concept of NDP States. A write waveform is shown, and for sim-
`plicity all the States are shown with equal spacing. Although there are a total of six programmable
`CTL outputs, only one (CTL0) is shown in Figure 10-7.
`
`Page 10-14
`
`EZ-USB FX2 Technical Reference Manual v2.1
`
`Exhibit 2058 - Page 204 of 460
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`(cid:127)
`

`
`S0
`
`S1
`
`S2
`
`S3
`
`S4
`
`S5
`
`S6
`
`GADR[8:0]
`
`A
`
`FD[15:0]
`
`Z
`
`VALID
`
`Z
`
`CTL0
`
`Figure 10-7. Non-Decision Point (NDP) States
`
`Referring to Figure 10-7:
`
` In State 0:
`FD[7:0] is programmed to be tristated.
`CTL0 is programmed to be driven to a logic 1.
`
`In State 1:
`FD[7:0] is programmed to be driven.
`CTL0 is still programmed to be driven to a logic 1.
`
`In State 2:
`FD[7:0] is programmed to be driven.
`CTL0 is programmed to be driven to a logic 0.
`
`In State 3:
`FD[7:0] is programmed to be driven.
`CTL0 is still programmed to be driven to a logic 0.
`
`In State 4:
`FD[7:0] is programmed to be driven.
`CTL0 is programmed to be driven to a logic 1.
`
`In State 5:
`FD[7:0] is programmed to be tristated.
`CTL0 is still programmed to be driven to a logic 1.
`
`In State 6:
`FD[7:0] is programmed to be tristated.
`CTL0 is still programmed to be driven to a logic 1.
`
`Chapter 10. General Programmable Interface (GPIF)
`
`Page 10-15
`
`Exhibit 2058 - Page 205 of 460
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`(cid:127)
`(cid:127)
`(cid:127)
`(cid:127)
`(cid:127)
`(cid:127)
`(cid:127)
`(cid:127)
`(cid:127)
`(cid:127)
`(cid:127)
`(cid:127)
`(cid:127)
`(cid:127)
`

`
`EZ-USB FX2 Technical Reference Manual
`
`Since all States in this example are coded as NDPs, the GPIF automatically branches from the
`last State (S6) to the Idle State (S7). This is the State in which the GPIF waits until the next GPIF
`waveform is triggered by the firmware.
`
`States 2 and 3 in the example are identical, as are States 5 and 6. In a real application, these
`would probably be combined (there’s no need to duplicate a State in order to “stretch” it, since
`each NDP State can be assigned a duration in terms of IFCLK cycles). If fewer than 7 States were
`defined for this waveform, the Idle State wouldn’t automatically be entered after the last pro-
`grammed State; that last programmed State’s State Instruction would have to include an explicit
`branch to the Idle State.
`
`10.3.2.2.2 Decision Point (DP) States
`Any State can be designated as a Decision Point (DP). A DP allows the GPIF engine to sample
`two signals — each of the “two” can be the same signal, if desired — perform a boolean operation
`on the sampled values, then branch to other States (or loop back on itself, remaining in the current
`State) based on the result.
`
`If a State Instruction includes a control task (advance the FIFO pointer, increment the GPIFADR
`address, etc.), that task is always executed once upon entering the State, regardless of whether
`the State is a DP or NDP. If the State is a DP that loops back on itself, however, it can be pro-
`grammed to re-execute the control task on every loop.
`
`With a Decision Point, the GPIF can perform simple tasks (wait until a RDY line is low before con-
`tinuing to the next State, for instance). Decision point States can also perform more-complex tasks
`by branching to one State if the operation on the sampled signals results in a logic 1, or to a differ-
`ent State if it results in a logic 0.
`
`In each State Instruction, the two signals to sample can be selected from any of the following:
`
`the six external RDY signals (RDY0-RDY5)
`one of the current FIFO’s flags (PF, EF, FF)
`the INTRDY bit in the READY register
`a “Transaction Count Expired” signal (which replaces RDY5)
`
`The State Instruction also specifies a logic function (AND, OR, or XOR) to be applied to the two
`selected signals. If it’s desired to act on the state of only one signal, the usual procedure is to
`select the same signal twice and specify the logic function as AND.
`
`The State Instruction also specifies which State to branch to if the result of the logical expression
`is 0, and which State to branch to if the result of the logical expression is 1.
`
`Below is an example waveform created using one Decision Point State (State 1); Non-Decision
`Point States are used for the rest of the waveform.
`
`Page 10-16
`
`EZ-USB FX2 Technical Reference Manual v2.1
`
`Exhibit 2058 - Page 206 of 460
`
`(cid:127)
`(cid:127)
`(cid:127)
`(cid:127)
`

`
`S1
`
`S2
`
`S3
`
`S4
`
`S5
`
`S6
`
`VALID
`
`Z
`
`S0
`
`A
`
`Z
`
`GADR[8:0]
`
`FD[15:0]
`
`CTL0
`
`RDY0
`
`Figure 10-8. One Decision Point: Wait States Inserted Until RDY0 Goes Low
`
`S0
`
`S1
`
`S2
`
`S3
`
`S4
`
`S5
`
`S6
`
`A
`
`Z
`
`GADR[8:0]
`
`FD[15:0]
`
`CTL0
`
`RDY0
`
`VALID
`
`Z
`
`Figure 10-9. One Decision Point: No Wait States Inserted:
`RDY0 is Already Low at Decision Point I1
`
`In Figure 10-8 and Figure 10-9, there is a single Decision Point defined as State 1. In this example,
`the input ready signal is assumed to be connected to RDY0, and the State Instruction for S1 is
`configured to branch to State 2 if RDY0 is a logic 0 or to branch to State 1 (i.e., loop indefinitely) if
`RDY0 is a logic 1.
`
`Chapter 10. General Programmable Interface (GPIF)
`
`Page 10-17
`
`Exhibit 2058 - Page 207 of 460
`
`

`
`EZ-USB FX2 Technical Reference Manual
`
`In Figure 10-8, the GPIF remains in S1 until the RDY0 signal goes low, then branches to S2.
`Figure 10-9 illustrates the GPIF behavior when the RDY0 signal is already low when S1 is
`entered: The GPIF branches to S2.
`
`Although it appears in Figure 10-8 that the GPIF branches immediately from State 0 to State 2,
`this isn’t exactly true. Even if RDY0 is already low before the GPIF enters State 1, the GPIF
`spends one IFCLK cycle in State 1.
`
`10.3.3 Re-Executing a Task Within a DP State
`
`In the simple DP examples shown earlier in this chapter, a control task (e.g., output a word on
`FD[15:0] and increment GPIFADR[8:0]) executes only once at the start of a DP State, then the
`GPIF waits, sampling a RDYx input repeatedly until that input “tells” the GPIF to branch to the next
`State.
`
`The GPIF also has the capability to re-execute the control task every time the RDYx input is sam-
`pled; this feature can be used to burst a large amount of data without passing through the Idle
`State.
`
`Page 10-18
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`EZ-USB FX2 Technical Reference Manual v2.1
`
`Exhibit 2058 - Page 208 of 460
`
`

`
`A+1
`
`D+1
`
`A+2
`
`D+2
`
`A+3
`
`D+3
`
`A D
`
`NDP
`
`DP
`
`NDP
`
`DP, transitions to
`next interval when
`term s are m et
`
`DP, using re-execute control
`task feature… to loop on to
`itself until term s are m et
`
`Figure 10-10. Re-Executing a Task within a DP State
`
`IFCLK
`
`G ADR[8:0]
`
`FD[7:0]
`
`CTL0
`
`RDY0
`
`State
`AddrMode
`DataMode
`NextData
`Int Trig
`
`IF/Wait
`Term A
`LFUNC
`Term B
`Branch1
`Branch0
`Re-execute
`CTL0
`CTL1
`CTL2
`CTL3
`CLT4
`CTL5
`
`1
`0
`Same Val
`Inc Val
`Activate
`Activate
`SameData NextData
`No Int
`No Int
`Wait 4
`IF
`RDY0
`AND
`RDY0
`Then 2
`Else 1
`Yes
`0
`1
`1
`1
`1
`1
`
`1
`1
`1
`1
`1
`1
`
`6
`5
`4
`3
`2
`Same Val
`Same Val
`Same Val
`Same Val
`Same Val
`NO Data
`NO Data
`NO Data
`NO Data
`NO Data
`SameData SameData SameData SameData SameData
`No Int
`No Int
`No Int
`No Int
`No Int
`Wait 1
`Wait 1
`Wait 1
`Wait 1
`Wait 1
`
`1
`1
`1
`1
`1
`1
`
`1
`1
`1
`1
`1
`1
`
`1
`1
`1
`1
`1
`1
`
`1
`1
`1
`1
`1
`1
`
`1
`1
`1
`1
`1
`1
`
`7
`
`1
`1
`1
`1
`1
`1
`
`Figure 10-11. GPIFTool Setup for the Waveform of Figure 10-10
`
`Chapter 10. General Programmable Interface (GPIF)
`
`Page 10-19
`
`Exhibit 2058 - Page 209 of 460
`
`

`
`EZ-USB FX2 Technical Reference Manual
`
`A+1
`
`D+1
`
`A D
`
`NDP
`
`DP
`
`NDP
`
`DP, transitions to
`next interval when
`term s are m et
`
`IFCLK
`
`G ADR[8:0]
`
`FD[7:0]
`
`CTL0
`
`RDY0
`
`DP, loop on to itself until term s
`are m et… control tasks execute
`on rising edge transition into
`DP only…
`
`Figure 10-12. A DP State Which Does NOT Re-Execute the Task
`
`State
`AddrMode
`DataMode
`NextData
`Int Trig
`
`IF/Wait
`Term A
`LFUNC
`Term B
`Branch1
`Branch0
`Re-execute
`CTL0
`CTL1
`CTL2
`CTL3
`CLT4
`CTL5
`
`1
`0
`Same Val
`Inc Val
`Activate
`Activate
`SameData NextData
`No Int
`No Int
`Wait 4
`IF
`RDY0
`AND
`RDY0
`Then 2
`Else 1
`No
`0
`1
`1
`1
`1
`1
`
`1
`1
`1
`1
`1
`1
`
`6
`5
`4
`3
`2
`Same Val
`Same Val
`Same Val
`Same Val
`Same Val
`NO Data
`NO Data
`NO Data
`NO Data
`NO Data
`SameData SameData SameData SameData SameData
`No Int
`No Int
`No Int
`No Int
`No Int
`Wait 1
`Wait 1
`Wait 1
`Wait 1
`Wait 1
`
`1
`1
`1
`1
`1
`1
`
`1
`1
`1
`1
`1
`1
`
`1
`1
`1
`1
`1
`1
`
`1
`1
`1
`1
`1
`1
`
`1
`1
`1
`1
`1
`1
`
`7
`
`1
`1
`1
`1
`1
`1
`
`Figure 10-13. GPIFTool Setup for the Waveform of Figure 10-12
`
`Page 10-20
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`
`Exhibit 2058 - Page 210 of 460
`
`

`
`10.3.4 State Instructions
`
`Each State’s characteristics are defined by a 4-byte State Instruction. The four bytes are named
`LENGTH / BRANCH, OPCODE, LOGIC FUNCTION, and OUTPUT.
`
`Note that the State Instructions are interpreted differently for Decision Points (DP = 1) and Non-
`Decision Points (DP = 0).
`
` Non-Decision Point State Instruction (DP = 0)
`
`Bit 7
`
`Bit 6
`
`Bit 2
`Bit 3
`Bit 4
`Bit 5
`Number of IFCLK cycles to stay in this State (0 = 256 cycles)
`
`Bit 1
`
`Bit 0
`
`LENGTH / BRANCH
`
`7
`x
`
`7
`
`7
`OE3
`
`7
`x
`
`6
`x
`
`6
`
`6
`OE2
`
`6
`x
`
`OPCODE
`
`5
`SGL
`
`4
`GINT
`
`3
`INCAD
`
`LOGIC FUNCTION
`
`2
`NEXT/
`SGLCRC
`
`1
`DATA
`
`0
`DP = 0
`
`5
`
`4
`
`3
`
`2
`
`1
`
`0
`
`Not Used
`
`OUTPUT (if TRICTL Bit = 1)
`
`4
`OE0
`
`3
`CTL3
`
`OUTPUT (if TRICTL Bit = 0)
`
`4
`CTL4
`
`3
`CTL3
`
`5
`OE1
`
`5
`CTL5
`
`2
`CTL2
`
`2
`CTL2
`
`1
`CTL1
`
`1
`CTL1
`
`0
`CTL0
`
`0
`CTL0
`
`Chapter 10. General Programmable Interface (GPIF)
`
`Page 10-21
`
`Exhibit 2058 - Page 211 of 460
`
`

`
`EZ-USB FX2 Technical Reference Manual
`
` Decision Point State Instruction (DP = 1)
`
`Bit 7
`Re-Execute
`
`Bit 6
`x
`
`Bit 5
`
`Bit 4
`BRANCHON1
`
`Bit 3
`
`Bit 2
`
`Bit 1
`BRANCHON1
`
`Bit 0
`
`LENGTH / BRANCH
`
`7
`x
`
`7
`
`7
`OE3
`
`7
`x
`
`LFUNC
`
`6
`x
`
`6
`
`6
`OE2
`
`6
`x
`
`5
`SGL
`
`5
`
`5
`OE1
`
`5
`CTL5
`
`OPCODE
`
`4
`GINT
`
`3
`INCAD
`
`LOGIC FUNCTION
`
`2
`NEXT/
`SGLCRC
`
`1
`DATA
`
`0
`DP = 1
`
`4
`TERMA
`
`3
`
`2
`
`1
`TERMB
`
`0
`
`OUTPUT (if TRICTL Bit = 1)
`
`4
`OE0
`
`3
`CTL3
`
`OUTPUT (if TRICTL Bit = 0)
`
`4
`CTL4
`
`3
`CTL3
`
`2
`CTL2
`
`2
`CTL2
`
`1
`CTL1
`
`1
`CTL1
`
`0
`CTL0
`
`0
`CTL0
`
`LENGTH /