Claim Ch artfor U.S. PatentNo. 6,249 ,825
`
`Th is claim ch artm aps som e ofth e claim s ofU.S. PatentNo. 6,249 ,825 (‘825
`patent)to Anch or Ch ips’EZ -USB product(e.g., partno. AN2131xx)and to
`Cypress’EZ -USB FX product(e.g., partno. CY7C646xx).
`
`Anch or Ch ips’EZ -USB: Th e EZ -USB Integrated Circuit(IC)
`is a solution for h igh -speed USB periph eraldevices (i.e., USB
`periph erals)th atare attach ed to a h ostPC th rough a USB port.
`
`CLAIM 1
`1. A system for
`reconfiguring a
`periph eral
`device h aving a
`first
`configuration
`connected by a
`com puter bus
`and a portto a
`h ostcom puter,
`th e system
`com prising:
`
`Ex. 2025, pp. 2.
`
`Ex. 2025, pp. 4.
`
`1
`
`Exhibit 2023 - Page 01 of 18
`
`
`
`Th is claim ch artm aps som e ofth e claim s ofU.S. PatentNo. 6,249 ,825 (‘825
`patent)to Anch or Ch ips’EZ -USB product(e.g., partno. AN2131xx)and to
`Cypress’EZ -USB FX product(e.g., partno. CY7C646xx).
`
`Anch or Ch ips’EZ -USB: Th e EZ -USB Integrated Circuit(IC)
`is a solution for h igh -speed USB periph eraldevices (i.e., USB
`periph erals)th atare attach ed to a h ostPC th rough a USB port.
`
`CLAIM 1
`1. A system for
`reconfiguring a
`periph eral
`device h aving a
`first
`configuration
`connected by a
`com puter bus
`and a portto a
`h ostcom puter,
`th e system
`com prising:
`
`Ex. 2025, pp. 2.
`
`Ex. 2025, pp. 4.
`
`1
`
`Exhibit 2023 - Page 01 of 18
`
`
`
`Th e USB periph eralw ith th e EZ -USB IC h as an initial
`configuration upon start-up.
`
`Ex. 2025, p. 5.
`
`Cypress’EZ -USB FX: Th e EZ -USB FX ch ip is a com pactIC
`th atprovides a h igh ly integrated solution for a USB periph eral
`device.
`
`Ex. 2032, pp. 29 (docum entpage 1-1).
`
`A USB periph eraldevice can attach to a h ostcom puter th rough
`a USB bus and connector (e.g., h aving pins D+ and D–).
`
`Ex. 2032, pp. 30 (docum entpage 1-2).
`
`2
`
`Exhibit 2023 - Page 02 of 18
`
`
`
`Ex. 2032, pp. 33 (docum entpage 1-5).
`
`Th e USB periph eraldevice w ith th e EZ -USB FX IC h as an
`initialconfiguration (e.g., upon pow er-on).
`
`Ex. 2032, pp. 85 (docum entpage 5-1).
`
`Anch or Ch ips’EZ -USB: Th e EZ -USB IC includes one or
`m ore circuits to dow nload inform ation for a second
`configuration from th e h ostPC into th e USB periph eralover
`th e USB bus. For exam ple, in th e figure below , th e Anch or
`Sm artUSB Engine Core is coupled to th e USB bus (w h ich
`includes th e D+ and D- lines)and includes one or m ore circuits
`configured to dow nload inform ation from th e h ostPC.
`
`a firstcircuit
`configured to
`dow nload
`inform ation for
`a second
`configuration
`from th e h ost
`com puter into
`th e periph eral
`device over th e
`com puter bus;
`and
`
`Ex. 2025, pp. 1.
`
`3
`
`Exhibit 2023 - Page 03 of 18
`
`
`
`Th e circuits connected to th e USB bus are configured to
`dow nload second configuration inform ation from th e h ostPC
`to th e USB periph eralover th e USB bus.
`
`Ex. 2025, pp. 5.
`
`Cypress’EZ -USB FX: Th e EZ -USB FX IC includes one or
`m ore circuits to dow nload inform ation for a second
`configuration from th e h ostcom puter into th e USB periph eral
`over th e USB bus. For exam ple, in th e figure below , th e Serial
`Interface Engine (SIE)is coupled to th e USB bus over a USB
`connector and includes one or m ore circuits configured to
`dow nload inform ation from th e h ostcom puter.
`
`4
`
`Exhibit 2023 - Page 04 of 18
`
`
`
`Ex. 2032, pp. 30 (docum entpage 1-2).
`
`Anch or Ch ips’EZ -USB: Th e EZ -USB IC includes one or
`m ore circuits to electronically sim ulate a ph ysical
`disconnection and reconnection ofth e periph eraldevice over
`th e USB bus. For exam ple, in th e figure below , th e Anch or
`Sm artUSB Engine Core includes one or m ore circuits
`configured to sim ulate a ph ysicaldisconnection and
`reconnection after th e second configuration is dow nloaded in
`RAM .
`
`a second circuit
`configured to
`electronically
`sim ulate a
`ph ysical
`disconnection
`and
`reconnection of
`th e periph eral
`device over said
`com puter bus to
`reconfigure th e
`periph eral
`device to said
`second
`configuration.
`
`5
`
`Exhibit 2023 - Page 05 of 18
`
`
`
`Ex. 2025, p. 1.
`
`Th e EZ -USB IC’s USB Engine Core sim ulates a ph ysical
`disconnectand re-connectand th e h ostPC recognizes
`attach m entofth e new USB periph eraldevice w ith th e updated
`second configuration.
`
`Ex. 2025, p. 5.
`
`Cypress’EZ -USB FX: Th e EZ -USB FX IC includes one or
`m ore circuits to electronically sim ulate a ph ysical
`disconnection and reconnection ofth e periph eraldevice over
`th e USB bus. For exam ple, in th e figure below , th e SIE
`includes one or m ore circuits configured to sim ulate a ph ysical
`disconnection and reconnection after th e second configuration
`is dow nloaded in RAM .
`
`6
`
`Exhibit 2023 - Page 06 of 18
`
`
`
`Ex. 2032, pp. 30 (docum entpage 1-2).
`
`Ex. 2032, pp. 85 (docum entpage 5-1).
`
`M ore specifically, th ree EZ -USB FX controlbits in th e USBCS
`(USB Controland Status)Register controlth e ReNum eration™
`process: DISCO N, DISCO E, and RENUM . To sim ulate a USB
`disconnect, th e 8051 (m icroprocessor)w rites a specific value to
`th e USBCS Register. To re-connectto th e USB, th e 8051
`w rites anoth er specific value to th e USBCS Register. A typical
`disconnect/reconnectcircuitis illustrated in th e figure below .
`
`7
`
`Exhibit 2023 - Page 07 of 18
`
`
`
`
`
`The logic for the DISCON and DISCOE bits is shown in Figure 5-3. To simulate a USB disconnect,
`the 0051 writes the value 00001010 to USBCS. This floats the DISCON# pin, and provides an
`internal DISCON=1 signal to the USB core that causes it to perform disconnect housekeeping.
`
`To re4:onnect to USB, the 8051 writes the value 00100110 to USBCS. This presents a logic HII to
`the DISCON# pin, enables the output buffer, and sets the RENUM bit H| to indicate that the 0051
`(and not the USB core) is now in control for USB transfers. This arrangement allows connecting
`the 1,500—ohm resistor directly between the DISCONti! pin and the USB D+ tine (Figure 5—4).
`
`
`
`
`
`
`
`Ex. 2032, pp. 9 5-9 6 (docum entpages 5-11, 5-12).
`Ex. 2032,
`.95-96 (document a es 5-11, 5-12).
`
`Figure 5-4. Typical Disconnect Circuit
`
`8
`
`Exhibit 2023 - Page 08 of 18
`
`Exhibit 2023 - Page 08 of 18
`
`
`
`CLAIM 5
`5. Th e system
`ofclaim 1,
`w h erein said
`com puter bus
`and port
`com prise a
`UniversalSerial
`Bus and port.
`
`Anch or Ch ips’EZ -USB: Th e EZ -USB Integrated Circuit(IC)is
`a single-ch ip low -pow er solution for USB periph erals.
`
`Ex. 2025, pp. 1.
`
`Th e USB periph eral(w ith th e EZ -USB IC)is attach ed to th e h ost
`PC th rough a USB port.
`
`Ex. 2025, pp. 2.
`
`Cypress’EZ -USB FX: Th e EZ -USB FX ch ip is a com pactIC
`th atprovides a h igh ly integrated solution for a USB periph eral
`device.
`
`Ex. 2032, pp. 29 (docum entpage 1-1).
`
`A USB periph eraldevice can attach to a h ostcom puter th rough a
`USB bus and connector (e.g., h aving pins D+ and D–).
`
`9
`
`Exhibit 2023 - Page 09 of 18
`
`
`
`
`
`
`
`
`
`
`
`
`U S B
`
`“3mm“
`
`EZ.USB
`
`EX. 2032, pp. 33 (document page 1-5).
`
`
`
`
`
`Program 8.
`USE
`Data
`
`RA."
`Interface
`Genera
`Purpose
`
`Microprocessor
`
`
`
`
`GPlF
`
`_q__
`Slave FIFOs
`
`
`
`t.w...-
`'L_______________________________________________________________________ 15 Emmi
`
`Figure 1—1. CYI’CS46x3—SUNC (80 pin) Simplified Biock Diagram
`
`The Cypress Semiconductor EZ—USB FX chip packs line intelligence required by a USB peripheral
`interface into a compact, integrated circuit. As Figure 1—1 illustrates, an integrated USB transceiver
`connects to the USB bus pins D+ and D-. A Serial Interface Engine {SIE} decodes and encodes
`the serial data and performs error correction, bit stuffing, and other signaling—level details required
`by USB. Ultimately, the SIE transfers data bytes to and from the USB interface.
`
`Ex. 2032, pp. 30 (docum entpage 1-2).
`EX. 2032, pp. 30 (document page 1-2).
`
`
`1.5 Host is Master
`
`This is a fundamental USB concept. There is erracth,r one master in a USB system: the host com—
`puter. USB devices respond to host requests. USB devices cannot send information between
`themselves, as the):r could it USE were a peer—to—peer tcpology.
`
`Ex. 2032, pp. 33 (docum entpage 1-5).
`
`10
`10
`
`Exhibit 2023 - Page 10 of 18
`
`Exhibit 2023 - Page 10 of 18
`
`
`
`CLAIM 11
`11. A m eth od
`for
`reconfiguring a
`periph eral
`device h aving a
`first
`configuration
`connected by a
`com puter bus
`and portto a
`h ostcom puter,
`th e m eth od
`com prising th e
`steps of:
`(A)
`dow nloading
`inform ation for
`a second
`configuration
`from th e h ost
`com puter into
`th e periph eral
`device over th e
`com puter bus;
`and
`(B)
`electronically
`sim ulating a
`ph ysical
`disconnection
`and
`reconnection of
`th e periph eral
`device over said
`com puter bus to
`reconfigure th e
`periph eral
`device to said
`
`Anch or Ch ips’EZ -USB: Th e EZ -USB IC is configured to
`perform a m eth od for reconfiguring a USB periph eraldevice th at
`is connected to h ostcom puter. See th e pream ble ofClaim 1.
`
`Cypress’EZ -USB FX: Th e EZ -USB FX IC is configured to
`perform a m eth od for reconfiguring a USB periph eraldevice th at
`is connected to h ostcom puter. See th e pream ble ofClaim 1.
`
`See th e firstlim itation ofClaim 1.
`
`See th e second lim itation ofClaim 1.
`
`11
`
`Exhibit 2023 - Page 11 of 18
`
`
`
`See Claim s 1 and 5.
`
`second
`configuration.
`
`CLAIM 15
`15. Th e m eth od
`ofclaim 11,
`w h erein step
`(A)com prises
`com m unicating
`said inform ation
`for th e second
`configuration to
`th e periph eral
`device using a
`UniversalSerial
`Bus.
`
`12
`
`Exhibit 2023 - Page 12 of 18
`
`
`
`Anch or Ch ips’EZ -USB: Th e EZ -USB Integrated Circuit(IC)is
`a solution for h igh -speed USB periph erals th atare attach ed to a
`h ostPC.
`
`CLAIM 18
`18. A system
`for sim ulating a
`disconnection
`and
`reconnection of
`a periph eral
`device
`connected by a
`com puter bus
`and a portto a
`h ostcom puter,
`th e system
`com prising:
`
`Ex. 2025, pp. 2.
`
`Ex. 2025, pp. 4.
`
`13
`
`Exhibit 2023 - Page 13 of 18
`
`
`
`Cypress’EZ -USB FX: Th e EZ -USB FX ch ip is a com pactIC
`th atprovides a h igh ly integrated solution for a USB periph eral
`device.
`
`Ex. 2032, pp. 29 (docum entpage 1-1).
`
`A USB periph eraldevice can attach to a h ostcom puter th rough a
`USB bus and connector (e.g., h aving pins D+ and D–).
`
`Ex. 2032, pp. 30 (docum entpage 1-2).
`
`Ex. 2032, pp. 33 (docum entpage 1-5).
`
`Anch or Ch ips’EZ -USB: A h ostPC includes one or m ore
`circuits to detectconnection ofth e USB periph eralw ith th e EZ -
`USB IC to th e h ostPC over th e USB bus. Se e e.g., Ex. 1013
`(USB 1.0 Spec), Sections 7.1.3, 7.1.4.1, 9 .1.2.
`
`a firstcircuit
`configured to
`detectth e
`periph eral
`device
`
`14
`
`Exhibit 2023 - Page 14 of 18
`
`
`
`connected to th e
`port;and
`
`Cypress’EZ -USB FX: A h ostcom puter includes one or m ore
`circuits to detectconnection ofth e USB periph eralw ith th e EZ -
`USB FX IC to th e h ostcom puter over th e USB bus. Se e e.g., Ex.
`1013 (USB 1.0 Spec), Sections 7.1.3, 7.1.4.1, 9 .1.2.
`
`Anch or Ch ips’EZ -USB: Th e EZ -USB IC includes one or m ore
`circuits to electronically sim ulate a ph ysicaldisconnection and
`reconnection ofth e periph eraldevice over th e USB bus. For
`exam ple, in th e figure below , th e Anch or Sm artUSB Engine Core
`includes one or m ore circuits configured to sim ulate a ph ysical
`disconnection and reconnection.
`
`a second circuit
`configured to
`electronically
`sim ulate a
`ph ysical
`disconnection
`and
`reconnection of
`th e periph eral
`device over said
`com puter bus.
`
`Ex. 2025, p. 1.
`
`Th e EZ -USB IC’s USB Engine Core sim ulates a ph ysical
`disconnectand re-connectand th e h ostPC recognizes attach m ent
`ofth e new USB device w ith th e updated second configuration.
`
`15
`
`Exhibit 2023 - Page 15 of 18
`
`
`
`Ex. 2025, p. 5.
`
`Cypress’EZ -USB FX: Th e EZ -USB FX IC includes one or
`m ore circuits to electronically sim ulate a ph ysicaldisconnection
`and reconnection ofth e periph eraldevice over th e USB bus. For
`exam ple, in th e figure below , th e SIE includes one or m ore
`circuits configured to sim ulate a ph ysicaldisconnection and
`reconnection after th e second configuration is dow nloaded in
`RAM .
`
`Ex. 2032, pp. 30 (docum entpage 1-2).
`
`Ex. 2032, pp. 85 (docum entpage 5-1).
`
`M ore specifically, th ree EZ -USB FX controlbits in th e USBCS
`(USB Controland Status)Register controlth e ReNum eration™
`
`16
`
`Exhibit 2023 - Page 16 of 18
`
`
`
`process: DISCO N, DISCO E, and RENUM . To sim ulate a USB
`disconnect, th e 8051 (m icroprocessor)w rites a specific value to
`th e USBCS Register. To re-connectto th e USB, th e 8051 w rites
`anoth er specific value to th e USBCS Register. A typical
`disconnect/reconnectcircuitis illustrated in th e figure below .
`
`Ex. 2032, pp. 9 5-9 6 (docum entpages 5-11, 5-12).
`
`Anch or Ch ips’EZ -USB: Th e EZ -USB Integrated Circuit(IC)is
`a single-ch ip low -pow er solution for h igh -speed USB periph erals.
`
`CLAIM 19
`19 . Th e system
`ofclaim 18,
`w h erein said
`com puter bus
`and port
`com prise a
`UniversalSerial
`Bus and port.
`
`Ex. 2025, pp. 1.
`
`17
`
`Exhibit 2023 - Page 17 of 18
`
`
`
`Cypress’EZ -USB FX: Th e EZ -USB FX ch ip is a com pactIC
`th atprovides a h igh ly integrated solution for a USB periph eral
`device.
`
`Ex. 2032, pp. 29 (docum entpage 1-1).
`
`A USB periph eraldevice can attach to a h ostcom puter th rough a
`USB bus and connector (e.g., h aving pins D+ and D–).
`
`Ex. 2032, pp. 30 (docum entpage 1-2).
`
`Ex. 2032, pp. 33 (docum entpage 1-5).
`
`18
`
`Exhibit 2023 - Page 18 of 18
`
`
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