Claim Ch artfor U.S. PatentNo. 6,012,103
`
`Th is claim ch artm aps som e ofth e claim s ofU.S. PatentNo. 6,012,103 (‘103
`patent)to Anch or Ch ips’EZ -USB product(e.g., partno. AN2131xx)and to
`Cypress’EZ -USB FX product(e.g., partno. CY7C646xx).
`
`Anch or Ch ips’EZ -USB: Th e EZ -USB integrated circuit
`(IC)is configured to perform a m eth od for reconfiguring a
`USB periph eraldevice th atis connected to h ostcom puter. For
`exam ple, th e EZ -USB IC is a solution for h igh -speed USB
`periph eraldevices (i.e., USB periph erals)th atare attach ed to a
`h ostPC th rough a USB port.
`
`CLAIM 14
`14. A m eth od
`for
`reconfiguring a
`periph eral
`device
`connected by a
`com puter bus
`and portto a
`h ostcom puter,
`th e m eth od
`com prising th e
`steps of:
`
`Ex. 2025, pp. 2.
`
`1
`
`Exhibit 2022 - Page 01 of 22
`
`
`
`Th is claim ch artm aps som e ofth e claim s ofU.S. PatentNo. 6,012,103 (‘103
`patent)to Anch or Ch ips’EZ -USB product(e.g., partno. AN2131xx)and to
`Cypress’EZ -USB FX product(e.g., partno. CY7C646xx).
`
`Anch or Ch ips’EZ -USB: Th e EZ -USB integrated circuit
`(IC)is configured to perform a m eth od for reconfiguring a
`USB periph eraldevice th atis connected to h ostcom puter. For
`exam ple, th e EZ -USB IC is a solution for h igh -speed USB
`periph eraldevices (i.e., USB periph erals)th atare attach ed to a
`h ostPC th rough a USB port.
`
`CLAIM 14
`14. A m eth od
`for
`reconfiguring a
`periph eral
`device
`connected by a
`com puter bus
`and portto a
`h ostcom puter,
`th e m eth od
`com prising th e
`steps of:
`
`Ex. 2025, pp. 2.
`
`1
`
`Exhibit 2022 - Page 01 of 22
`
`
`
`Ex. 2025, pp. 4.
`
`Cypress’EZ -USB FX: Th e EZ -USB FX IC is configured to
`perform a m eth od for reconfiguring a USB periph eraldevice
`th atis connected to h ostcom puter. Th e EZ -USB FX ch ip is a
`com pactIC th atprovides a h igh ly integrated solution for a
`USB periph eraldevice.
`
`Ex. 2032, pp. 29 (docum entpage 1-1).
`
`A USB periph eraldevice can attach to a h ostcom puter
`th rough a USB bus and connector (e.g., h aving pins D+ and
`D–).
`
`2
`
`Exhibit 2022 - Page 02 of 22
`
`
`
`Ex. 2032, pp. 30 (docum entpage 1-2).
`
`Ex. 2032, pp. 33 (docum entpage 1-5).
`
`Anch or Ch ips’EZ -USB: A h ostPC includes one or m ore
`circuits configured to detectconnection ofth e USB periph eral
`w ith th e EZ -USB IC to th e h ostPC over th e USB bus. Se e
`e.g., Ex. 1013 (USB 1.0 Spec), Sections 7.1.3, 7.1.4.1, 9 .1.2.
`
`Th e USB periph eralw ith th e EZ -USB IC h as an initial
`configuration upon start-up.
`
`detecting th e
`periph eral
`device
`connected to
`th e port,
`w h erein th e
`periph eral
`device h as a
`first
`configuration;
`
`Ex. 2025, p. 5.
`
`3
`
`Exhibit 2022 - Page 03 of 22
`
`
`
`Cypress’EZ -USB FX: A h ostcom puter includes one or
`m ore circuits configured to detectconnection ofth e USB
`periph eralw ith th e EZ -USB FX IC to th e h ostcom puter over
`th e USB bus. Se e e.g., Ex. 1013 (USB 1.0 Spec), Sections
`7.1.3, 7.1.4.1, 9 .1.2.
`
`Th e USB periph eraldevice w ith th e EZ -USB FX IC h as an
`initialconfiguration (e.g., upon pow er-on).
`
`Ex. 2032, pp. 85 (docum entpage 5-1).
`
`Anch or Ch ips’EZ -USB: Th e EZ -USB IC includes one or
`m ore circuits to dow nload inform ation for a second
`configuration from th e h ostPC into th e USB periph eralover
`th e USB bus. For exam ple, in th e figure below , th e Anch or
`Sm artUSB Engine Core is coupled to th e USB bus (w h ich
`includes th e D+ and D- lines)and includes one or m ore
`circuits to dow nload inform ation from th e h ostPC.
`
`dow nloading a
`second setof
`configuration
`inform ation
`from th e h ost
`com puter into
`th e periph eral
`device over th e
`com puter bus;
`and
`
`4
`
`Exhibit 2022 - Page 04 of 22
`
`
`
`Ex. 2025, pp. 1.
`
`Th e circuits connected to th e USB bus are configured to
`dow nload second configuration inform ation from th e h ostPC
`to th e USB periph eralover th e USB bus.
`
`Ex. 2025, pp. 5.
`
`Cypress’EZ -USB FX: Th e EZ -USB FX IC includes one or
`m ore circuits to dow nload inform ation for a second
`configuration from th e h ostcom puter into th e USB periph eral
`over th e USB bus. For exam ple, in th e figure below , th e
`SerialInterface Engine (SIE)is coupled to th e USB bus over a
`
`5
`
`Exhibit 2022 - Page 05 of 22
`
`
`
`USB connector and includes one or m ore circuits to dow nload
`inform ation from th e h ostcom puter.
`
`Ex. 2032, pp. 30 (docum entpage 1-2).
`
`Anch or Ch ips’EZ -USB: Th e EZ -USB IC includes one or
`m ore circuits to electronically sim ulate a ph ysical
`disconnection and reconnection ofth e periph eraldevice over
`th e USB bus. For exam ple, in th e figure below , th e Anch or
`Sm artUSB Engine Core includes one or m ore circuits to
`sim ulate a ph ysicaldisconnection and reconnection after th e
`second configuration is dow nloaded in RAM .
`
`electronically
`sim ulating a
`ph ysical
`disconnection
`and
`reconnection of
`th e periph eral
`device to
`reconfigure th e
`periph eral
`device to a
`second
`configuration
`based on th e
`
`6
`
`Exhibit 2022 - Page 06 of 22
`
`
`
`second setof
`configuration
`inform ation.
`
`Ex. 2025, p. 1.
`
`Th e EZ -USB IC’s USB Engine Core sim ulates a ph ysical
`disconnectand re-connectand th e h ostPC recognizes
`attach m entofth e new USB periph eraldevice w ith th e updated
`second configuration.
`
`Ex. 2025, p. 5.
`
`Cypress’EZ -USB FX: Th e EZ -USB FX IC includes one or
`m ore circuits to electronically sim ulate a ph ysical
`disconnection and reconnection ofth e periph eraldevice over
`th e USB bus. For exam ple, in th e figure below , th e SIE
`includes one or m ore circuits to sim ulate a ph ysical
`disconnection and reconnection after th e second configuration
`is dow nloaded in RAM .
`
`7
`
`Exhibit 2022 - Page 07 of 22
`
`
`
`Ex. 2032, pp. 30 (docum entpage 1-2).
`
`Ex. 2032, pp. 85 (docum entpage 5-1).
`
`M ore specifically, th ree EZ -USB FX controlbits in th e
`USBCS (USB Controland Status)Register controlth e
`ReNum eration™ process: DISCO N, DISCO E, and RENUM .
`To sim ulate a USB disconnect, th e 8051 (m icroprocessor)
`w rites a specific value to th e USBCS Register. To re-connect
`to th e USB, th e 8051 w rites anoth er specific value to th e
`USBCS Register. A typicaldisconnect/reconnectcircuitis
`illustrated in th e figure below .
`
`8
`
`Exhibit 2022 - Page 08 of 22
`
`
`
`
`
`
`5.10 ReNumeration 7’"
`
`
`
`Three EZ—USB FX control bits in the USBCS {USE Control and Status} Register control the ReNu—
`merationTM process: DISCON, DISCUE. and RENUM.
`
`The logic for the DISCON and DISCDE bits is shown in Figure 5—3. To simulate a USB disconnect,
`the B051 writes the value 00001010 to USBCS. This floats the DISCOhltil pin, and provides an
`intemal DISCONI‘I signal to the USB core that causes it to perform disconnect housekeeping.
`
`To re{onnect to USB, the 3051 writes the value 00000110 to USECS. This presents a logic HII to
`the DISCON# pin, enables the output buffer, and sets the RENUM bit HI to indicate that the 0051
`(and not the USB core) is now in control for USB transfers. This arrangement allows connecting
`the 1,5000hm resistor directlyr between the DlSCONt‘t pin and the USB D+ line {Figure 5—4}.
`
`
`
`
`
`Figure 54. Typical Disconnect Circuit
`
`Ex. 2032, pp. 9 5-9 6 (docum entpages 5-11, 5-12).
`
`EX. 2032, pp. 95-96 (document pages 5-11, 5-12).
`
`9
`
`Exhibit 2022 - Page 09 of 22
`
`Exhibit 2022 - Page 09 of 22
`
`
`
`CLAIM 19
`19 . Th e
`m eth od of
`claim 14,
`w h erein
`dow nloading
`com prises
`com m unicating
`said second set
`of
`configuration
`inform ation to
`th e periph eral
`device using a
`universalserial
`bus and port.
`
`See Claim 14 generally for discussion ofth e UniversalSerial
`Bus and port.
`
`Anch or Ch ips’EZ -USB: Th e EZ -USB Integrated Circuit
`(IC)is a single-ch ip low -pow er solution for USB periph erals.
`
`Ex. 2025, pp. 1.
`
`Th e USB periph eral(w ith th e EZ -USB IC)is attach ed to th e
`h ostPC th rough a USB port.
`
`Ex. 2025, pp. 2.
`
`Cypress’EZ -USB FX: Th e EZ -USB FX ch ip is a com pact
`IC th atprovides a h igh ly integrated solution for a USB
`periph eraldevice.
`
`Ex. 2032, pp. 29 (docum entpage 1-1).
`
`10
`
`Exhibit 2022 - Page 10 of 22
`
`
`
`A USB periph eraldevice can attach to a h ostcom puter
`th rough a USB bus and connector (e.g., h aving pins D+ and
`D–).
`
`Ex. 2032, pp. 30 (docum entpage 1-2).
`
`Ex. 2032, pp. 33 (docum entpage 1-5).
`
`11
`
`Exhibit 2022 - Page 11 of 22
`
`
`
`Anch or Ch ips’EZ -USB: Th e EZ -USB IC is a solution for
`h igh -speed USB periph eraldevices (i.e., USB periph erals)th at
`are attach able over a USB bus th rough a USB port.
`
`CLAIM 24
`24. A
`periph eral
`interface device
`for a com puter
`periph eralbus
`and port,
`com prising:
`
`Ex. 2025, pp. 2.
`
`Cypress’EZ -USB FX: Th e EZ -USB FX ch ip is a com pact
`IC th atprovides a h igh ly integrated solution for a USB
`periph eraldevice.
`
`Ex. 2032, pp. 29 (docum entpage 1-1).
`
`A USB periph eraldevice can attach to a h ostcom puter over a
`USB bus and connector (e.g., h aving pins D+ and D–).
`
`12
`
`Exhibit 2022 - Page 12 of 22
`
`
`
`Ex. 2032, pp. 30 (docum entpage 1-2).
`
`Anch or Ch ips’EZ -USB: Th e EZ -USB IC includes one or
`m ore circuits configured to connectth e USB periph eralto th e
`h ostPC over th e USB bus. For exam ple, in th e figure below ,
`th e USB XCVR circuitis configured to connectth e USB
`periph eralto th e h ostPC over th e USB bus (w h ich includes
`th e D+ and D- lines).
`
`m eans for
`ph ysically
`connecting a
`periph eral
`device to a
`com puter
`system th rough
`th e com puter
`periph eralbus,
`w h erein th e
`periph eral
`device h as a
`first
`configuration;
`
`Ex. 2025, pp. 1.
`
`13
`
`Exhibit 2022 - Page 13 of 22
`
`
`
`Ex. 2025, pp. 4.
`
`Th e USB periph eralw ith th e EZ -USB IC h as an initial
`configuration upon start-up.
`
`Ex. 2025, p. 5.
`
`Cypress’EZ -USB FX: Th e EZ -USB FX IC includes one or
`m ore circuits configured to connectth e USB periph eralto th e
`h ostcom puter over th e USB bus. For exam ple, in th e figure
`below , th e USB Transceiver circuitis configured to connect
`th e USB periph eralto th e h ostcom puter over th e USB bus.
`
`14
`
`Exhibit 2022 - Page 14 of 22
`
`
`
`Ex. 2032, pp. 30 (docum entpage 1-2).
`
`Ex. 2032, pp. 33 (docum entpage 1-5).
`
`Th e USB periph eraldevice w ith th e EZ -USB FX IC h as an
`initialconfiguration (e.g., upon pow er-on).
`
`Ex. 2032, pp. 85 (docum entpage 5-1).
`
`m eans for
`receiving a
`second setof
`
`Anch or Ch ips’EZ -USB: Th e EZ -USB IC includes one or
`m ore circuits configured to receive a second configuration
`from th e h ostPC into th e USB periph eralover th e USB bus.
`
`15
`
`Exhibit 2022 - Page 15 of 22
`
`
`
`For exam ple, in th e figure below , th e Anch or Sm artUSB
`Engine Core is coupled to th e USB bus (w h ich includes th e
`D+ and D- lines)and includes one or m ore circuits configured
`to receive inform ation from th e h ostPC.
`
`configuration
`inform ation
`from a
`com puter
`system over th e
`com puter
`periph eralbus
`and port;and
`
`Ex. 2025, pp. 1.
`
`Th e circuits connected to th e USB bus are configured to
`receive second configuration inform ation from th e h ostPC to
`th e USB periph eralover th e USB bus.
`
`Ex. 2025, pp. 5.
`
`16
`
`Exhibit 2022 - Page 16 of 22
`
`
`
`Cypress’EZ -USB FX: Th e EZ -USB FX IC includes one or
`m ore circuits configured to receive a second configuration
`from th e h ostcom puter into th e USB periph eralover th e USB
`bus. For exam ple, in th e figure below , th e SerialInterface
`Engine (SIE)is coupled to th e USB bus over a USB connector
`and includes one or m ore circuits configured to receive th e
`second configuration from th e h ostcom puter.
`
`Ex. 2032, pp. 30 (docum entpage 1-2).
`
`Anch or Ch ips’EZ -USB: Th e EZ -USB IC includes one or
`m ore circuits to electronically sim ulate a ph ysical
`disconnection and reconnection ofth e periph eraldevice over
`th e USB bus. For exam ple, in th e figure below , th e Anch or
`Sm artUSB Engine Core includes one or m ore circuits
`configured to sim ulate a ph ysicaldisconnection and
`reconnection after th e second configuration is dow nloaded in
`RAM .
`
`m eans for
`electronically
`sim ulating a
`ph ysical
`disconnection
`and
`reconnection of
`th e periph eral
`device to
`reconfigure th e
`
`17
`
`Exhibit 2022 - Page 17 of 22
`
`
`
`periph eral
`device to a
`second
`configuration
`based on th e
`second setof
`configuration
`inform ation.
`
`Ex. 2025, p. 1.
`
`Th e EZ -USB IC’s USB Engine Core sim ulates a ph ysical
`disconnectand re-connectand th e h ostPC recognizes
`attach m entofth e new USB periph eraldevice w ith th e updated
`second configuration.
`
`Ex. 2025, p. 5.
`
`Cypress’EZ -USB FX: Th e EZ -USB FX IC includes one or
`m ore circuits to electronically sim ulate a ph ysical
`disconnection and reconnection ofth e periph eraldevice over
`th e USB bus. For exam ple, in th e figure below , th e SIE
`includes one or m ore circuits configured to sim ulate a ph ysical
`disconnection and reconnection after th e second configuration
`is dow nloaded in RAM .
`
`18
`
`Exhibit 2022 - Page 18 of 22
`
`
`
`Ex. 2032, pp. 30 (docum entpage 1-2).
`
`Ex. 2032, pp. 85 (docum entpage 5-1).
`
`M ore specifically, th ree EZ -USB FX controlbits in th e
`USBCS (USB Controland Status)Register controlth e
`ReNum eration™ process: DISCO N, DISCO E, and RENUM .
`To sim ulate a USB disconnect, th e 8051 (m icroprocessor)
`w rites a specific value to th e USBCS Register. To re-connect
`to th e USB, th e 8051 w rites anoth er specific value to th e
`USBCS Register. A typicaldisconnect/reconnectcircuitis
`illustrated in th e figure below .
`
`19
`
`Exhibit 2022 - Page 19 of 22
`
`
`
`
`
`5. 10 ReNumerarion T“
`
`
`
`Three EZ-USB FX control bits in the USBCS {USB Control and Status} Register control the ReNu-
`n"rerat]'on"'ll process: DISCON. DISCOE, and RENUM.
`
`The logic for the DISCON and DISCOE bits is shown in Figure 5—3. To simulate a USB disconnect,
`the 8051 writes the value 00001010 to USBCS. This floats the DISCONtr pin, and provides an
`inlemal DISCON=1 signal to the USE core that causes it to perform disconnect housekeeping.
`
`To re—connect to USB, the 0051 writes the value 00100110 to USBCS. This presents a logic HII to
`the DISCON# pin, enables the output buffer, and sets the RENUM b'rt Hl to indicate that the 0051
`(and not the USB core) is now in control for USB transfers. This arrangement allows connecting
`the 1,500—ohm resistor directly between the DISCON# pin and the USB D+1ine (Figure 5—4).
`
`DISCOM
`
`1500
`
`
`
`EZ—U88
`%
`
`.31}Liam— E‘'P
`
`Figure 5—4. Typical Disconnect Circuit
`
`Ex. 2032, pp. 9 5-9 6 (docum entpages 5-11, 5-12).
`
`EX. 2032, pp. 95-96 (document pages 5-11, 5-12).
`
`20
`20
`
`Exhibit 2022 - Page 20 of 22
`
`Exhibit 2022 - Page 20 of 22
`
`
`
`CLAIM 27
`27. Th e device
`ofclaim 26,
`w h erein said
`com puter
`periph eralbus
`and port
`com prise a
`universalserial
`bus and port.
`
`Anch or Ch ips’EZ -USB: Th e EZ -USB Integrated Circuit
`(IC)is a single-ch ip low -pow er solution for USB periph erals.
`
`Ex. 2025, pp. 1.
`
`Th e USB periph eral(w ith th e EZ -USB IC)is attach ed to th e
`h ostPC th rough a USB port.
`
`Ex. 2025, pp. 2.
`
`Cypress’EZ -USB FX: Th e EZ -USB FX ch ip is a com pact
`IC th atprovides a h igh ly integrated solution for a USB
`periph eraldevice.
`
`Ex. 2032, pp. 29 (docum entpage 1-1).
`
`A USB periph eraldevice can attach to a h ostcom puter
`
`21
`
`Exhibit 2022 - Page 21 of 22
`
`
`
`th rough a USB bus and connector (e.g., h aving pins D+ and
`D–).
`
`Ex. 2032, pp. 30 (docum entpage 1-2).
`
`Ex. 2032, pp. 33 (docum entpage 1-5).
`
`22
`
`Exhibit 2022 - Page 22 of 22
`
`
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