_
`
`Objectlve
`
`_
`
`Summary of
`Qualifications
`
`8711 NW Benson SI.
`Portland. OR 97229
`Home (503)-291-1587
`Email: mnsulling©garneysooml
`
`'
`
`John Garney
`
`\
`
`1
`1
`
`To provide critical computer hardware and software expertise to successfully resolve
`
`intellectual property proceedings.
`
`Demonstrated strong broad and deep individual contributor skills in: computer system
`new technology architecture definition, analysis and specification; cross business group
`
`Proven ability to derive specific technical
`communication and group leadership.
`requirements from vague problem areas and work in broad PC industry environments to
`stimulate deployment of new technologies (e.g. PCMCIA, CardBus, Plug&Play, Power
`Management, Universal Serial Bus 1.0, 2.0, 3.0 & 3.1). Consistently recognized by
`peers and managers for my ability to rapidly assimilate and master new technical areas
`and then become acknowledged as a key leader
`in driving additional
`technical
`progress. Widely respected for ability to generate, articulate, and critically analyze:
`technical proposals, concepts and specifications. Extensive hands-on experience with
`prototyping/debugging/analysis of hardware/firmware/software. 27+ years experience
`in various research and development assignments in the PC industry. Provided expert
`witness services to 6 clients, to date; all have settled out of court.
`
`Work experieqqer#
`
`Portland, OR
`Garney Consulting, L.L.C.
`2007 — Present
`System Architect (consulting/expert—witness services to client companies)
`
`I Vice-Chair of USB 3.0 10G Hub Working Group. Member of other USB 3.0 10G
`Working Groups and extensive reviewer of drafts in progress.
`
`I Major technical contributor to USBIF UASP Device Class Working Group compliance
`test definitions.
`
`l Intensive debugging of reliability problems and workarounds for USB 2.0 Hub in
`consumer home network product that successfully resolved customer release problems.
`
`I Support USB-IF Peripheral Integration Lab testing of customer products using client
`company USB software stack. Usually requires analysis of operational failures and USB
`specification requirements to determine required corrective action in either/both customer
`or client company software/hardware.
`
`I USB 3.0, xHCI & UASP (USB Attached SCSI Protocol) embedded product
`architectures: Detailed analysis/review of USB 3.0 SuperSpeed Stream protocol and state
`machines resulted in numerous clarifications in Errata. Review of xHCI specification and
`listed as a contributor
`in the published Intel document. Client company advisory
`representative to ANSI T10/CAP/UAS working group and USB-IF UASP working group.
`Member of USB-IF Mass Storage, OTG2, OTG3 and AV working groups.
`
`I Wireless USB projects: Refined overall WUSB embedded system device and host
`architectures extending existing client products. Work involved several on-site,
`international, three-way customer,
`in-depth technical discussions. Defined embedded
`system (cell phone appropriate) Cable Association Method (CAM) protocol interfaces for
`host and device side, supporting Wireless USB CAM requirements. Proposed embedded
`system device-side Numeric Association Method (NAM) protocol interfaces. Drove key
`requirements into definition of radio controller interface. Defined cryptographic product
`
`EXHIBIT 2021
`
`LG Elecs. V. Cypress Semiconductor
`
`IPR2014—01405, US. Pat. 6,493,770
`
`Exhibit 2021 - Page 01 of 08
`
`Exhibit 2021 - Page 01 of 08
`
`

`

`requirements for host and device in support of WUSB and WiMedia functionality suitable
`for RFQ technical details.
`Client company representative to WiMedia Embedded
`Controller Interface and WiMedia Association Method Workgroups.
`
`l Reviewer of USB 3.0 draft specifications.
`
`l Delivered 2 3-day USB 2.0 Training Workshops (Germany, Nonrvay) providing in-depth
`material on core aspects of USB 2.0. Included hand's—on USB bus trace analysis of actual
`USB products.
`
`I Provided expert witness services for several USB patent infringement cases in the US
`and UK; involving storage, configuration and other USB technologies. Analyzed patents
`and wrote expert report on plaintiff claims. Cases were settled out of court before going to
`deposition or trial.
`
`1989 - 2007
`
`Intel CorporationHillsboro, OR
`
`Sr. Staff Software Architect, Corporate Technology Group 8- Intel
`Architecture Labs
`
`A variety of technology Research & Development assignments from 1-3 years
`duration each. Many required Microsoft interactions to achieve broad PC industry
`acceptance.
`
`l System architect for cross platform (handheld/mobile, desktop, server) exploration
`expanding on virtualization/partitioning advanced technologies.
`Established design
`directions for provisioning, chain-of-trust,
`isolation and communication mechanisms in
`investigations of possible future IA32 platforms. Made proposals to CPU and chipset
`architects for new instructions and silicon inter process/processor communication features
`in support of this overall technology. Provided technical leadership/direction to many other
`engineers on the team in US and India.
`
`I Software project lead for new high density, non-volatile, silicon storage technology
`development. Responsible for overall software architecture definition of a disk caching
`subsystem (extension of Intel Application Accelerator 3.5) including HW programming
`interface definition. Oversaw demos delivered to ESM and other VPs. Acting project
`manager of 4 person geographically distributed team until
`fulltime manager hired.
`Developed analytic model to estimate silicon area requirements. Eventually deployed as
`Intel Robson disk cache/storage technology and current Intel SSDs.
`
`Intel technical lead/chair for protocol, hub and other non-
`l Universal Serial Bus 2.0:
`electrical definitions. Proposed, defined and drove ratification of transaction translator
`(core element of USB2.0 Hubs) in international, cross company working group. Engaged
`with Intel Desktop Products Group to define Enhanced Host Controller Interface product
`specification with other junior engineers. USB2.0 received PC Magazine Best New
`Technology award.
`Received Intel Achievement Award 2003 for USB.
`Stable
`specification broadly adopted in PC industry.
`
`Proposed and defined advanced features in
`I Isochronous Data Platform Support:
`chipset hardware for higher quality, lower cost streaming data support (video, audio, etc.).
`Engaged with Desktop Products Group Sr. Architects for future chipset product plans.
`
`I 3D Graphics: Developed detailed analytic model of Microsoft Talisman architecture for
`non-DSP implementation of chunk based 3D rendering with on-the-fly sprite compositing.
`Defined basic driver framework pursued by software team and contributed to key
`decisions related to hardware performance implementation choices. Efforts contributed to
`Intel suspending their involvement in developing this technology. Assignment included
`achieving Microsoft acceptance of Intel’s contributions and requirements in the published
`P098 3D Graphics chapter (as chapter editor).
`
`Exhibit 2021 - Page 02 of 08
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`Exhibit 2021 - Page 02 of 08
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`

`

`I Universal Serial Bus 1.0: Intel technical lead for V1.0 Specification creation, adoption
`and USB core team interactions. Wrote core system architecture chapter (5), coordinated
`other chapters and delivered many presentations/tutorials at other companies and
`industry events
`(WinHEC,
`Intel, Telephony Conferences). Specification
`stability
`contributed to mass market availability in less than 3 years from initial specification.
`Extensive hands-on technical leadership during prototype/debug/certification of eariy USB
`products by Intel and other USB vendors.
`
`I Plug and Play, Power Management: Extensive work with Microsoft technical experts to
`define OS architecture for enhanced functionality. Member of Microsoft team and
`recognized by Microsoft VP as being significant contributor to definition of Plug and Play
`for Window595.
`
`l Intel's PCMCIA software representative: extensively reviewed PCMCIA pre-2.0, co-
`defined software interfaces (Card and Socket Services, 200+ pages) sections of PCMCIA
`2.01 (November 1992) and 2.1 (July 1993), wrote Intel compatible subset definition that
`was subsequently adopted by PC industry (ExCA) for dependable card interchange,
`managed team that enhanced 16 bit definition to 32 bit PCI related extension (CardBus).
`Specification stability and accurate understanding of other industry players contributed to
`enrolling Microsoft as active supporter vs. detractor. Software architect for 2 Intel HW
`product teams building 2 different PCMCIA host adapters, both incorporated in 3rd party
`laptops.
`Demonstrated PCMCIA Execute-in-Place (XIP) prototype tools/driver for
`converting commonly available Windows 3.x applications (such as MS Word and
`Powerpoint) and executing them directly from a flash memory card (without requiring copy
`to DRAM).
`
`1988 - 1989
`
`BiiN CorporationHillsboro, OR
`
`Staff Software Architect] Project Leader
`
`l Responsible for fault tolerance(FT) software design of BiiN/OS and member of security
`design team. Specified and designed overall system architecture for hardware/software
`FT including: online module
`replacement, dynamic selection of FT level and
`detection/recovery of hardware/software subsystem failures. Integrated/debugged core
`08 software with novel fine-grained protection domain, capability based hardware.
`Developed method for function inheritance support for a strongly typed, hardware
`enforced (i960XA) abstract
`type manager environment.
`Involved in design of OS
`enhancements to pursue NCSC B2 Security Rating. Project leader and indirectly provided
`leadership for many other developers. Working FT functionality was in alpha test phase at
`termination of company. BiiN was a joint venture spun off by Intel/Siemens that provided a
`“golden parachute” retum to Intel upon its demise.
`
`1980 - 1988
`
`Intel CorporationHillsboro, OR
`
`Software Architect! Project Leader
`
`l Steadily advanced through variety of assignments in software evaluation of several
`operating
`systems
`(iRMX 80/88/86,
`iMAX/432)
`and
`then 08 subsystem
`design/development
`(overall
`IO architecture,
`initialization/
`shutdown,
`dynamic
`reconfiguration of BiiN/OS). Also established software development methodologies and
`reference drivers for use by other team members. Recognized as key technical leader for
`all OS driver development.
`
`Various years
`
`Personal Projects
`
`Exhibit 2021 - Page 03 of 08
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`Exhibit 2021 - Page 03 of 08
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`

`

`Various projects for home automation involving hardware/circuit design, PCB layout,
`firmware and software design/development and integration testing.
`
`I Reverse engineered Litetouch 2000 low voltage residential lighting control protocol and
`designed/ implemented Scenix 8X28 microcontroller hardware/firmware protocol module
`that converted between RS232 serial commands/events and Litetouch proprietary
`protocol.
`
`l Reverse engineered Kustom whole house audio wall control protocol and designed/
`implemented Scenix 8X28 microcontroller hardware/firmware protocol module that
`converted between RS232 serial commands and Kustom wall control protocol.
`
`I Designed/built ultra low power, battery powered, wireless radio sensor modules using
`PlC12F6xx microcontrollers for sensing light, contact closure and temperature. Custom
`radio protocol designed including support for detection of missed reports and current
`battery level. Designed Rabbit 2000 ethemet connected based radio receiver. Used to
`detect: water heater pilot light vs. main burner lit, mousetrap trigger, day/night, and room
`temperatures. 16 sensors deployed with rolling 3 year readings logged and displayed via
`web interface.
`
`I Designed/built Rabbit 2000 microcontroller based, 2x40 character VFD ethemet
`connected general purpose display console. Used to display time/date and various
`household/weather status indications.
`
`Education
`
`1978 - 1980
`
`Purdue UniversityWest Lafayette, IN
`
`M.S. Computer Science
`
`1975 - 1978
`
`Purdue UniversityWest Lafayette, IN
`
`3.3. Computer Science & B.S. Mathematics
`
`References
`
`Available upon request
`
`Patents,
`Publications and
`
`Presentations _ _
`
`62 patents granted; 12+ as solo inventor; usually the lead inventor for all patents.
`Approximately 12 patents pending.
`Patents are in a variety of computer system areas including: operating system device
`drivers, BIOS, 3D graphics, serial buses (such as USB), disk caches, memory buses.
`For example, Device driver configuration in a computer system (1994), System for
`copying device driver stub in allocated portion of system memory corresponding to
`receiving resource to enable device driver execution from resource memory (1995),
`Preservation of a computer system processing state in a mass storage device (1995),
`System for enabling access to device driver residing in resource memory corresponding
`to coupled resource by allowing memory mapping to device driver to be executed
`(1995), Method and apparatus for executing applications in place from write
`once/seldom memories (1996).
`
`Involved in several Patent Trademark Office (PTO) Office Actions to resolve questions
`pertaining to pending patent applications. Frequently asked to review patents from other
`inventions to clarify novelty of a pending patent. On one occasion, flown to Wash. DC. to
`meet directly with patent examiner to expedite patent application.
`
`Full patent list available on request.
`
`Jan-Mar 2000: 05350 Adjunct Professor at Portland State University
`
`Exhibit 2021 - Page 04 of 08
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`Exhibit 2021 - Page 04 of 08
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`

`

`Taught Winter Term 08350 Course
`
`Catalogue Description: Techniques for the design and analysis of algorithms. Problem
`solving. Case studies of existing algorithms (sorting, searching, graph algorithms, dynamic
`programming, string matching). NP-completeness.
`Prerequisites: CS 252
`Goals: To develop a group of useful algorithms which can be used to solve
`common problems. The development of tools and principles for analyzing the time, space,
`and correctness used by these algorithms.
`
`1997-1999: Co-developed and taught several 2-day USB 1.0 workshops
`
`Co-developed 2-day class material on Universal Serial Bus 1.0 and taught many 10-40
`person classes over 1+ years. Some classes taught internationally.
`
`1998: Lead Co-author of “USB Hardware and Software” Book
`
`Technical reference book "USB Hardware and Software” (ISBN 0-929392—37-X) written with
`4 other authors and published in 1998. Also available in Japanese translation. Wrote
`chapters 1, 3, 7 & 8. Coordinated book review and assembly.
`
`2000: USB 2.0 Hub Working Group chairperson/editor/technical-lead
`
`Hub working group chairperson/editor for Universal Serial Bus (USB) Technical Specification
`Revision 2.0. Responsible for driving technical details/solutions for all non-electrical areas of
`USB 2.0. Defined, designed, proposed, defended and wrote almost all high speed details in
`Chapter 5 (USB Data Flow Model), Chapter 8 (Protocol Layer), Chapter 11.14-11.22 (Hub
`Transaction Translator).
`Inventor of transaction translator extension to USB hubs (a central
`element of USB 2.0). Only minor errata has been released for the specification since its
`publication in April 2000.
`
`Spoke at international conferences with simultaneous translation (Taiwan and Japan)
`
`USB Developers Conferences, WinHEC conferences (on USB, Power Management and
`Plug and Play).
`
`Intel Software Developer's Conference 1996, 1997 papers.
`
`Awards received __
`
`Intel Achievement Award 2003 (USBZ.0), Intel Architecture Labs Divisional Award, Intel
`Software Developer’s Conference: Best Paper, several Business Group Recognition
`Awards. USB Developers Conference: Best Speaker.
`
`Keywords: Operating Systems, USB, PCMCIA, PCCard, Fault Tolerance. Hot plug, disk
`cache, 3D graphics, power management.
`
`Exhibit 2021 - Page 05 of 08
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`Exhibit 2021 - Page 05 of 08
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`

`

`Patent Information for John Carney:
`(Most patents assigned to Intel Corporation, dates below should be grant dates)
`
`Patents Granted:
`
`1.
`
`2.
`
`(6/7/94) 5,319,751: Device driver configuration in a computer system
`
`(1/31/95) 5,386,552: Preservation of a computer system processing state in a mass
`storage device
`
`(4/4/95) 5,404,494: System for copying device driver stub into allocated portion
`of system memory corresponding to receiving resource to enable device driver
`execution from resource memory
`
`(5/2/95) 5,412,798: System for enabling access to device driver residing in
`
`resource memory corresponding to coupled resource by allowing memory
`mapping to device driver to be executed
`
`(7/23/96) 5,538,436: Two—part memory card socket connector and related
`
`interrupt handler
`
`(12/3/96) 5,581,768: Method and apparatus for executing applications in place
`from write once/seldom memories
`
`(10/13/98) 5,822,784: Mechanism supporting execute in place read only memory
`applications located on removable computer cards
`(12/29/98) 5,854,905: Extensible BIOS for boot support of devices on multiple
`hierarchical buses
`
`(3/30/99) 5,890,015: Method and apparatus for implementing wireless universal
`
`serial bus host controller by interfacing a universal serial bus hub as a universal
`bus device
`
`(6/27/00) 6,081,850: Storing dynamically loaded device drivers on a mass storage
`device to support access to removable computer cards
`
`(8/8/00) 6,101,613: Architecture providing isochronous access to memory in a
`system
`
`(9/12/00) 6,119,190: Method to reduce system bus load due to USB bandwidth
`reclamation
`
`(9/12/00) 6,119,243: Architecture for the isochronous transfer of information
`
`within a computer system
`
`(2/20/01) 6,192,380: Automatic web based form fill-in
`
`(7/10/01) 6,260,119: Memory cache management for isochronous memory access
`
`(2/19/02) 6,349,354: Method to reduce system bus load due to USB bandwidth
`reclamation
`'
`
`(2/26/02) 6,351,783: Method and apparatus for isochronous data transport over an
`
`asynchronous bus
`
`(5/14/02) 6,389,501: I/O peripheral device for use in a store-and-forward segment
`
`of a peripheral bus
`
`(6/25/02) 6,412,049: Method for minimizing CPU memory latency while
`
`transferring streaming data
`
`(7/9/02) 6,418,538: Method and system for scheduling transactions over a half
`
`10.
`
`11.
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`12.
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`13.
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`14.
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`15.
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`16.
`
`17.
`
`18.
`
`19.
`
`20.
`
`duplex link
`
`Exhibit 2021 - Page 06 of 08
`
`Exhibit 2021 - Page 06 of 08
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`

`

`21.
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`22.
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`23.
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`24.
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`25.
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`26.
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`27.
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`28.
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`29.
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`30.
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`31.
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`32.
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`33.
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`34.
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`35.
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`36.
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`37.
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`38.
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`39.
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`40.
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`41.
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`42.
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`43.
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`44.
`
`(1 1/5/02) 6,477,600: Apparatus and method for processing isochronous interrupts
`
`(l 1/ 19/02) 6,484,201: Method and apparatus to test an isochronous data transport
`
`(4/8/03) 6,546,018: Digital system having a peripheral bus structure with at least
`one store-and—forward segment
`(9/30/03) 6,629,186: Bus controller and associated device drivers for use to
`control a peripheral bus having at least one store-and-forward segment
`
`(10/7/03) 6,630,931: Generation of stereoscopic displays using image
`
`approximation
`(1/ 13/04) 6,678,761: Method and apparatus for budget development under
`universal serial bus protocol in a multiple speed transmission environment
`(4/27/04) 6,728,801: Method and apparatus for period promotion avoidance for
`hubs
`
`(8/3/04) 6,771,664: Transaction scheduling for a bus system in a multiple speed
`environment
`
`(8/24/04) 6,782,484: Method and apparatus for lossless resume capability with
`
`peripheral devices
`(9/ 14/04) 6,792,495: Transaction scheduling for a bus system
`
`(11/2/04) 6,813,251 & 7,675,871 (3/9/10) & 7,886,087 (2/8/11) & 8,677,032 B2
`(3/18/14): Split transaction protocol for a bus system
`(4/26/05) 6,886,062: Method and apparatus for improving time constraints and
`
`extending limited length cables in a multiple-speed bus
`
`(5/3/05) 6,889,265: Apparatus and method to allow and synchronize schedule
`
`changes in a USB enhanced host controller
`(7/ 19/05) 6,920,533: System boot time reduction method
`
`(8/2/05) 6,925 ,015: Stacked memory device having shared bitlines and method
`
`making the same
`(10/4/05) 6,952,429: Transaction scheduling for a bus system in a multiple speed
`environment
`
`(2/28/06) 7,007,110: NAK throttling for USB host controllers
`
`(2/28/06) 7,007,119: System and method for supporting split transactions on a
`bus
`
`(8/1/06) 7,085,878: Transportation of main memory and intermediate memory
`contents
`
`(10/31/06) 7,130,962: Writing cache lines on a disk drive
`
`(12/19/06) 7,152,125: Dynamic master/slave configuration for multiple expansion
`modules
`
`( l/2/07) 7,158,532: Half duplex link with isochronous and asynchronous
`arbitration
`
`(1/23/07) 7,168,026: Method and apparatus for preservation of failure state in a
`
`read destructive memory
`
`(2/27/07) 7,185,120: Method and apparatus for period promotion avoidance for
`hubs
`
`Exhibit 2021 - Page 07 of 08
`
`Exhibit 2021 - Page 07 of 08
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`

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`45.
`
`46.
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`47.
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`48.
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`49.
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`50.
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`51.
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`52.
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`53.
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`54.
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`55.
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`56.
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`57.
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`58.
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`59.
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`60.
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`61.
`
`(6/5/07) 7,228,406: Interacting with optional read-only memory
`
`(6/12/07) 7,231,497: Merging write-back and write-through cache policies
`
`(8/21/07) 7,260,672: Using data stored in a destructive-read memory
`
`(10/2/07) 7,277,993: Write—back disk cache
`
`(2/5/08) 7,328,304: Interface for a block addressable mass storage system
`
`(4/ 15/08) 7,360,015: Preventing storage of streaming accesses in a cache
`
`(6/ 17/08) 7,389,398: Method and apparatus for data transfer between partitions in
`a computer system
`
`(8/12/08) 7,412,562: Using non-volatile memories for disk caching of partition
`table entries
`
`(9/9/08) 7,424,603 & 8,086,837 (12/27/11): Method and apparatus to store
`initialization and configuration information
`(3/31/09): 7,512,082: Tracking transaction status for a bus system providing
`legacy bus compatibility
`(7/7/09) 7,558,911: Maintaining disk cache coherency in multiple operating
`
`system environment
`
`(09/08/09) 7,587,717 B2: Dynamic master/slave configuration for multiple
`
`expansion modules
`
`(12/29/09) 7,640,426: Methods and apparatus to manage hardware resources for a
`
`partitioned platform.
`
`(10/ 18/ 1 1) 8,041,920: Partitioning memory mapped device configuration space
`
`(3/27/ 12) 8,146,089: Sharing resources of a partitioned system.
`
`(1/ 10/ 13) 8,713,683: Security Arrangements for Extended USB Protocol Stack of
`a USB Host System
`
`(7/2/ 13) 8,479,208 B2: System partitioning to present software as platform level
`
`functionality
`
`Exhibit 2021 - Page 08 of 08
`
`Exhibit 2021 - Page 08 of 08
`
`