United States Patent [19]
`Bedingfield et al.
`
`[54] SYSTEM FOR PCMCIA PERIPHERAL TO
`EXECUTE INSTRUCTIONS FROM SHARED
`MEMORY WHERE THE SYSTEM RESET
`SIGNAL CAUSES SWITCHING BETWEEN
`MODES OF OPERATION BY ALERTING
`THE STARTING ADDRESS
`
`[75]
`
`Inventors: Jolm BediDgfield, Largo, Fla; Cnlg
`Matthews, Long Beach, NJ.
`
`[73] Assignee: AT&T Corp., Murray Hill, N.Y.
`
`[21 I Appl. No.: 64,304
`[22] Filed:
`May 20, 1993
`
`lnL Cl.6
`.......................... .......................... - •• G06F 3100
`[51]
`[52] u.s. Cl. ·····-·············· ... ·· 3951834; 395/500; 395/828;
`395/497.01; 3641160; 364n28.1; 3641238.2;
`3641243
`[58] Field of Sean:h ..................................... 3951275, 500,
`395/200, 834, 828, 497.01
`
`[56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5/1979 Rawlings et al ...........•............ 3641200
`4,156,907
`7/1984 Skelton et al ..•.•..•••....••..........• 3641200
`4,459,662
`!5/1985 Mendell .................................. 3641200
`4,519,032
`9/1986 DiNitto et al ........................... 34()(724
`4,611,202
`111989 Gulick. ............................ _ ......... 37&94
`4,809,269
`411989 Letwin .................................... 3641200
`4,825,3!58
`311993 Weiss et al .
`.............................. 379.198
`5,195,130
`611994 Gamey .................................... 3951200
`5,319,751
`611994 Phillips et al. .......................... 395/500
`5,321,828
`5,353,432 1011994 Riebek. et al. .. ........................ 395/500
`
`OTHER PUBUCATIONS
`
`Winn Rosch, PCMCIA: The Exptmsion Sysrem of/he Futurr
`PC Magazine, Jan. 26, 1993, pp. 321 10 326.
`European Search Repon dated Sep. 9. 1994, regarding EPO
`Application No. EP 94 30 3539.
`EP-A--0 464433 filed Jun. 15, 1991. Listed as panicu1arly
`relevant if taken alone, as to claims 1-11 , 15-18 on Euro(cid:173)
`pean Search Repon regarding EPO Application EP 94 30
`3539.
`
`IIIIIIIIIIIIW 1~1111111111111 am
`US005537654A
`5,537,654
`1111 Patent Number:
`[451 Date of Patent:
`Jul. 16, 1996
`
`EP-A--0268285 filed Nov. 19,1987. Listed as technological
`background in European Search Repon regarding EPO
`Application EP 94 30 3539.
`
`EP-A--0-536 793 filed Oct. 9, 1992. Listed as technological
`background in European Search Repon regarding EPO
`Application EP 94 30 3539.
`
`"Reprograrnmability Eases PCMCIA Designs" Publication:
`Electronic Design; publication date Apr. 18, 1994. Usted as
`intermediate document and technological background in
`European Search Repon regarding EPO Application EP 94
`30 3539.
`
`"Microprogram Loading System", Patent Abstracts of
`Japan, Publication No. JP62025353, publication date Mar. 2,
`1987, Genma Hideaki et al., Int. Class: G06Fl3/00; G06F9/
`24. Listed as technological background in European Search
`Repon regarding EPO Application EP 94 30 3539. Trans(cid:173)
`lation: Abstract only.
`
`Prinlllry Eraminer-Thomas C. Lee
`Assistant Examiner-Rehana Perveen Krick
`Allomey, Agml, or Firm-Joseph J. Opalacb
`
`[57]
`
`ABSTRACT
`
`A "Personal Computer Memory Card International Associa(cid:173)
`tion" (PCMCIA) peripheral, e.g .• a modem, incorporates a
`shared memory interface to a personal computer. This shared
`memory interface provides the capability 10 euily program
`the PCMCIA peripheral either in the factory or in the field.
`In addition, the shared memory interface removes the
`requirement of having a resident "boot-up" code in the
`PCMCIA peripheral. Finally, the shared memory interface
`provides the capability 10 transfer user data from the per(cid:173)
`sonal computer, i.e., data aerminal, 10 the PCMCIA modem
`at a higher data transfer rate than is currently available via
`the modem's universal uynchronous receive/transmit
`(UAIU) integrated circuit.
`
`4 Claims, 3 Drawlag Sbeell
`
`EXHIBIT 1020
`IPR Petition for U.S. Patent No. 6,249,825
`
`

`

`US. Patent
`
`Jul. 16, 1996
`
`Sheet 1 of 3
`
`5,537,654
`
`F l G. 1
`
`I
`
`r1OO _
`
`_
`
`_
`
`_
`
`_
`
`_
`
`_
`
`_
`
`_
`
`_
`
`_
`
`CPU
`
`I
`
`HOST ACCESS
`
`CPU mm 144
`
`cE171
`
`7
`
`CEI72
`
`.
`
`.
`
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`
`-
`
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`
`'
`
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`
`15%
`CHIP ENABLE
`ROuT1NGLOG1c
`i
`
`E
`
`15"
`‘521
`
`5
`141
`
`1401 fm WAIT ENABLE
`CONTROL LOGM: ~ ‘73
`Wm
`M2
`A»
`
`PCMC'A BUS '2‘
`
`'
`
`12o
`
`170
`I
`
`<:
`
`CPU
`
`'
`
`-
`
`160
`
`I
`
`GONTROL
`
`PRocEssoR .
`
`AB/US175
`
`PROGRAM MEMORY
`
`<2:
`
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`
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`
`'
`
`.
`
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`I
`
`v
`
`1
`SHARED MEMORY
`CE
`135 PCMCIA
`BUFFER J36
`“ ATTRIBUTE
`CONTROL
`REGION
`PROGRAM “157
`NORMAL
`OowNLOAO
`OPERAT1NG OPERATING
`MOOE
`MOOE
`
`130
`
`
`
`i PcMclA' :—:-—:—: _ [ PCMCIA GONNEGTOR ~
`
`
`
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`
`
`
`cE(MOsT) _ _
`
`-
`
`_
`
`'
`
`f
`
`_
`
`|NTER|EACE
`1°
`
`PCMCIA SLOT
`HOST CPU
`
`P22?!
`~27°
`
`?FLOPPY 01511 216
`
`200
`
`REMOVABLE sTORAGE UNIT 215
`
`F I G. 2
`
`NORMAL OPERATING MOOE
`DOWNLOAD OPERATING MODE
`
`LINE 151
`0E1
`CEZ
`
`LINE 152
`C£2
`CE1
`
`

`

`US. Patent
`
`Jul. 16, 1996
`
`Sheet 2 of 3
`
`5,537,654
`
`FIG. 3
`
`CPU 270
`
`PCMCIA PERIPHERAL MAP
`
`DOWNLOAD MODE LOCATION
`
`RESET LOCATION
`
`SHARED MEMORY I30
`
`FIG. 4
`
`ACCESS RESET MEMORY LOCATION on PCMCIA MODEM 100 I405
`
`WRITE A CONTROL PROGRAM TO SHARED MEMORY REGION 137 I410
`
`II
`
`II
`ACCESS DOWNLOAD MODE MEMORY LOCATION
`
`I415
`
`I
`TRANSFER NEW COMPUTER PROGRAM TO BUFFER 136
`
`I420
`
`II
`ACCESS RESET LOCATION ON PCMCIA MODEM IOO
`
`f 425
`
`

`

`US. Patent
`
`Jul. 16, 1996
`
`Sheet 3 of 3
`
`5,537,654
`
`FIG. 5
`
`CPU I70 BEGINS
`SHARED MEMORY ACCESS
`
`505
`'
`--—--> ACTIVATE wAII ENABLE SIGNAL ~
`
`515
`I
`DISABLE WAIT ENABLE
`SIGNAL AND WAIT FOR
`TIME; I
`
`HOST
`ACCESS
`SIGNAL
`INACTIVE
`v
`ACCESS SHARED ,320
`MEMORY
`
`530
`I
`DISABLE WAIT ENABLE N
`
`i)
`
`

`

`5,537,654
`
`1
`SYSTEM FOR PCMCIA PERIPHERAL TO
`EXECUTE INSTRUCTIONS FROM SHARED
`MEMORY WHERE THE SYSTEM RESET
`SIGNAL CAUSES SWITCHING BETWEEN
`MODES OF OPERATION BY ALERTING
`THE STARTING ADDRESS
`
`BACKGROUND OF THE INVENTION
`
`2
`of ?ash memory. This computer program includes the boot
`code and the operating program. When the modem‘s CPU
`receives a command from the host to change the operating
`program via one of the serial ports, the modem’s CPU
`executes a download program contained in the active bank
`of ?ash memory. This download software ?rst erases the
`non-active bank of ?ash memory and then copies the
`received data from one of the serial data ports into the
`non-active bank. This received data is the new computer
`program, which contains new boot code and the new oper
`ating program. At the conclusion of this download mode, the
`modem’s CPU toggles a non-volatile switch so that it will
`boot after a reset from the newly updated bank of ?ash
`memory, i.e., it switches which bank of ?ash memory is the
`active bank. This approach is disclosed in the co-pending,
`commonly assigned US. patent application of Hecht et a1.
`entitled “Apparatus and Method for Downloading Pro
`grams,” Ser. No. 07/880,257, ?led on May 8, 1992, now
`pending.
`As described above, although a ?ash memory upgrade for
`a PCMCIA modern via one of the serial ports is an advan
`tageous approach, there are several limitations. One is that
`during manufacture the boot block must be programmed into
`the ?ash memory prior to soldering the ?ash memory onto
`the printed circuit board. This adds cost to the manufacturing
`process of the PCMCIA modem. In addition, if the boot
`block is somehow erased or corrupted and power to the
`PCMCIA modem is lost, there is no recovery mechanism
`other than removing and replacing the ?ash memory. Fur
`thermore, the size of the boot block is ?xed (typically 16K
`bytes), which presents constraints on the functionality of the
`boot block. In addition, the boot block similarly constrains
`the size of the PCMCIA modem‘s operating program since
`a portion of the ?ash memory is dedicated to the boot block.
`Finally, the speed of any field upgrade is limited because of
`the use of a serial data port.
`
`SUMMARY OF THE INVENTION
`
`This invention eliminates all of the above-mentioned
`limitations by providing a method and apparatus for loading
`a ?ash memory after it is a part of a completed PCMCIA
`modem assembly. In accordance with the principles of the
`invention, a PCMCIA peripheral incorporates a shared
`memory interface to a host computer via the PCMCIA
`connector. This shared memory provides the capability to
`easily load or change the computer program of the PCMCIA
`peripheral from the host computer without requiring either
`the a priori presence of a dedicated boot block in the ?ash
`memory or the use of a serial data port.
`In an embodiment of the invention, a PCMCIA modern
`includes a CPU, memory, and a shared memory that is
`coupled to a personal computer (PC) via the PCMCIA
`connector. During normal operation, the CPU accesses and
`executes any computer program stored in the memory. A
`?eld upgrade or initial factory load is performed in the
`following manner. First, the PC applies a reset to the
`PCMCIA modem. During this reset, the PC stores a control
`program in the shared memory. After storing the control
`program, the PC alters the memory map of the PCMCIA
`modem so that after the reset the CPU executes the control
`program stored in the shared memory. This control program
`further provides the ability to the PCMCIA modem to
`transfer a new computer program via the shared memory to
`the memory of the PCMCIA modem, i.e., the control pro
`gram is the boot block software. After transferring the new
`computer program, the PC again initiates a reset of the
`
`The present invention relates to data communications
`equipment and, more particularly, to a modem having a
`“Personal Computer Memory Card lntemational Associa
`tion” interface.
`The “Personal Computer Memory Card International
`Association” (PCMCIA) interface de?nes the physical size
`and the electrical interconnection for a class of computer
`peripherals, i.e., PCMCIA peripherals. Generally, the size of
`a PCMCIA peripheral is approximately that of a “credit
`car
`Each credit card size PCMClA peripheral electrically
`interconnects via a PCMCIA electrical connector to a “host
`computer,” which is typically a “notebook” size personal
`computer (PC). PCMCIA peripherals like memory, modems,
`fax, hard disks, etc., are currently available.
`Like their more conventional cousins, a PCMCIA modem
`is a complex piece of equipment that comprises specialized
`microprocessor circuitry. For example, a PCMCIA modem
`typically includes a general-purpose microprocessor (CPU),
`memory, a telephone line interface to the Public Switched
`Telephone Network (PSTN), and a high-speed digital signal
`processor for processing the respective communications
`signal in both the transmit and receive directions. The
`functionality of the PCMCIA modem is provided by the
`CPU’s execution of a computer program, i.e., the “operating
`program,” that resides in the PCMCIA modem’s memory.
`This memory is usually “?ash memory,“ which is a non
`volatile memory that is ?eld-programmable by the modem’s
`CPU.
`An advantage of the ?ash memory is that it allows ?eld
`upgrades of the modem’s operating program for either
`providing new features or “bug” ?xes. In order to perform
`a field upgrade a part of the ?ash memory is reserved for a
`“boot block” computer program. This part of the ?ash
`memory is write-protected so that it retains its data, i.e., the
`boot block, even when the rest of the ?ash memory is erased
`and reprogrammed. The boot block includes computer soft
`ware for booting-up the modem, e.g., after application of
`power, and for loading the remainder of the ?ash memory
`with the operating program.
`A ?eld upgrade of the modem’s ?ash memory is per
`formed over one of the serial data ports, either the data
`communications port or the data terminal port. First, the
`modem‘s CPU receives a command to reload the operating
`program from a “host” coupled to one of the serial ports.
`Then the modem’s CPU executes that portion of the boot
`block associated with loading the ?ash memory. This part of
`the software ?rst erases the remaining portion of the ?ash
`memory and then receives the new operating program via
`one of the serial ports and writes the new operating program
`to the ?ash memory.
`An alternative approach that does not require a non
`writable boot block in the ?ash memory is provided by
`AT&T Paradyne‘s 3800 modem, which comprises an inde
`pendent “upper bank” and “lower bank” of ?ash memory.
`The modem’s CPU can boot from either bank. The modem’s
`CPU begins operation by executing the computer program
`stored in one of the ?ash memory banks, i.e., the active bank
`
`20
`
`30
`
`50
`
`60
`
`

`

`5,537,654
`
`3
`PCMCIA modem that returns the memory map of the
`PCMCIA modem to normal such that after the reset the CPU
`executes the new computer program stored in the PCMCIA
`modem‘s memory.
`In accordance with a feature of the invention, neither the
`?eld upgrade nor the initial program load in the factory
`require any boot block software to be resident in the PCM
`CIA card.
`Another feature of the invention uses the shared memory
`interface to transfer user data from the personal computer,
`i.e., data terminal, to the PCMCIA modern. This results in a
`higher data transfer rate than is currently available via the
`on-board universal asynchronous receive/transmit (UART)
`integrated circuit that couples the modem to any terminal
`equipment.
`
`10
`
`BRIEF DESCRIPTION OF THE DRAWING
`
`FIG. 1 is a block diagram of a portion of a PCMCIA
`20
`modem embodying the principles of the invention;
`FIG. 2 is a table implemented by chip enable routing logic
`150 of FIG. 1;
`FIG. 3 illustrates a PCMCIA peripheral map for host
`computer 200 of FIG. 1;
`FIG. 4 is a flow diagram of a method embodying the
`principles of the invention; and
`FIG. 5 is a ?ow diagram of a memory arbitration method
`performed by CPU 170 of FIG. 1.
`
`25
`
`30
`
`DETAILED DESCRIPTION
`
`FIG. 1 shows a portion of a PCMCIA modem that
`embodies the inventive concepts of this invention. As
`shown, host computer 200 includes PCMCIA slot 220 for
`receiving PCMCIA modern 100, host CPU 270, and remov
`able storage unit 215 for receiving ?oppy disk 216. PCM
`CIA modem 100 includes CPU 170, program memory 160,
`shared memory 130, chip enable routing logic 150, control
`logic 140, and PCMCIA connector 120. CPU 170 is a
`microprocessor-based central processing unit which oper
`ates on, or executes, program data stored in program
`memory 160 or shared memory 130 (discussed below) via
`control processor bus 175, which provides control, address
`and data signals (not shown). PCMCIA modern 100 is
`physically and electrically coupled to host computer 200 via
`PCMCIA interface 10. The latter includes PCMCIA con
`nector 120 of PCMCIA modem 100 and PCMCIA slot 220
`of host computer 200. For the purposes of this example,
`program memory 160 is a ?ash memory. The program data
`stored in program memory 160 is hereinafter referred to as
`the operating computer program. This operating computer
`program provides the modem functionality for transmitting
`and receiving data via a communications facility (not
`shown).
`It is assumed that CPU 170 includes appropriate address
`decode and chip enable logic. Two chip enable signals, CE1
`and CE2, are provided by CPU 170 on lines 171 and 172,
`respectively. These chip enable signals are used to select
`either program memory 160 or shared memory 130. Nor
`mally, these chip enable signals would be coupled directly to
`these memory devices. However, in accordance with the
`principles of the invention, CEl and CB2 are applied to chip
`enable routing logic 150, which provides chip enable signals
`to program memory 160 and shared memory 130 as a
`function of the mode of operation of PCMCIA modem 100.
`This is shown in FIG. 2. For the purposes of this example it
`
`35
`
`45
`
`50
`
`55
`
`65
`
`4
`is assumed that there are two modes of operation: a “normal
`mode” and a “download mode.” During a normal mode, chip
`enable routing logic 150 provides CEl to program memory
`160, via line 151; and provides CE2 to shared memory 174],
`via line 152.
`After a CPU reset signal is applied to CPU 170 via line
`144, CPU 170 applies CE1 to chip enable routing logic 150.
`As is known in the art, after application of a reset signal, a
`micro-processor starts execution at a known starting address
`location. For the purposes of this example, it is assumed that
`this prede?ned location is mapped to an address range
`associated with CEl. The CPU reset signal on line 144 is
`provided by control logic 140 either as a result of RESET
`signal (not shown) de?ned in the PCMCIA interface being
`asserted, e.g., during a power-up condition; or as a result of
`a memory access by host CPU 270 (discussed below). In the
`normal mode of operation, as shown in FIG. 2, CEl is routed
`to program memory 160 so that CPU 170 executes the
`operating computer program. In this normal mode, CPU 170
`accesses shared memory 130 by providing CE2 on line 152
`via chip enable routing logic 150.
`Shared memory 130 is also known as a “dual port ram”
`and has two sets of address, data, and control lines. One set
`is used to interface to PCMCIA bus 121 and the other set is
`used to interface to control processor bus 175. In accordance
`with the principles of the invention, shared memory 130 is
`put to di?'erent use depending on the mode of operation. As
`shown in FIG. 1, during the normal mode of operation,
`shared memory 130 comprises PCMCIA attribute region
`135, which includes the software de?nable Card Information
`Structure, Pin Replacement Register, Con?guration Option
`Register, Card Con?guration and Status Register in accor
`dance with the PCMCIA interface standard. However, dur
`ing the download mode of operation (discussed below),
`shared memory 130 includes region 136, which is a buffer
`that stores data received from host CPU 270 of host com—
`puter 200; and region 137, which stores a control program
`provided by host CPU 270 and subsequently executed by
`CPU 170.
`In accordance with the principles of the invention, the
`other mode of operation—~the download mode—directs
`CPU 170 to begin execution of program data from shared
`memory 130 after the application of a CPU reset signal on
`line 144. In particular, in the download mode of operation,
`chip enable routing logic 150 switches the CE1 signal from
`lead 151 to lead 152, and conversely, switches the CB2
`signal from lead 152 to lead 151. As a result, CPU 170 now
`executes instructions stored in shared memory 130 after
`exiting from a reset condition.
`Whether or not the download mode of operation is entered
`by PCMCIA modern 100 is under the control of host CPU
`270. It should be noted that under the PCMCIA standard,
`portions, or all, of PCMCIA modem 100 is mapped into a
`part of the PCMCIA peripheral space of host CPU 270. An
`illustrative PCMCIA peripheral map of PCMCIA 100 as
`viewed by host CPU 270 is shown in FIG. 3. An illustrative
`method for use in host CPU 270 for switching PCMCIA
`modem 100 to the download mode is shown in FIG. 4. Host
`CPU 270 affects a reset of CPU 170 in step 405 by asserting
`the RESET signal of the PCMCIA interface, or by writing a
`particular data value to a particular memory location on
`PCMCIA modem 100 that is associated with resetting PCM
`CIA modem 100, i.e., a “reset location” as shown in FIG. 3.
`In this example, this reset location is within the shared
`memory region and during normal operation is associated
`with the Con?guration Option Register, which is a pan of
`PCMCIA attribute region 135 as de?ned by the PCMCIA
`
`

`

`5,537,654
`
`5
`standard. One of the de?ned data bits of the Con?guration
`Option Register is the “SRESET” bit. CPU 270 affects a
`reset of PCMCIA modem 100 by setting the “SRESET” bit,
`which is d7, equal to a logical one. Control logic 140 of
`PCMCIA modem 100 detects this memory write to the reset
`location and in response thereto generates a CPU reset signal
`on line 144 to CPU 170.
`While the CPU reset signal is active CPU 170 is inactive,
`i.e., performs no memory accesses. Host CPU 270 then
`writes a control program to shared memory region 137 in
`step 410. After step 410, host CPU 270 switches the mode
`of operation of PCMCIA modem 100 by accessing in a
`particular way a respective prede?ned memory location
`associated with the download mode in step 415. In this
`example, host CPU 270 performs three consecutive writes of
`a prede?ned data value to the download mode location.
`Control logic 140 of PCMCIA modem 100 detects these
`consecutive memory accesses and compares the data values
`being written by CPU 270 to the prede?ned data value. If the
`data values being written equal the prede?ned data value,
`control logic 140 applies a control signal on line 142 to chip
`enable routing logic 150. The latter alters the routing of the
`above-mentioned chip enable signals as shown in FIG. 2 for
`the download mode. It is assumed that steps 410 and 415
`occur while the above-mentioned reset signal on line 144 is
`still active. In other words, it is assumed that control logic
`140 generates a CPU reset signal of sufficient width to
`provide the time for host CPU 270 to perform steps 410 and
`415. If host CPU 270 does not switch the mode of operation
`within the period of time when the CPU reset signal is
`active, control logic 140 blocks any subsequent attempts to
`switch modes and PCMCIA modem 100 simply continues to
`remain in the normal mode. In other words, control logic 140
`provides a “lockout mechanism” that prevents inadvertent
`switching of chip enables. This lockout mechanism forces
`PCMCIA modem 100 to default to the normal mode after a
`CPU reset signal is applied unless host CPU 270 accesses in
`the prescribed manner the download mode location. Alter
`natively, to avoid this time constraint on host CPU 270, the
`latter can make use of the SRESET bit for turning on and off
`the CPU reset signal.
`In the download mode and after removal of the CPU reset
`signal, CPU 170 executes the control program in shared
`memory 130. Host CPU 270 men transfers data to shared
`memory region 136 in step 420. This data represents por
`tions of the new computer program to be placed into
`program memory 160. The control program, when executed
`by CPU 170, transfers the data placed in shared memory
`region 136 by host CPU 270 to program memory 160—thus
`changing the operating computer program executed by CPU
`170 during the normal mode of operation. It should be noted
`50
`that no boot block software is required to be resident in the
`PCMCIA peripheral other than the temporary control pro
`gram provided by host CPU 270 in order to accomplish this
`download, irrespective of whether this download is a part of
`a ?eld upgrade or the initial program load in a factory. It is
`assumed that the control program executed by CPU 170
`includes a “hand-shaking” procedure for coordinating the
`transfer of data blocks from host CPU 270 to program
`memory 160. For example, after the data in shared memory
`region 136 is written by CPU 170 to a portion of program
`memory 160, CPU 170 writes to a prede?ned “?ag” location
`of shared memory 130. This ?ag, when read by host CPU
`270, indicates to host CPU 270 to write the next portion of
`the operating computer program to shared memory region
`
`45
`
`55
`
`After host CPU 270 has ?nished downloading the new
`operating computer program to PCMCIA modem 100, host
`
`20
`
`25
`
`35
`
`6
`CPU 270 again resets PCMCIA modem 100 in step 425.
`With the application of the CPU reset signal, control logic
`140 switches PCMCIA modem 100 back to the normal mode
`as part of the lock-out mechanism described above. As a
`result, control logic 140 alters the routing of the above
`mentioned chip enable signals as shown in FIG. 2 for the
`normal mode. In the normal mode and after removal of the
`CPU reset signal, CPU 170 executes the new operating
`computer program now stored in program memory 160.
`As can be seen from the above description, when trans‘
`ferring data from the buffer located within shared memory
`region 136 to program memory 160, both CPU 170 and host
`CPU 270 are accessing shared memory 130. For example, at
`the same time CPU 170 is reading program data from shared
`memory region 137—host CPU may be attempting to write
`data to the buffer located within shared memory region 136.
`As a result, a memory contention scheme is required to
`arbitrate between CPU 170 and host CPU 270 when they
`attempt to access shared memory 130 simultaneously.
`In this example, the memory contention scheme is imple
`mented by a combination of hardware, represented by con
`trol logic 140, a software protocol, and the PCMCIA de?ned
`WAIT signal on line 142. Although shown as a separate
`signal for convenience, it should be realized that the WAIT
`signal on line 142 is a subset of PCMCIA bus 121.
`Control logic 140 monitors PCMCIA bus 121 to detect
`any shared memory accesses by host CPU 270. When host
`CPU 270 begins a shared memory access to PCMCIA
`modem 100, control logic 140 activates the host access
`signal on line 141, which is received by CPU 170. In
`addition, CPU 170 provides a wait enable signal on line 173,
`which is received by control unit 140. If the wait enable
`signal is active, control unit 140 enables the generation of
`the WAIT signal on line 142 in response to any subsequent
`shared memory access by host CPU 270. As is known in the
`art, when the PCMCIA WAIT signal on line 142 is active,
`host CPU 270 inserts wait states in the current memory
`access. Conversely, if the wait enable signal is inactive,
`control unit 140 disables the generation of this WAIT signal
`so that no additional wait states are inserted into a shared
`memory access of host CPU 270. It should be noted that the
`PCMCIA speci?cation requires that accesses by host com
`puter 270 via PCMCIA connector 120 be completed with no
`more than a 12 microsecond delay.
`FIG. 5 shows a ?ow diagram for a method used by CPU
`170 for implementing a software protocol to control the
`generation of the wait enable signal on line 173. Whenever
`CPU 170 accesses shared memory, CPU 170 ?rst activates
`the wait enable signal on line 173 in step 505. CPU 170 then
`reads, or samples, the host access signal on line 141 in step
`510. This allows CPU 170 to check if host CPU 270 has
`already begun an access to shared memory. If the host access
`signal is active, then the wait enable signal on line 173 is
`disabled and CPU 170 itself waits for a predetermined
`period of time, T, in step 515 before returning to step 505.
`The latter step is important because host CPU 270 may
`ignore the WAIT signal on line 141 if it was enabled after the
`wait recognition window of host CPU 270. This may occur
`because of the asynchronous relationship of any shared
`memory accesses by the two processors. However, if the
`host access signal is inactive, CPU 170 accesses shared
`memory in step 520 and then disables the wait enable signal
`on line 173 in step 530.
`As described above and in accordance with the principles
`of the invention, host CPU 270 is able to change the
`operating computer program stored in PCMCIA modem 100
`
`

`

`5,537,654
`
`10
`
`7
`and thereby provide an easy means to update or change the
`functionality of PCMCIA modem 100. As shown in FIG. 1,
`the program data executed by PCMCIA modem 100 can be
`provided to host CPU 270 via ?oppy disk 216. Indeed, any
`type of programs for PCMCIA modern 100 can be easily
`provided. For example, ?oppy disk 216 can supply a diag
`nostic testing program, which when downloaded by host
`CPU 270 allows PCMCIA modem 100 to perform a series
`of diagnostic tests.
`In addition, the use of shared memory 130 in PCMCIA
`modem 100 also provides other improvements to system
`operation. For example, since the PCMCIA peripheral is a
`modern, host computer 200 is a data terminal. As is known
`in the art, host CPU 270 transfers data for transmission over
`a data communications channel (not shown) by writing data
`in parallel to a UART (not shown) of PCMCIA modem 100.
`This UART then converts the data to a serial form to
`simulate the serial data transmission from the data terminal.
`Consequently, the PCMCIA modem again converts the
`serial data stream from its UART back to a parallel form
`again. Unfortunately, this process tends to limit the speed of
`any data transfer. However, in accordance with the inven
`tion, shared memory 130 can be used to transfer user data
`between the data terminal and the modem at a a higher data
`transfer rate. This is accomplished by dedicating a portion of
`shared memory 130 as a bu?’er for directly transferring data
`from host computer 200 to PCMCIA modern 100.
`In addition, in the prior art, the PCMCIA attribute struc
`ture is typically pre-de?ned and non-changeable, e.g., a
`30
`read-only memory (ROM) is used to provide the PCMCIA
`attribute structure. However, the use of shared memory 130
`allows for a software de?nable PCMCIA card information
`structure that can be dynamically altered by CPU 170.
`The foregoing merely illustrates the principles of the
`invention and it will thus be appreciated that those skilled in
`the art will be able to devise numerous alternative arrange
`ments which, although not explicitly described herein,
`embody the principles of the invention and are within its
`spirit and scope.
`For example, although the inventive concept was
`described in terms of utilizing ?ash memory, any non
`volatile programmable RAM can be used. In fact, even
`
`8
`volatile RAM can be used as long as the PCMCIA peripheral
`is properly initialized by the host computer on power-up of
`the system.
`We claim:
`1. Apparatus comprising:
`a PCMCIA connector;
`a processor responsive to a processor reset signal for
`providing a starting address for accessing a memory
`location to execute at least one instruction stored
`therein;
`a ?rst memory;
`a second memory that is shared with a host computer via
`the PCMCIA connector and which stores PCMCIA
`attribute information in a ?rst mode; and
`control circuitry coupled to a parallel data bus of the
`PCMCIA connector responsive to a system reset signal
`received from the PCMCIA connector for a:) providing
`the processor reset signal to the processor, and b)
`switching between the ?rst and a second mode of
`operation;
`where the system reset signal causes the control circuitry
`to alter the starting address provided by the processor
`in such a way that the memory location is located
`within the ?rst memory in the ?rst mode of operation,
`and in the second mode of operation, the system reset
`signal causes the control circuitry to alter the starting
`address provided by the processor means in such a way
`that the memory location is located within the second
`memory.
`2. The apparatus of claim 1 further including'the host
`computer.
`3. The apparatus of claim 2 wherein the a system reset
`signal is at least one memory access by the host computer to
`the second memory via the PCMCIA connector.
`4. The apparatus of claim 2 wherein the host computer
`includes a removable storage means for receiving from a
`disk inserted therein a plurality of instructions that is copied
`to the second memory.
`
`*
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`*
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`* * *
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`20
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`25
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`35
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