111111
`
`(12) United States Patent
`Snyder et al.
`
`lllllllllllllllllllllllllllllllllllllllllllllllllllllllllllll
`
`US006338109Bl
`US 6,338,109 Bl
`*Jan.8,2002
`
`(10) Patent No.:
`(45) Date of Patent:
`
`(54) MICROCONTROLLER DEVELOPMENT
`SYSTEM AND APPLICATIONS THEREOF
`FOR DEVELOPMENT OF A UNIVERSAL
`SERIAL BUS MICROCONTROLLER
`
`5,319,754 A * 6/1994 Meinecke et al.
`.......... 710/130
`5,329,471 A * 7/1994 Swoboda eta!. ............. 703/23
`5,426,421 A
`• 6/1995 Gray ..................... 395/200.53
`
`(List continued on next page.)
`
`(75)
`
`Inventors: Warren S. Snyder, Snohomish;
`Frederick D. Jaccard, Woodinville,
`both of WA (US)
`
`FOREIGN PPJENT DOCUMENTS
`wo 97/36230
`
`10/1997
`
`wo
`
`(73)
`
`Assignee: Cypress Semiconductor Corp., San
`Jose, CA (US)
`
`(*)
`
`Notice:
`
`This patent issued on a continued pros(cid:173)
`ecution application filed under 37 CFR
`1.53(d), and is subject to the twenty year
`patent term provisions of 35 U.S.C.
`154(a)(2).
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 08/711,419
`
`(22) Filed:
`
`Aug. 30, 1996
`
`Int. Cl.7
`••••••••.•.•..........................••••.••.•. G06F 13/00
`(51)
`(52) U.S. Cl •....................... 710/129; 710/100; 710/126;
`710/127; 711!103; 714/29; 395/500
`(58) Field of Search ....................... 395/183.05, 200.53,
`395/500, 306, 309, 307, 280; 703/23, 28;
`711/103; 714/29; 709/223; 710/129, 127,
`100, 126
`
`(56)
`
`References Cited
`
`U.S. PPJENT DOCUMENTS
`
`3,833,888 A
`4,038,533 A
`4,042,972 A
`4,433,378 A *
`4,466,055 A
`4,511,968 A
`5,047,926 A *
`5,241,631 A *
`5,313,618 A *
`
`9/1974 Stafford et a!.
`7/1977 Dummermuth
`8/1977 Gruner et a!.
`2/1984 Leger ......................... 395/280
`8/1984 Kinoshita et al.
`4/1985 Fencsik et al.
`9/1991 Kuo et a!. . ... .. ... ... . 395/183.05
`8/1993 Smith et a!. .. ... .. ... . .. ... 395/306
`5/1994 Pawloski ..................... 703/28
`
`OTHER PUBLICATIONS
`
`Universal Serial Bus Specification, Revision 1.0, pp. 1-268,
`Jan. 15, 1996.
`Universal Host Controller Interface (UHCI) Design Guide,
`Revision 1.1, Intel, pp. 1-41, Mar. 1996.
`Warren Snyder, "Dual ROM Microprogrammable Micro(cid:173)
`processor and Universal Serial Bus Microcontroller Devel(cid:173)
`opment System", U.S. Serial No. 08!705,807, Filed Aug. 30,
`1996. (Now U.S. Patent No. 5,859,993-Issued Jan. 12,
`1999).
`
`Primary Examiner--Ayaz R. Sheikh
`Assistant Examiner--Frantz Blanchard Jean
`(74) Attorney, Agent, or Firm-Christopher P. Maiorana,
`P.C.
`
`(57)
`
`ABSTRACT
`
`A microcontroller including a system bus; a microprocessor
`coupled to the system bus and configured to transfer data and
`control signals over the system bus; a memory device
`coupled to the microprocessor and mapped to the system bus
`and configured to store microprogram instructions for
`execution by the microprocessor; a controller coupled to the
`system bus and configured to transfer data and control
`signals to the microprocessor over the system bus; a host
`interface coupled to the system bus and configured to
`interface to a host computer and receive the data and the
`control signals over the system bus from the microprocessor;
`and an I/0 interface coupled to the system bus and config(cid:173)
`ured to interface to at least one I/0 device and receive the
`data and the control signals over the system bus from the
`microprocessor.
`
`23 Claims, 2 Drawing Sheets
`
`EXHIBIT 1015
`IPR Petition for U.S. Patent No. 6,249,825
`
`

`
`US 6,338,109 Bl
`Page 2
`
`U.S. PATENT DOCUMENTS
`5,495,593 A *
`5,546,562 A *
`5,664,123 A *
`5,675,813 A
`5,684,721 A
`
`Elmer et a!. ................ 711!103
`Patel .......................... 395!500
`Lee et a!.
`. . . . . . . . . . . . . . . . . . . 395/309
`Holm dahl
`Swoboda et a!.
`
`2/1996
`8/1996
`9/1997
`10/1997
`* 11/1997
`
`5,689,684 A * 11/1997 Mulchandani eta!. ........ 703/23
`5,691,994 A * 11/1997 Acosta eta!. .............. 371/40.1
`5,758,107 A * 5/1998 Robles eta!. ............... 395/307
`5,805,792 A * 9/1998 Swoboda eta!. ............. 703/23
`5,941,979 A * 8/1999 Lentz .......................... 712/33
`* cited by examiner
`
`........... 364/578
`
`

`
`15,
`SYSTEM BUS LOGIC
`50~
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`I
`I
`
`r10a
`,.-10b
`...-10c
`
`Cl
`
`<(
`
`RAM
`
`U.S. Patent
`
`Jan.8,2002
`
`Sheet 1 of 2
`
`US 6,338,109 Bl
`
`USB MICROCONTROLLER
`g
`-~--------------------------,
`1 MICROPROCESSOR
`I
`'"'"l
`I
`FPGA1
`"'~~--,
`I
`I
`3a
`1 ADDRESS
`I
`I
`I
`I
`I
`
`DATA
`
`ROM':
`I
`I
`I
`I ADDRESS
`
`3b
`
`ROM':
`I
`_ __ __ .J
`
`DATA
`
`22~
`ALU
`
`I
`
`34"'\
`SEQUENCER
`LOGIC
`11 a"'\
`SYSTEM
`STATE
`REG ESTERS
`
`I
`
`ADDRESS
`
`2~
`
`DATA
`
`I
`
`INSTRUCTION
`RAM
`
`!
`I TRACE REGESTER I
`(/)
`I
`(/) <(
`I
`w
`------- ---------------------
`~
`a:: ~
`.J
`Cl ~ DATA
`_,I Cl
`CONTROL SIGNALS
`(SOl, lOW, lOR, MW, MR, & BRQ)
`
`16"'\
`
`I
`USB
`HOST I
`
`6
`\
`
`USB
`
`17...1
`
`1/0 PORTS
`19...1
`
`7"'\
`
`PC
`7a"'\
`
`I
`I
`I
`I
`I
`I
`18,
`I :
`1/0
`DEVICE I :
`I ____ ..,
`I
`I
`I
`I
`I
`I
`I RS232
`r~ I
`14...1
`I
`I
`
`DEVELOPER
`ACCESS
`DEVICE
`
`7b~
`
`12
`\..J
`l
`
`FPGA2
`USB LOGIC
`
`USB INTERFACE J
`12b../ 12a~
`I
`I REG ESTERS
`
`13
`\J
`
`110 LOGIC
`
`1/0 INTERFACE
`13b../ 13a~
`
`I REG ESTERS
`
`1
`I
`
`CONTROLLER
`5a,
`
`5
`\.
`J PC INTERFACE J
`
`l
`
`7c~
`
`7d~
`
`FIG. 1
`
`'-v--'
`10
`I DISPLAY I ~--------------------------------------
`I
`I MOUSE
`I
`I KEYBOARD
`
`

`
`U.S. Patent
`
`Jan.8,2002
`
`Sheet 2 of 2
`
`US 6,338,109 Bl
`
`50'
`
`BIT NUMBER:
`
`5 4 3 2 1 0
`..---,r---r-.--,----r---r---r----"1
`
`RUN
`51
`
`FIG. 2
`
`YES
`(RUN 51=0)
`
`NO (RUN 51=1)
`
`200
`EXECUTE ONE
`INSTRUCTION
`
`NO
`(SINGLE STEP 52=0)
`
`CLR/ RESET
`(RUN 51=0)
`
`FIG. 3
`
`

`
`US 6,338,109 Bl
`
`1
`MICROCONTROLLER DEVELOPMENT
`SYSTEM AND APPLICATIONS THEREOF
`FOR DEVELOPMENT OF A UNIVERSAL
`SERIAL BUS MICROCONTROLLER
`
`BACKGROUND OF THE INVENTION
`
`2
`
`-continued
`
`5
`
`qO <~ qO_temp;
`q1 <~ q1_temp;
`q2 <~ q2_temp;
`END struct;
`
`which defines the inputs and outputs of the shifter and then
`maps those bits to a series of D Flip-Flops. After compiling
`10 the source code and debugging the circuit, a netlist can be
`generated for a specific family of FPGAor ASIC devices to
`produce the circuit with the desired functionality.
`
`1. Field of the Invention
`This invention relates to microprocessor development
`systems, and more particularly to a Universal Serial Bus
`("USB") microcontroller development system configured to
`aid in the design, debug, and testing of USB compliant
`devices and firmware.
`2. Discussion of Background
`USB is a peripheral bus standard that allows computer 15
`peripherals to be attached to a personal computer without the
`need for specialized cards or other vendor specific hardware
`attachments. The USB standard specifies a common con(cid:173)
`figuration for the connection of well known peripherals such
`as CD-ROM, tape and floppy disk drives, scanners, printers, 20
`keyboards, joysticks, mice, telephones, modems, etc. In
`addition to well known peripheral devices, the USB standard
`has flexibility to accommodate less known and newly devel(cid:173)
`oped technologies. Information about the USB standard,
`including the specification for building USB compliant 25
`devices, is currently available free of charge over the Inter-
`net.
`Developers wishing to implement USB devices must
`build that device to the USB standard. Prior to fabricating
`IC's for USB standard devices, a developer will spend a
`significant amount of resources in testing and refinement of
`prototypes. An efficient method for testing USB compliant
`devices is needed to reduce the costs associated with pro(cid:173)
`totype development and testing of those devices.
`The design and manufacture of electronic devices such as
`counters, state machines, specialized registers, and micro(cid:173)
`processors is currently aided by technologies that allow
`engineers to specify design characteristics of a circuit, such
`as storage device size, register types, connections and asso(cid:173)
`ciated logic, in a Hardware Description Language ("HDL").
`This source code or HDL is then compiled, allowing the
`electronic device to be simulated and debugged while imple(cid:173)
`menting the specified circuit characteristics. Once the opera(cid:173)
`tion of device is verified, the compiled source code can be 45
`mapped to a specific architecture such as Application Spe(cid:173)
`cific Integrated Circuits ("ASICs") or Field Programmable
`Gate Arrays ("FPGAs"). This allows the system designer to
`produce a device with design flexibility and portability into
`various architecture families.
`As an example, a 3-bit shift register can be implemented
`in a HDL such as Register Transfer Language ("RTL") with
`the following RTL statements:
`
`SUMMARY OF THE INVENTION
`
`Accordingly, one object of the present invention is to
`provide a flexible USB microcontroller development system
`that allows for testing of USB compliant devices. The
`microcontroller includes a microprocessor with instruction
`RAM, a controller with a computer interface (e.g., RS-232)
`to a personal computer or other external computing device,
`data RAM, USB logic and registers for interfacing to a USB
`host computer, and 1/0 logic and registers for interfacing to
`an 1/0 device. The USB microcontroller development sys-
`tem includes the microcontroller, an external computer, a
`USB host computer, and an 1!0 device. The USB micro(cid:173)
`controller development system allows both the micropro(cid:173)
`cessor or an attached external computer to control the
`microcontroller. This is accomplished by mapping the USB
`30 microcontroller system state which includes the contents of
`the data RAM, the microprocessors system state registers
`including system state registers corresponding to the con(cid:173)
`tents of the instruction RAM, the USB logic registers, and
`the 1/0 logic registers to a system bus. The controller or
`35 microprocessor places address, data, and control signals on
`the system bus which are decoded by various logic to allow
`reading or writing of the system state. The controller reads
`or writes the instruction RAM by reading or writing a
`program counter and an instruction register, included as part
`40 of the microprocessor's system state registers, via the sys(cid:173)
`tem bus. Accordingly, the external computer connected to
`the controller via the RS-232 bus can read or write the USB
`microcontroller system state to aid in the design, debug, and
`testing of USB compliant devices and firmware.
`It is also an object of the present invention to provide a
`development access device on the external computer for
`providing a user a graphical interface for controlling the
`USB microcontroller. The development access device dis(cid:173)
`playing menus, buttons, text boxes etc. corresponding to the
`50 microprocessor's system state registers, the contents of the
`instruction RAM, the USB logic registers, and the 1!0 logic
`registers. The user, after selecting the appropriate menu,
`button, or filling in the appropriate text box, can read or
`write the corresponding microprocessor's system state
`55 registers, the contents of the instruction RAM, the USB
`logic registers, and the 1!0 logic registers via the external
`computer and computer interface to control the USB micro(cid:173)
`controller.
`It is yet another object of the present invention to provide
`60 a method for implementing the above USB microcontroller
`development system utilizing a Hardware Description Lan(cid:173)
`guage. By utilizing a Hardware Description Language, the
`design engineers are free to concentrate on the design of
`important features of the system and it's functionality rather
`65 than a gate level implementation of the system. After deter(cid:173)
`mining top level characteristics and functional blocks of the
`system, an HDL program describing those characteristics
`
`ENTITY shifter3 IS port (
`elk
`IN BIT;
`IN BIT;
`x
`:
`qO
`OUT BIT;
`:
`q1
`OUT BIT;
`:
`q2
`OUT BIT;
`END shifter3;
`ARCHITECTURE struct OF shifter3 IS
`SIGNAL qO_temp, q1_temp, q2_temp : BIT;
`BEGIN
`d1
`d2
`d3
`
`:OFF PORT MAP (x,clk,qO_temp);
`:OFF PORT MAP (qO_temp,clk,q1_temp);
`:OFF PORT MAP (q1_temp,clk,q2_temp);
`
`

`
`US 6,338,109 Bl
`
`4
`microcontroller, the instructions loaded from an external
`computer coupled to a computer interface of the
`microcontroller, the external computer directed to load the
`microprocessor instructions by a developer access device
`running on the external computer;retrieving the set of micro(cid:173)
`processor instructions from the memory device for execu-
`tion by the microprocessor; and controlling a starting,
`stopping, and single step execution of the microprocessor
`instructions by the microprocessor by the developer access
`10 device reading and writing at least one register of system
`state registers of the microprocessor.
`
`3
`and functional blocks is developed and debugged. In the
`present invention, HDL implemented processes are used in
`designing various functional blocks of the USB microcon(cid:173)
`troller development system. The USB microcontroller
`development system designed using HDL is then mapped to 5
`FPGAs and packaged onto a single printed circuit board
`along with minimal additional logic such as EEPROMs and
`RAM.
`The above and other objects are achieved according to the
`present invention by providing a new and improved micro(cid:173)
`controller including a system bus; a microprocessor coupled
`to the system bus and configured to transfer data and control
`signals over the system bus; a memory device coupled to the
`microprocessor and mapped to the system bus and config(cid:173)
`ured to store microprogram instructions for execution by the 15
`microprocessor; a controller coupled to the system bus and
`configured to transfer data and control signals to the micro(cid:173)
`processor over the system bus; a host interface coupled to
`the system bus and configured to interface to a host com(cid:173)
`puter and receive the data and the control signals over the 20
`system bus from the microprocessor; and an 1!0 interface
`coupled to the system bus and configured to interface to at
`least one 1!0 device and receive the data and the control
`signals over the system bus from the microprocessor.
`According to a second aspect of the present invention,
`there is provided a method of fabricating a microcontroller
`including steps of determining functional microprocessor
`requirements that will at least provide execution control of
`the microprocessor; determining functional control circuit
`requirements that will at least provide control of the micro- 30
`processor; determining functional host interface require(cid:173)
`ments that will at least provide an interface to a host
`computer; determining functional I/O interface requirements
`that will at least provide an interface to at least one 1!0
`device; defining the functional requirements of the 35
`microprocessor, the control circuit, the host interface and the
`1!0 interface in an Hardware Description Language (HDL);
`compiling the HDL language to derive a circuit representa(cid:173)
`tion of the microcontroller; and mapping the circuit repre(cid:173)
`sentation onto one or more devices.
`According to a third aspect of the present invention, there
`is provided a microcontroller development system including
`a system bus; a microprocessor coupled to the system bus
`and configured to transfer data and control signals over the
`system bus; a memory device coupled to the microprocessor 45
`and mapped to the system bus and configured to store
`microprogram instructions for execution by the micropro(cid:173)
`cessor; an external computing device; a controller coupled to
`the system bus and configured to transfer data and control
`signals to the microprocessor over the system bus including 50
`a computer interface coupled to the system bus and config(cid:173)
`ured to transfer commands from the external computing
`device to the controller, the commands used by the controller
`to generate the data and the control signals for controlling
`the microprocessor; a host interface coupled to the system 55
`bus and configured to interface to the external computing
`device and receive the data and the control signals over the
`system bus from the microprocessor; at least one 1!0 device;
`and an 1!0 interface coupled to the system bus and config(cid:173)
`ured to interface to the at least one 1!0 device and receive the 60
`data and the control signals over the system bus from the
`microprocessor.
`According to a fourth aspect of the present invention,
`there is provided a method of development of a microcon(cid:173)
`troller in a microcontroller development system, including
`steps of loading a set of microprocessor instructions into a
`memory device coupled to a microprocessor of the
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`A more complete appreciation of the invention and many
`of the attendant advantages thereof will be readily obtained
`as the same becomes better understood by reference to the
`following detailed descriptions when considered in connec(cid:173)
`tion with the accompanying drawings, wherein:
`FIG. 1 is a block diagram implementing the USB micro(cid:173)
`controller development system according to the present
`invention;
`FIG. 2. is a bit-diagram of a trace register used on the USB
`microcontroller of FIG. 1; and
`FIG. 3. is a logic flow diagram showing the run/single step
`operations of the USB microcontroller development system
`of FIG. 1.
`
`25
`
`40
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`Referring now to the drawings, wherein like reference
`numerals designate identical or corresponding parts
`throughout the several views, and more particularly to FIG.
`1 thereof, the present invention includes a USB microcon-
`troller development system 100, which allows 100% testing
`of USB firmware before the fabrication of final ICs. The
`USB microcontroller development system 100 is designed
`using FPGAs, EEPROMs and RAMs, but may be imple(cid:173)
`mented in other electronic configurations including ASICs
`and/or microprocessor systems having a computing device
`with appropriately mapped system states and 1!0 interfaces,
`as described herein.
`The operation of the USB microcontroller development
`system will be discussed with reference to FIGS. 1-3.
`In FIG. 1, FPGA1 1 and EEPROMs 3 implement a
`microprocessor 9. Within the microprocessor 9 is provided
`circuit block 11 including ALU 22, sequencer logic 34, and
`system state registers lla. System state registers lla are
`mapped to a system bus 10 through system bus logic 15
`which includes a trace register 50. Microprocessor 9 is
`connected to instruction RAM 2 which is used to store USB
`firmware under development.
`FPGA2 6 includes USB logic 12 which provide an
`interface to a USB host computer 16 via USB bus 17 and
`includes registers 12a; 1!0 logic 13 which provides an
`interface to an 1!0 device 18 via 1!0 ports 19 and includes
`registers 13a; and controller 5 which provides a PC interface
`Sa to the PC 7 (or other external computing device) via
`RS-232 bus 14. The USB logic 12, the 1!0 logic 13 and the
`controller 5 are coupled to the system bus logic 15 of
`microprocessor 9 via the system bus 10. In addition, system
`bus logic 15 includes trace register 50 which is mapped to
`the system bus and can be accessed by either the controller
`5 or the microprocessor 9 to control the execution of
`65 firmware running in instruction RAM 2.
`As previously discussed, the purpose of the USB micro(cid:173)
`controller development system is to aid engineers in the
`
`

`
`US 6,338,109 Bl
`
`15
`
`5
`design, debug and development of USB compliant devices
`and USB firmware. This is accomplished by providing a
`flexible USB microcontroller development system that
`allows data gathering and stimulation of the USB micro(cid:173)
`controller system state by providing the system state as
`addressed 110, provides a computer interface to the USB
`microcontroller and allows a user to load and control execu(cid:173)
`tion of USB firmware, an d provides an interface to a USB
`host computer and USB device under development.
`The data gathering and stimulation of the USB microcon(cid:173)
`troller system state will now be described.
`The USB microcontroller system state is determined by
`providing access to the following registers: System state
`registers lla of microprocessor 9 including (not shown): a
`program counter which holds the address of the instruction
`RAM 2, an instruction register which holds the data corre(cid:173)
`sponding to the program counter, stack pointers which are
`addresses into data RAM 4, and temporary registers which
`are used during execution of instructions from instruction
`RAM 2 by microprocessor 9. In addition the USB micro(cid:173)
`controller system state includes data memory contents in 20
`data RAM 4, USB logic registers 12a, 110 logic registers
`13a, and trace register 50 of system bus logic 15.
`The above registers are 110 mapped to the system bus 10,
`so that when an address is placed on the system bus the
`system bus logic 15, USB logic 12 and 110 logic 13 decode 25
`this address to determine which logic block and which
`register within the logic block is being addressed.
`In addition, system bus 10 includes several control signals
`lOa that are provided by microprocessor 9 or controller 5.
`From the microprocessor 9:
`SOl (start of instruction): tells the USB logic 12, 110 logic
`13, and controller 5 that a new instruction is about to
`execute in instruction RAM 2;
`lOW (110 write): tells the USB logic 12,110 logic 13, and
`controller 5 that the microprocessor 9 wishes to write to 35
`system state registers lla, USB logic registers 12a, 110
`logic registers 13a, or trace register 50;
`lOR (110 read): tells the USB logic 12, 110 logic 13, and
`controller 5 that the microprocessor 9 wishes to read
`system state registers lla, USB logic registers 12a, 110 40
`logic registers 13a, or trace register 50;
`MW (memory write): tells the USB logic 12, 110 logic 13,
`and controller 5 that the microprocessor 9 wishes to
`write data to data RAM 4;
`
`6
`Control signals lOW, lOR, MW and MR of control
`signals lOa are the same as from the microprocessor 9,
`except from the point of view of the controller 5, they share
`the same physical wire/signal paths but the scope is deter-
`s mined by a master bus request ("BRQ") control signal of
`control signals lOa. BRQ allows the controller 5 to preempt
`the microprocessor 9 and have the controller 5 control
`signals replace those of the microprocessor 9. The value/
`states of the controller 5 control signals lOa are generated
`10 from a finite state machine (not shown) in controller 5 that
`also communicates with the PC 7 using an RS-232 serial
`data protocol. In this way controller 5 can take over control
`of the system from microprocessor 9 and read and write the
`contents of the system state.
`The computer interface and execution control and loading
`of USB firmware will now be described.
`In FIG. 1, PC 7 includes developer access device 7a which
`is a graphical user interface ("GUI") or other software
`running on PC 7 for displaying menus, buttons, text boxes
`etc. (not shown) on display 7b corresponding system state
`registers lla, trace register 50, USB logic registers 12a, and
`110 registers 13a and for commanding PC 7 to transfer
`appropriate commands over the RS-232 bus 14 to PC
`interface Sa of controller 5. Thus, the user, after selecting the
`appropriate menu, button, or filling in the appropriate text
`box with mouse 7c and keyboard 7d, can read or write the
`corresponding system state registers lla, trace register 50,
`USB logic registers 12a, and 110 registers 13a via PC 7,
`RS-232 bus 14 and PC interface Sa to control the USB
`30 microcontroller 8.
`On command from developer access device 7a, as previ(cid:173)
`ously described, PC 7 sends a series of three 8-bit data bytes
`as serial data to PC interface Sa of controller 5 in a command
`structure over RS-232 bus 14. The PC interface Sa includes
`a UART function for providing the RS-232 function. The
`first byte sent by PC 7 is either an 110 (system state registers
`lla, USB logic registers 12a, 110 logic registers 13a, or
`trace register 50) or data RAM 4 address; the second byte is
`a command; and the third byte is a data value that together
`with the address byte and the command byte identifies and
`supports data read and write operations to either an 110 or
`data RAM 4 address location. The 110 and data RAM 4
`command structure is outlined in Table A
`
`TABLE A
`
`Command Structure
`
`Command
`Byte
`(hex)
`
`Data
`Byte
`x ~don't
`care
`
`00
`
`02
`01
`
`03
`
`DATA
`
`DATA
`XX
`
`XX
`
`Function
`
`Write the Data Byte to
`the location identified by
`the Address Byte.
`Read the data byte at the
`location identified by the
`address byte an transmit
`the byte read to PC 7.
`
`Command
`Name
`
`WRITE DATA
`BYTE
`
`READ DATA
`BYTE
`
`Address Byte
`
`Data RAM 4
`Address
`*l/0 Address
`Data RAM 4
`Address
`*l/0 Address
`
`*l/0 includes system state registers lla, USB logic registers 12a, l/0 logic registers 13a, and
`trace register 50.
`
`MR (memory read): tells the USB logic 12, 110 logic 13,
`and controller 5 that the microprocessor 9 wishes to
`read data from data RAM 4; and
`
`From the Controller 5:
`
`Trace register 50 of system bus logic 15 has two status bits
`(see FIG. 2) that can be read or written to by using the
`65 previously mentioned command structure, control of the
`USB microcontroller development system 100 can be facili(cid:173)
`tated by either PC 7 or microprocessor 9 which have access
`
`

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`US 6,338,109 Bl
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`10
`
`8
`The interface to a USB host computer and USB device
`under development will now be described.
`A USB host computer 16 is connected to USB interface
`12b of USB logic 12 via USB 17. USB interface 12b
`5 complies with the USB standard. The USB logic 12 decodes
`addresses on the system bus 10, allowing microprocessor 9
`or controller 5 to read or write contents of the USB logic
`registers 12a via the command structure, as previously
`described.
`Sensors, potentiometer, motors, LEDs, memories, data
`collecting or other input output devices of an 1!0 device 18
`are connected to 1!0 interface 13b via 1!0 ports 19. The 1!0
`logic 13 decodes addresses on the system bus 10, allowing
`microprocessor 9 or controller 5 to read or write contents of
`15 the 1/0 logic registers 13a via the command structure, as
`previously described.
`As an example, the USB microcontroller development
`system 100 could be used to debug firmware for a USB
`mouse or joystick, etc. In this case, the mouse or joystick
`sensors, potentiometer, etc. would be attached to 1!0 inter(cid:173)
`face 13b via 1!0 ports 19, and the USB host computer 16
`would be attached to USB interface 12b via USB 17. The
`firmware could be loaded from PC 7 to instruction RAM 2
`by writing to the system state registers lla and then
`debugged using the trace register 50 function and the ability
`to read/modify the microcontroller system state, as pre vi-
`ously described. In this way, the USB mouse or joystick
`function etc. could implemented to run on USB host com(cid:173)
`puter 16 via the USB microcontroller development system
`100.
`The present invention may be implemented via a Hard(cid:173)
`ware Description Language, as previously described.
`As an example, the writing operation of the system state
`registers lla can be implemented in HDL with statements
`such as:
`
`always @ (posedge REGW)
`begin
`case (LA)
`'rA:
`'rTl:
`'rT2:
`'rDSP:
`'rPSP:
`'rPCL:
`endcase
`
`a~ DI;
`t1 ~ DI;
`t2 ~ DI;
`dsp ~ DI;
`psp ~ DI;
`pel~ DI;
`
`end
`
`and mapping of the system state registers lla can be
`50 implemented in HDL with statements such as:
`
`7
`to data RAM 4, system state registers lla, and trace register
`50 via the command structure of Table A
`FIG. 2. is a bit-diagram of a trace register 50 provided in
`system bus logic 15 to implement the above function. The
`contents of the trace register 50 can be modified by the
`microprocessor 9 or the PC 7 via the command structure of
`Table A RUN 51 (bit 0) of trace register 50, if set (bit 0=1),
`causes the microprocessor 9 to execute instructions from
`instruction RAM 2, and if reset or cleared (bit 0=0), causes
`the microprocessor 9 to stop executing instructions from
`instruction RAM 2. SINGLE STEP 52 (bit 1) of trace
`register 50, along with the RUN 51 control how many
`instructions from instruction RAM 2 microprocessor 9
`executes.
`FIG. 3. is a logic flow diagram showing the RUN/
`SINGLE STEP operations outlined above.
`At step 100 the microprocessor 9 is stopped (RUN 51=0).
`As long as RUN 51 is set to zero, by either the micropro(cid:173)
`cessor 9 or the controller 5, the microprocessor will not
`execute instructions in instruction RAM 2. However, if RUN
`51 is set to one, by the controller 5, the logic flow goes to 20
`step 200.
`At step 200 one instruction is executed by microprocessor
`9 from instruction RAM 2 and the logic flows to step 300.
`At step 300 the contents of the SINGLE STEP 52 is
`checked. If SINGLE STEP 52 is set to zero (SINGLE STEP 25
`52=0), by either the microprocessor 9 or the controller 5,
`single step mode is not being selected and the logic flows
`back to step 100 where steps 100--300 are executed until
`either the microprocessor 9 or the controller 5 sets RUN 51
`to zero causing the microprocessor 9 to stop executing 30
`instructions from instruction RAM 2. If SINGLE STEP 52
`is set to one (SINGLE STEP 52=1), by either the micropro(cid:173)
`cessor 9 or the controller 5, single step mode is being
`selected and the logic flows to step 400.
`At step 400 RUN 51 is set to zero, the logic flows to step 35
`100, and the microprocessor 9 is stopped at step 100 since
`RUN 51 was set to zero at step 400.
`In this way, during single step mode only one instruction
`is executed at steps 100-400, the microprocessor 9 is
`stopped at step 100 since RUN 51 is set to zero at step 400, 40
`and the PC 7 must issue an 1!0 write command to set RUN
`51 to one at step 100 in order for microprocessor 9 to execute
`the next instruction from instruction RAM 2. If single step
`mode is not set, then microprocessor 9 continuously
`executes instructions from instruction RAM 2 until either 45
`the microprocessor 9 itself or the PC 7 issues a write data
`byte command to clear RUN 51 to zero. At any time the PC
`7 can modify/read the USB microcontroller system state, as
`described previously, to assist in debugging firmware stored
`in instruction RAM 2.
`In addition, since PC 7 can write the system state registers
`lla of microprocessor 9, as described previously, which
`include the program counter (not shown) which is the
`address of the instruction RAM 2, an instruction register (not
`shown) which holds the data corresponding to the program 55
`counter, PC 7 can be used to load firmware into instruction
`RAM 2 for execution by microprocessor 9.
`The program counter holds the address of instruction
`RAM 2 and instruction register holds the data corresponding
`to the program counter. Thus, by PC 7 writing to the
`program counter and the instruction register and the
`sequencer logic 34 issuing a write command to instruction
`RAM 2, the entire contents of instruction RAM 2 may be
`written to by PC 7. Similarly, by writing an address to the
`program counter and the sequencer logic 34 issuing a read
`command to instruction RAM 2, the entire contents of
`instruction RAM 2 may be read.
`
`always @ (LA or a or t1 or t2 or ID or IR or dsp or psp or
`pel or pch)
`begin
`#5;
`case (LA)
`'rA:
`'rT1:
`'rT2:
`'rDSP:
`'rPSP:
`'rPCL:
`'rPCH:
`'riD:
`endcase
`
`LD ~a;
`LD ~ tl;
`LD ~ t2;
`LD ~ dsp;
`LD ~ psp;
`LD ~pel;
`LD ~ pch;
`LD ~ ID;
`
`end
`
`60
`
`65
`
`

`
`US 6,338,109 Bl
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`9
`and HDL statements such as:
`
`assign #1 regSelect ~ (DA[7:3] ~~ 5'b1110);
`assign #1 idSelect ~ (DA[7:3] ~~ 5'b1111);
`
`implement the address decode for the system state registers
`lla and data RAM 4.
`In the present invention, HDL implemented processes are 10
`used in designing various components of the USB micro(cid:173)
`controller 8 to achieve the various objects of the invention.
`The various components of the USB microcontroller 8,
`when appropriately programmed in HDL, are mapped to
`FPGAs and packaged onto a single printed circuit board
`along with minimal additional logic such as EEPROMs and 15
`RAM.
`Although in the preferred embodiment the USB micro(cid:173)
`controller 8 includes several FPGAs, RAM and EEPROMs
`packaged onto a circuit board, this invention may be imple(cid:173)
`mented using a conventional general purpose digital com- 20
`puter or microprocessor programmed according to the teach(cid:173)
`ings of the p