Chapter 15. EZ-USB FX Registers
`
`15.1 Introduction
`
`This section describes the EZ-USB FX registers in the order they appear in the EZ-USB FX mem-
`ory map. The registers are named according to the following conventions.
`
`Most registers deal with endpoints. The general register format is DDDnFFF, where:
`
`DDD
`
`is endpoint direction, IN or OUT with respect to the USB host.
`
`n
`
`is the endpoint number, where:
`
`“ 07” refers to endpoints 0-7 as a group.
`
`0-7 refers to each individual BULK/INTERRUPT/CONTROL endpoint.
`
`“ ISO” indicates isochronous endpoints as a group.
`
`FFF
`
`is the function, where:
`
`CS is a control and status register
`
`IRQ is an Interrupt Request Bit
`
`IE is an Interrupt Enable Bit
`
`BC, BCL, and BCH are byte count registers. BC is used for single byte counts, and
`BCL/H are used as the low and high bytes of 16-bit byte counts.
`
`DATA is a single-register access to a FIFO.
`
`BUF is the start address of a buffer.
`
`15.1.1 Example Register Formats
`
`IN7BC is the Endpoint 7 IN byte count.
`
`Chapter 15. EZ-USB FX Registers
`
`Page 15-1
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`Exhibit 2032 - Page 295 of 435
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`
`15.1 Introduction
`
`This section describes the EZ-USB FX registers in the order they appear in the EZ-USB FX mem-
`ory map. The registers are named according to the following conventions.
`
`Most registers deal with endpoints. The general register format is DDDnFFF, where:
`
`DDD
`
`is endpoint direction, IN or OUT with respect to the USB host.
`
`n
`
`is the endpoint number, where:
`
`“ 07” refers to endpoints 0-7 as a group.
`
`0-7 refers to each individual BULK/INTERRUPT/CONTROL endpoint.
`
`“ ISO” indicates isochronous endpoints as a group.
`
`FFF
`
`is the function, where:
`
`CS is a control and status register
`
`IRQ is an Interrupt Request Bit
`
`IE is an Interrupt Enable Bit
`
`BC, BCL, and BCH are byte count registers. BC is used for single byte counts, and
`BCL/H are used as the low and high bytes of 16-bit byte counts.
`
`DATA is a single-register access to a FIFO.
`
`BUF is the start address of a buffer.
`
`15.1.1 Example Register Formats
`
`IN7BC is the Endpoint 7 IN byte count.
`
`Chapter 15. EZ-USB FX Registers
`
`Page 15-1
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`Exhibit 2032 - Page 295 of 435
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`
`EZ-USB FX Technical Reference Manual
`
`OUT07IRQ is the register containing interrupt request bits for OUT endpoints 0-7.
`
`INISOVAL contains valid bits for the isochronous IN endpoints (EP8IN-EP15IN).
`
`15.1.2 Other Conventions
`
`USB
`
`Indicates a global (not endpoint-specific) USB function.
`
`ADDR
`
`Is an address.
`
`VAL
`
`Means valid.
`
`FRAME Is a frame count.
`
`PTR
`
`Is an address pointer.
`
`Register Name
`
`Register Function
`
`Address
`
`b7
`
`b6
`
`b5
`
`b4
`
`b3
`
`b2
`
`b1
`
`b0
`
`bitname
`
`bitname
`
`bitname
`
`bitname
`
`bitname
`
`bitname
`
`bitname
`
`bitname
`
`R, W access R, W access R, W access R, W access R, W access R, W access R, W access R, W access
`Default val
`Default val
`Default val
`Default val
`Default val
`Default val
`Default val
`Default val
`
`Figure 15-1. Register Description Format
`
`Figure 15-1. illustrates the register description format used in this chapter.
`
`The top line shows the register name, functional description, and address in the EZ-USB
`FX memory.
`
`The second line shows the bit position in the register.
`
`The third line shows the name of each bit in the register.
`
`The fourth line shows 8051 accessibility: R(ead), W(rite), or R/W.
`
`The fifth line shows the default value. These values apply after a Power-On-Reset (POR).
`
`Page 15-2
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`EZ-USB FX Technical Reference Manual v1.2
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`Exhibit 2032 - Page 296 of 435
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`
`
`15.2 Slave FIFO Registers
`
`15.2.1 FIFO A Read Data
`
`AINDATA
`
`FIFO A Read Data
`
`7800
`
`b7
`
`D7
`
`R
`x
`
`b6
`
`D6
`
`R
`x
`
`b5
`
`D5
`
`R
`x
`
`b4
`
`D4
`
`R
`x
`
`b3
`
`D3
`
`R
`x
`
`b2
`
`D2
`
`R
`x
`
`b1
`
`D1
`
`R
`x
`
`b0
`
`D0
`
`R
`x
`
`Figure 15-2. FIFO A Read Data
`
`Each time the 8051 reads a byte from this register, the A-IN FIFO advances to the next byte in the
`FIFO and the AINBC (byte count) decrements. Reading this register when there is one byte
`remaining in the A-IN FIFO sets the A-IN FIFO Empty Flag (AINEF, in ABINCS.4), which causes
`an interrupt request on INT4 (Table 2). Reading this register when the A-IN FIFO is empty returns
`indeterminate data and has no effect on the FIFO flags byte counts. For more information, see
`Section 7.2.1. "FIFO A Read Data".
`
`15.2.2 A-IN FIFO Byte Count
`
`AINBC
`
`A-IN FIFO Byte Count
`
`7801
`
`b7
`
`0
`
`R
`0
`
`b6
`
`D6
`
`R
`0
`
`b5
`
`D5
`
`R
`0
`
`b4
`
`D4
`
`R
`0
`
`b3
`
`D3
`
`R
`0
`
`b2
`
`D2
`
`R
`0
`
`b1
`
`D1
`
`R
`0
`
`b0
`
`D0
`
`R
`0
`
`Figure 15-3. A-IN FIFO Byte Count
`
`This count reflects the number of bytes remaining in the A-IN FIFO. Valid byte counts are 0-64.
`When non-zero, every byte written by outside logic increments this count, and every 8051 read of
`AINDATA decrements this count. If AINBC is zero, an 8051 read of AINDATA returns indeterminate
`data and results in the byte count in AINBC remaining at zero. Data bytes should never be written
`to the FIFO from outside logic when the AINFULL flag is HI. For more information, see Section
`7.2.2. "A-IN FIFO Byte Count".
`
`Chapter 15. EZ-USB FX Registers
`
`Page 15-3
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`Exhibit 2032 - Page 297 of 435
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`EZ-USB FX Technical Reference Manual
`
`15.2.3 A-IN FIFO Programmable Flag
`
`AINPF
`
`A-IN FIFO Programmable Flag
`
`7802
`
`b7
`
`LTGT
`
`R/W
`0
`
`b6
`
`D6
`
`R/W
`0
`
`b5
`
`D5
`
`R/W
`0
`
`b4
`
`D4
`
`R/W
`0
`
`b3
`
`D3
`
`R/W
`0
`
`b2
`
`D2
`
`R/W
`0
`
`b1
`
`D1
`
`R/W
`0
`
`b0
`
`D0
`
`R/W
`0
`
`Figure 15-4. A-IN FIFO Programmable Flag
`
`This register controls the sense and value for the internal A-IN FIFO programmable flag. This flag
`is testable by the 8051. For more information including a list of bit definitions for this register, see
`Section 7.2.3. "A-IN FIFO Programmable Flag".
`
`15.2.4 A-IN FIFO Pin Programmable Flag
`
`AINPFPIN
`
`A-IN FIFO Pin Programmable Flag
`
`7803
`
`b7
`
`LTGT
`
`R/W
`0
`
`b6
`
`D6
`
`R/W
`0
`
`b5
`
`D5
`
`R/W
`0
`
`b4
`
`D4
`
`R/W
`0
`
`b3
`
`D3
`
`R/W
`0
`
`b2
`
`D2
`
`R/W
`0
`
`b1
`
`D1
`
`R/W
`0
`
`b0
`
`D0
`
`R/W
`0
`
`Figure 15-5. A-IN FIFO Pin Programmable Flag
`
`This register controls the sense and value for the A-IN FIFO Programmable Flag that appears on
`the AINFLAG pin. This pin is used by external logic to regulate external writes to the A-IN FIFO.
`The AINPFPIN Register is programmed with the same data format as the previous register,
`AINPF. The only operational difference is that the flag drives a hardware pin rather than existing as
`an internal register bit. For more information, see Section 7.2.3.3. "A-IN FIFO Pin Programmable
`Flag".
`
`Page 15-4
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`EZ-USB FX Technical Reference Manual v1.2
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`Exhibit 2032 - Page 298 of 435
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`
`
`15.2.5 B-IN FIFO Read Data
`
`BINDATA
`
`B-IN FIFO Read Data
`
`7805
`
`b7
`
`D7
`
`R
`x
`
`b6
`
`D6
`
`R
`x
`
`b5
`
`D5
`
`R
`x
`
`b4
`
`D4
`
`R
`x
`
`b3
`
`D3
`
`R
`x
`
`b2
`
`D2
`
`R
`x
`
`b1
`
`D1
`
`R
`x
`
`b0
`
`D0
`
`R
`x
`
`Figure 15-6. B-IN FIFO Read Data
`
`Each time the 8051 reads a byte from this register, the B-IN FIFO advances to the next byte in the
`FIFO and the BINBC (byte count) decrements. Reading this register when there is one byte
`remaining in the FIFO sets the B-IN FIFO Empty Flag (BINEF, in ABINCS.1), which causes an
`INT4 Request. Reading this register when the B-IN FIFO is empty returns indeterminate data and
`has no effect on the FIFO flags or byte count. For more information, see Section 7.2.4. "B-IN FIFO
`Read Data".
`
`15.2.6 B-IN FIFO Byte Count
`
`BINBC
`
`B-IN FIFO Byte Count
`
`7806
`
`b7
`
`0
`
`R
`0
`
`b6
`
`D6
`
`R
`0
`
`b5
`
`D5
`
`R
`0
`
`b4
`
`D4
`
`R
`0
`
`b3
`
`D3
`
`R
`0
`
`b2
`
`D2
`
`R
`0
`
`b1
`
`D1
`
`R
`0
`
`b0
`
`D0
`
`R
`0
`
`Figure 15-7. B-IN FIFO Byte Count
`
`This count reflects the number of bytes remaining in the B-IN FIFO. Valid byte counts are 0-64.
`When non-zero, every byte written by outside logic increments this count, and every 8051 read of
`BINDATA decrements this count. If BINBC is zero, an 8051 read of BINDATA returns indeterminate
`data and results in the byte count in BINBC remaining at zero. Data bytes should never be written
`to the FIFO from outside logic when the BINFULL flag is HI. For more information, see Section
`7.2.5. "B-IN FIFO Byte Count."
`
`Chapter 15. EZ-USB FX Registers
`
`Page 15-5
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`Exhibit 2032 - Page 299 of 435
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`EZ-USB FX Technical Reference Manual
`
`15.2.7 B-IN FIFO Programmable Flag
`
`BINPF
`
`B-IN FIFO Programmable Flag
`
`7807
`
`b7
`
`LTGT
`
`R/W
`0
`
`b6
`
`D6
`
`R/W
`0
`
`b5
`
`D5
`
`R/W
`0
`
`b4
`
`D4
`
`R/W
`0
`
`b3
`
`D3
`
`R/W
`0
`
`b2
`
`D2
`
`R/W
`0
`
`b1
`
`D1
`
`R/W
`0
`
`b0
`
`D0
`
`R/W
`0
`
`Figure 15-8. B-IN FIFO Programmable Flag
`
`This register controls the sense and value for the internal B-IN FIFO programmable flag. For more
`information including a list of bit descriptions, see Section 7.2.6. "B-IN FIFO Programmable Flag."
`
`15.2.8 B-IN FIFO Pin Programmable Flag
`
`BINPFPIN
`
`B-IN FIFO Pin Programmable Flag
`
`7808
`
`b7
`
`LTGT
`
`R/W
`0
`
`b6
`
`D6
`
`R/W
`0
`
`b5
`
`D5
`
`R/W
`0
`
`b4
`
`D4
`
`R/W
`0
`
`b3
`
`D3
`
`R/W
`0
`
`b2
`
`D2
`
`R/W
`0
`
`b1
`
`D1
`
`R/W
`0
`
`b0
`
`D0
`
`R/W
`0
`
`Figure 15-9. B-IN FIFO Pin Programmable Flag
`
`This register controls the sense and value for the B-IN FIFO Programmable Flag that appears on
`the BINFLAG pin. This pin is used by external logic to regulate external writes to the B-IN FIFO.
`The BINPFPIN Register is programmed with the same data format as the previous register,
`BINPF. The only operational difference is that the flag drives a hardware pin rather than existing as
`an internal register bit. For more information see Section 7.2.7. "B-IN FIFO Pin Programmable
`Flag."
`
`Page 15-6
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`EZ-USB FX Technical Reference Manual v1.2
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`Exhibit 2032 - Page 300 of 435
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`
`
`15.2.9 Input FIFOs A/B Toggle CTL and Flags
`
`ABINTCS
`
`Input FIFOs A/B Toggle CTL and Flags
`
`780A
`
`b7
`
`b6
`
`b5
`
`b4
`
`b3
`
`b2
`
`b1
`
`b0
`
`INTOG
`
`INSEL
`
`AINPF
`
`AINEF
`
`AINFF
`
`BINPF
`
`BINEF
`
`BINFF
`
`R/W
`0
`
`R/W
`1
`
`R
`0
`
`R
`1
`
`R
`0
`
`R
`0
`
`R
`1
`
`R
`0
`
`Figure 15-10. Input FIFOs A/B Toggle CTL and Flags
`
`For information about this register, including a list of bit descriptions, see Section 7.2.8. "Input
`FIFOs A/B Toggle CTL and Flags."
`
`15.2.10 Input FIFOs A/B Interrupt Enables
`
`ABINIE
`
`Input FIFOs A/B Interrupt Enables
`
`780B
`
`b7
`
`0
`
`R/W
`0
`
`b6
`
`0
`
`R/W
`0
`
`b5
`
`b4
`
`b3
`
`b2
`
`b1
`
`b0
`
`AINPFIE
`
`AINEFIE
`
`AINFFIE
`
`BINPFIE
`
`BINEFIE
`
`BINFFIE
`
`R/W
`0
`
`R/W
`0
`
`R/W
`0
`
`R/W
`0
`
`R/W
`0
`
`R/W
`0
`
`Figure 15-11. Input FIFOs A/B Interrupt Enables
`
`For information about this register, including a list of bit descriptions, see Section 7.2.9. "Input
`FIFOs A/B Interrupt Enables."
`
`15.2.11 Input FIFOs A/B Interrupt Requests
`
`ABINIRQ
`
`Input FIFOs A/B Interrupt Enables
`
`780C
`
`b7
`
`0
`
`R/W
`x
`
`b6
`
`0
`
`R/W
`x
`
`b5
`
`b4
`
`b3
`
`b2
`
`b1
`
`b0
`
`AINPFIR
`
`AINEFIR
`
`AINFFIR
`
`BINPFIR
`
`BINEFIR
`
`BINFFIR
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`Figure 15-12. Input FIFOs A/B Interrupt Requests
`
`Chapter 15. EZ-USB FX Registers
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`Page 15-7
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`Exhibit 2032 - Page 301 of 435
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`EZ-USB FX Technical Reference Manual
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`For information about the ABINIRQ Register, including a list of bit descriptions, see Section 7.2.10.
`"Input FIFOs A/B Interrupt Requests."
`
`15.2.12 FIFO A Write Data
`
`AOUTDATA
`
`FIFO A Write Data
`
`780E
`
`b7
`
`D7
`
`R
`x
`
`b6
`
`D6
`
`R
`x
`
`b5
`
`D5
`
`R
`x
`
`b4
`
`D4
`
`R
`x
`
`b3
`
`D3
`
`R
`x
`
`b2
`
`D2
`
`R
`x
`
`b1
`
`D1
`
`R
`x
`
`b0
`
`D0
`
`R
`x
`
`Figure 15-13. FIFO A Write Data
`
`A-OUT FIFO Write Data. Each time the 8051/DMA writes a byte to this register, the A-OUT FIFO
`advances to the next open position in the FIFO and the AOUTBC (byte count) increments. Writing
`this register when there are 63 bytes remaining in the A-OUT FIFO sets the A-FIFO Full Flag
`(AOUTFF, in ABOUTCS.3), which causes an INT4 Request. Writing this register when the A-OUT
`FIFO is full (64 bytes) does not update the FIFO or byte count, and has no effect on the FIFO flags
`or byte count. For more information, see Section 7.2.11. "FIFO A Write Data."
`
`15.2.13 A-OUT FIFO Byte Count
`
`AOUTBC
`
`A-OUT FIFO Byte Count
`
`780F
`
`b7
`
`D7
`
`R
`0
`
`b6
`
`D6
`
`R
`0
`
`b5
`
`D5
`
`R
`0
`
`b4
`
`D4
`
`R
`0
`
`b3
`
`D3
`
`R
`0
`
`b2
`
`D2
`
`R
`0
`
`b1
`
`D1
`
`R
`0
`
`b0
`
`D0
`
`R
`0
`
`Figure 15-14. Input FIFOs A/B Interrupt Requests
`
`This count reflects the number of bytes remaining in the A-OUT FIFO. Valid byte counts are 0-64.
`When non-zero, every byte read by outside logic decrements this count, and every 8051 write of
`AOUTDATA increments this count. If AOUTBC is zero, reading a data byte by outside logic returns
`indeterminate data and results in the byte count in AOUTBC remaining at zero. For more informa-
`tion, see Section 7.2.11.1. "A-OUT FIFO Byte Count."
`
`Page 15-8
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`EZ-USB FX Technical Reference Manual v1.2
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`Exhibit 2032 - Page 302 of 435
`
`
`
`15.2.14 A-OUT FIFO Programmable Flag
`
`AOUTPF
`
`A-OUT FIFO Programmable Flag
`
`7810
`
`b7
`
`LTGT
`
`R/W
`1
`
`b6
`
`D6
`
`R/W
`0
`
`b5
`
`D5
`
`R/W
`1
`
`b4
`
`D4
`
`R/W
`0
`
`b3
`
`D3
`
`R/W
`0
`
`b2
`
`D2
`
`R/W
`0
`
`b1
`
`D1
`
`R/W
`0
`
`b0
`
`D0
`
`R/W
`0
`
`Figure 15-15. Input FIFOs A/B Interrupt Requests
`
`This register controls the sense and value for the internal A-OUT FIFO Programmable Flag. The
`internal flag may be tested by the 8051, and/or enabled to cause an INT4 Interrupt Request. The
`8051 tests the internal FIFO programmable flag by reading the AOUTPF Bit in ABOUTCS.5 (regis-
`ter at 0x7818). For more information including a list of bit descriptions, see Section 7.2.12. "A-OUT
`FIFO Programmable Flag."
`
`15.2.15 A-OUT FIFO Pin Programmable Flag
`
`AOUTPFPIN
`
`A-OUT FIFO Pin Programmable Flag
`
`7811
`
`b7
`
`LTGT
`
`R/W
`1
`
`b6
`
`D6
`
`R/W
`1
`
`b5
`
`D5
`
`R/W
`0
`
`b4
`
`D4
`
`R/W
`0
`
`b3
`
`D3
`
`R/W
`0
`
`b2
`
`D2
`
`R/W
`0
`
`b1
`
`D1
`
`R/W
`0
`
`b0
`
`D0
`
`R/W
`0
`
`Figure 15-16. A-OUT FIFO Pin Programmable Flag
`
`This register controls the sense and value for the A-OUT FIFO Programmable Flag that appears
`on the AOUTFLAG pin. This pin is used by external logic to regulate external reads from the A-
`OUT FIFO. The AOUTPFPIN Register is programmed with the same data format as the previous
`register, AOUTPF. The only operational difference is that the flag drives a hardware pin rather than
`existing as an internal register bit. For more information, see Section 7.2.13. "A-OUT FIFO Pin
`Programmable Flag."
`
`Chapter 15. EZ-USB FX Registers
`
`Page 15-9
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`Exhibit 2032 - Page 303 of 435
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`
`
`EZ-USB FX Technical Reference Manual
`
`15.2.16 B-OUT FIFO Write Data
`
`BOUTDATA
`
`B-OUT FIFO Write Data
`
`7813
`
`b7
`
`D7
`
`R
`x
`
`b6
`
`D6
`
`R
`x
`
`b5
`
`D5
`
`R
`x
`
`b4
`
`D4
`
`R
`x
`
`b3
`
`D3
`
`R
`x
`
`b2
`
`D2
`
`R
`x
`
`b1
`
`D1
`
`R
`x
`
`b0
`
`D0
`
`R
`x
`
`Figure 15-17. B-OUT FIFO Write Data
`
`Each time the 8051/DMA writes a byte to this register, the B-OUT FIFO advances to the next open
`position in the FIFO and the BOUTBC (Byte count) increments. Writing this register when there
`are 63 bytes remaining in the B-OUT FIFO sets the B-FIFO Full Flag (BOUTFF, in ABOUTCS.0),
`which causes an INT4 Interrupt Request. Writing this register when the B-OUT FIFO is full (64
`bytes) does not update the FIFO or byte count, and has no effect on the FIFO flags or byte count.
`For more information, see Section 7.2.14. "B-OUT FIFO Write Data."
`
`15.2.17 B-OUT FIFO Byte Count
`
`BOUTBC
`
`B-OUT FIFO Byte Count
`
`7814
`
`b7
`
`D7
`
`R
`0
`
`b6
`
`D6
`
`R
`0
`
`b5
`
`D5
`
`R
`0
`
`b4
`
`D4
`
`R
`0
`
`b3
`
`D3
`
`R
`0
`
`b2
`
`D2
`
`R
`0
`
`b1
`
`D1
`
`R
`0
`
`b0
`
`D0
`
`R
`0
`
`Figure 15-18. B-OUT FIFO Byte Count
`
`This count reflects the number of bytes remaining in the B-OUT FIFO. Valid byte counts are 0-64.
`When non-zero, every byte read by outside logic decrements this count, and every 8051 write of
`BOUTDATA increments this count. If BOUTBC is zero, reading a data byte by outside logic returns
`indeterminate data and results in the byte count in BOUTBC remaining at zero. For more informa-
`tion, see Section 7.2.15. "B-OUT FIFO Byte Count."
`
`Page 15-10
`
`EZ-USB FX Technical Reference Manual v1.2
`
`Exhibit 2032 - Page 304 of 435
`
`
`
`15.2.18 B-OUT FIFO Programmable Flag
`
`BOUTPF
`
`B-OUT FIFO Programmable Flag
`
`7815
`
`b7
`
`LTGT
`
`R/W
`1
`
`b6
`
`D6
`
`R/W
`0
`
`b5
`
`D5
`
`R/W
`1
`
`b4
`
`D4
`
`R/W
`0
`
`b3
`
`D3
`
`R/W
`0
`
`b2
`
`D2
`
`R/W
`0
`
`b1
`
`D1
`
`R/W
`0
`
`b0
`
`D0
`
`R/W
`0
`
`Figure 15-19. B-OUT FIFO Programmable Flag
`
`This register controls the sense and value for the internal B-OUT FIFO Programmable Flag. The
`internal flag may be tested by the 8051, and/or enabled to cause an INT4 Interrupt Request. For
`more information including a list of bit descriptions, see Section 7.2.16. "B-OUT FIFO Programma-
`ble Flag."
`
`15.2.19 B-OUT FIFO Pin Programmable Flag
`
`BOUTPFPIN
`
`B-OUT FIFO Pin Programmable Flag
`
`7816
`
`b7
`
`LTGT
`
`R/W
`0
`
`b6
`
`D6
`
`R/W
`0
`
`b5
`
`D5
`
`R/W
`0
`
`b4
`
`D4
`
`R/W
`0
`
`b3
`
`D3
`
`R/W
`0
`
`b2
`
`D2
`
`R/W
`0
`
`b1
`
`D1
`
`R/W
`0
`
`b0
`
`D0
`
`R/W
`0
`
`Figure 15-20. B-OUTFIFO Pin Programmable Flag
`
`This register controls the sense and value for the B-OUT FIFO Programmable Flag that appears
`on the BOUTFLAG pin. This pin is used by external logic to regulate external reads from the B-
`OUT FIFO. The BOUTPFPIN Register is programmed with the same data format as the previous
`register, BOUTPF. The only operational difference is that the flag drives a hardware pin rather than
`existing as an internal register bit. For more information including a list of bit descriptions, see Sec-
`tion 7.2.17. "B-OUT FIFO Pin Programmable Flag."
`
`Chapter 15. EZ-USB FX Registers
`
`Page 15-11
`
`Exhibit 2032 - Page 305 of 435
`
`
`
`EZ-USB FX Technical Reference Manual
`
`15.2.20 Output FIFOs A/B Toggle CTL and Flags
`
`ABOUTCS
`
`Output FIFOs A/B Toggle CTL and Flags
`
`7818
`
`b7
`
`b6
`
`b5
`
`b4
`
`b3
`
`b2
`
`b1
`
`b0
`
`OUTINTOG OUTSEL
`
`AOUTPF
`
`AOUTEF
`
`AOUTFF
`
`BOUTPF
`
`BOUTEF
`
`BOUTFF
`
`R/W
`0
`
`R/W
`1
`
`R/W
`0
`
`R/W
`1
`
`R/W
`0
`
`R/W
`0
`
`R/W
`1
`
`R/W
`0
`
`Figure 15-21. Output FIFOs A/B Toggle CTL and Flags
`
`For information about this register, including a list of bit descriptions, see Section 7.2.18. "Output
`FIFOs A/B Toggle CTL and Flags."
`
`15.2.21 Output FIFOs A/B Interrupt Enables
`
`ABOUTIE
`
`Output FIFOs A/B Interrupt Enables
`
`7819
`
`b7
`
`0
`
`R/W
`0
`
`b6
`
`0
`
`R/W
`0
`
`b5
`
`b4
`
`b3
`
`b2
`
`b1
`
`b0
`
`AOUTPFIE AOUTEFIE AOUTFFIE BOUTPFIE BOUTEFIE BOUTFFIE
`
`R/W
`0
`
`R/W
`0
`
`R/W
`0
`
`R/W
`0
`
`R/W
`0
`
`R/W
`0
`
`Figure 15-22. Output FIFOs A/B Interrupt Enables
`
`For information about this register, including a list of bit descriptions, see Section 7.2.19. "Output
`FIFOs A/B Interrupt Enables."
`
`15.2.22 Output FIFOs A/B Interrupt Requests
`
`ABOUTIRQ
`
`Output FIFOs A/B Interrupt Requests
`
`781A
`
`b7
`
`0
`
`R/W
`x
`
`b6
`
`0
`
`R/W
`x
`
`b5
`
`b4
`
`b3
`
`b2
`
`b1
`
`b0
`
`AOUTPFIR AOUTEFIR AOUTFFIR BOUTPFIR BOUTEFIR BOUTFFIR
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`Figure 15-23. Output FIFOs A/B Interrupt Requests
`
`Page 15-12
`
`EZ-USB FX Technical Reference Manual v1.2
`
`Exhibit 2032 - Page 306 of 435
`
`
`
`For information about this register, including a list of bit descriptions, see Section 7.2.20. "Output
`FIFOs A/B Interrupt Requests."
`
`15.2.23 FIFO A/B Setup
`
`ABSETUP
`
`FIFO A/B Setup
`
`b7
`
`0
`
`R/W
`0
`
`b6
`
`0
`
`R/W
`0
`
`b5
`
`b4
`
`ASYNC
`
`DBLIN
`
`R/W
`0
`
`R/W
`0
`
`b3
`
`0
`
`R/W
`0
`
`b2
`
`OUTDLY
`
`R/W
`0
`
`b1
`
`0
`
`R/W
`0
`
`Figure 15-24. FIFO A/B Setup
`
`781C
`
`b0
`
`DBLOUT
`
`R/W
`0
`
`For information about this register, including a list of bit descriptions, see Section 7.2.21. "FIFO A/
`B Setup."
`
`15.2.24 FIFO A/B Control Signal Polarities
`
`ABPOLAR
`
`FIFO A/B Control Signal Polarities
`
`781D
`
`b7
`
`0
`
`R/W
`x
`
`b6
`
`0
`
`R/W
`x
`
`b5
`
`BOE
`
`R/W
`x
`
`b4
`
`AOE
`
`R/W
`x
`
`b3
`
`b2
`
`b1
`
`b0
`
`SLRD
`
`SLWR
`
`ASEL
`
`BSEL
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`Figure 15-25. FIFO A/B Control Signal Polarities
`
`These bits define the pin polarities for the indicated signals. The 8051 sets a bit LOW for active
`low, and HI for active high. For more information including a list of bit descriptions, see Section
`7.2.22. "FIFO A/B Control Signal Polarities."
`
`Chapter 15. EZ-USB FX Registers
`
`Page 15-13
`
`Exhibit 2032 - Page 307 of 435
`
`
`
`EZ-USB FX Technical Reference Manual
`
`15.2.25 FIFO Flag Reset
`
`ABFLUSH
`
`Reset All FIFO Flags
`
`781E
`
`b7
`
`x
`
`W
`x
`
`b6
`
`x
`
`W
`x
`
`b5
`
`x
`
`W
`x
`
`b4
`
`x
`
`W
`x
`
`b3
`
`x
`
`W
`x
`
`b2
`
`x
`
`W
`x
`
`b1
`
`x
`
`W
`x
`
`b0
`
`x
`
`W
`x
`
`Figure 15-26. FIFO Flag Reset
`
`The 8051 writes any value to this register to reset the FIFO byte counts to zero, effectively flushing
`the FIFOs. Consequently, the byte counts are set to zero, the empty flags are set, and the full flags
`are cleared. Reading this register returns indeterminate data. For more information including a list
`of bit descriptions, see Section 7.2.23. "FIFO Flag Reset."
`
`15.3 Waveform Selector
`
`WFSELECT
`
`Waveform Selector
`
`7824
`
`b7
`
`b6
`
`b5
`
`b4
`
`b3
`
`b2
`
`b1
`
`b0
`
`SINGLEWR0-3
`
`SINGLERD0-3
`
`FIFOWR0-3
`
`FIFORD0-3
`
`W
`x
`
`W
`x
`
`R
`x
`
`R
`x
`
`W
`x
`
`W
`x
`
`R
`x
`
`R
`x
`
`Figure 15-27. Waveform Selector
`
`For detailed information, see Chapter 8. "General Programmable Interface (GPIF)".
`
`Page 15-14
`
`EZ-USB FX Technical Reference Manual v1.2
`
`Exhibit 2032 - Page 308 of 435
`
`
`
`15.4 GPIF Done, GPIF IDLE Drive Mode
`
`IDLECS
`
`GPIF Done, GPIF IDLE Drive Mode
`
`7825
`
`b7
`
`DONE
`
`R/W
`x
`
`b6
`
`0
`
`R/W
`x
`
`b5
`
`0
`
`R/W
`x
`
`b4
`
`0
`
`R/W
`x
`
`b3
`
`0
`
`R/W
`x
`
`b2
`
`0
`
`R/W
`x
`
`b1
`
`0
`
`R/W
`x
`
`b0
`
`IDLEDRV
`
`R/W
`x
`
`Figure 15-28. GPIF Done, GPIF IDLE Drive Mode
`
`For detailed information, see Chapter 8. "General Programmable Interface (GPIF)".
`
`15.5 Inactive Bus, CTL States
`
`IDLECTLOUT
`
`Inactive Bus, CTL States
`
`7826
`
`b7
`
`IOE3
`
`R/W
`x
`
`b6
`
`b5
`
`b4
`
`b3
`
`IOE2
`
`IOE1/CTL5 IOE0/CTL4
`
`CTL3
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`b2
`
`CTL2
`
`R/W
`x
`
`b1
`
`CTL1
`
`R/W
`x
`
`b0
`
`CTL0
`
`R/W
`x
`
`Figure 15-29. Inactive Bus, CTL States
`
`CTLOUTCFG
`
`CTLOUT Pin Drive
`
`b7
`
`TRICTL
`
`R/W
`x
`
`b6
`
`0
`
`R/W
`x
`
`b5
`
`CTL5
`
`R/W
`x
`
`b4
`
`CTL4
`
`R/W
`x
`
`b3
`
`CTL3
`
`R/W
`x
`
`b2
`
`CTL2
`
`R/W
`x
`
`b1
`
`CTL1
`
`R/W
`x
`
`Figure 15-30. CTLOUT Pin Drive
`
`7827
`
`b0
`
`CTL0
`
`R/W
`x
`
`Chapter 15. EZ-USB FX Registers
`
`Page 15-15
`
`Exhibit 2032 - Page 309 of 435
`
`
`
`EZ-USB FX Technical Reference Manual
`
`15.6 GPIF Address LSB
`
`GPIFADRL
`
`GPIF Address Low
`
`782A
`
`b7
`
`x
`
`R/W
`x
`
`b6
`
`x
`
`R/W
`x
`
`b5
`
`A5
`
`R/W
`x
`
`b4
`
`A4
`
`R/W
`x
`
`b3
`
`A3
`
`R/W
`x
`
`b2
`
`A2
`
`R/W
`x
`
`b1
`
`A1
`
`R/W
`x
`
`b0
`
`A0
`
`R/W
`x
`
`Figure 15-31. GPIF Address Low
`
`15.7 FIFO A IN Transaction Count
`
`AINTC
`
`FIFO A IN Transaction Count
`
`782C
`
`b7
`
`FITC
`
`R/W
`x
`
`b6
`
`b5
`
`b4
`
`b3
`
`b2
`
`b1
`
`b0
`
`AINTC6
`
`AINTC5
`
`AINTC4
`
`AINTC3
`
`AINTC2
`
`AINTC1
`
`AINTC0
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`Figure 15-32. FIFO A IN Transaction Count
`
`For detailed information, see Chapter 8. "General Programmable Interface (GPIF)".
`
`Page 15-16
`
`EZ-USB FX Technical Reference Manual v1.2
`
`Exhibit 2032 - Page 310 of 435
`
`
`
`15.8 FIFO A OUT Transaction Count
`
`AOUTTC
`
`FIFO A OUT Transaction Count
`
`782D
`
`b7
`
`b6
`
`b5
`
`b4
`
`b3
`
`b2
`
`b1
`
`b0
`
`FITC
`
`AOUTTC6 AOUTTC5 AOUTTC4 AOUTTC3 AOUTTC2 AOUTTC1 AOUTTC0
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`Figure 15-33. FIFO A OUT Transaction Count
`
`See Chapter 8. "General Programmable Interface (GPIF)" for detailed information.
`
`15.9 FIFO A Transaction Trigger
`
`ATRIG
`
`FIFO A Transaction Trigger
`
`782E
`
`b7
`
`x
`
`R/W
`x
`
`b6
`
`x
`
`R/W
`x
`
`b5
`
`x
`
`R/W
`x
`
`b4
`
`x
`
`R/W
`x
`
`b3
`
`x
`
`R/W
`x
`
`b2
`
`x
`
`R/W
`x
`
`b1
`
`x
`
`R/W
`x
`
`b0
`
`x
`
`R/W
`x
`
`Figure 15-34. FIFO A Transaction Trigger
`
`See Chapter 8. "General Programmable Interface (GPIF)" for detailed information.
`
`Chapter 15. EZ-USB FX Registers
`
`Page 15-17
`
`Exhibit 2032 - Page 311 of 435
`
`
`
`EZ-USB FX Technical Reference Manual
`
`15.10 FIFO B IN Transaction Count
`
`BINTC
`
`FIFO B IN Transaction Count
`
`7830
`
`b7
`
`b6
`
`b5
`
`b4
`
`b3
`
`b2
`
`b1
`
`b0
`
`BINTC7
`
`BINTC6
`
`BINTC5
`
`BINTC4
`
`BINTC3
`
`BINTC2
`
`BINTC1
`
`BINTC0
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`Figure 15-35. FIFO B IN Transaction Count
`
`For detailed information, see Chapter 8. "General Programmable Interface (GPIF)".
`
`15.11 FIFO B OUT Transaction Count
`
`BOUTTC
`
`FIFO B OUT Transaction Count
`
`7831
`
`b7
`
`b6
`
`b5
`
`b4
`
`b3
`
`b2
`
`b1
`
`b0
`
`BOUTTC7 BOUTTC6 BOUTTC5 BOUTTC4 BOUTTC3 BOUTTC2 BOUTTC1 BOUTTC0
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`Figure 15-36. FIFO B OUT Transaction Count
`
`For detailed information, see Chapter 8. "General Programmable Interface (GPIF)".
`
`Page 15-18
`
`EZ-USB FX Technical Reference Manual v1.2
`
`Exhibit 2032 - Page 312 of 435
`
`
`
`15.12 FIFO B Transaction Trigger
`
`BTRIG
`
`FIFO B Transaction Trigger
`
`7832
`
`b7
`
`x
`
`R/W
`x
`
`b6
`
`x
`
`R/W
`x
`
`b5
`
`x
`
`R/W
`x
`
`b4
`
`x
`
`R/W
`x
`
`b3
`
`x
`
`R/W
`x
`
`b2
`
`x
`
`R/W
`x
`
`b1
`
`x
`
`R/W
`x
`
`b0
`
`x
`
`R/W
`x
`
`Figure 15-37. FIFO B Transaction
`
`For detailed information, see Chapter 8. "General Programmable Interface (GPIF)".
`
`15.13 GPIF Data H (16-bit mode only)
`
`SGLDATH
`
`GPIF Data H (16-bit mode only)
`
`7834
`
`b7
`
`D15
`
`R/W
`x
`
`b6
`
`D14
`
`R/W
`x
`
`b5
`
`D13
`
`R/W
`x
`
`b4
`
`D12
`
`R/W
`x
`
`b3
`
`D11
`
`R/W
`x
`
`b2
`
`D10
`
`R/W
`x
`
`b1
`
`D9
`
`R/W
`x
`
`b0
`
`D8
`
`R/W
`x
`
`Figure 15-38. GPIF Data H (16-bit mode only)
`
`15.14 Read or Write GPIF Data L and Trigger Read Transaction
`
`SGLDATLTRIG
`
`R/W GPIF DataL/Trig Rd Transaction
`
`7835
`
`b7
`
`D7
`
`R/W
`x
`
`b6
`
`D6
`
`R/W
`x
`
`b5
`
`D5
`
`R/W
`x
`
`b4
`
`D4
`
`R/W
`x
`
`b3
`
`D3
`
`R/W
`x
`
`b2
`
`D2
`
`R/W
`x
`
`b1
`
`D1
`
`R/W
`x
`
`b0
`
`D0
`
`R/W
`x
`
`Figure 15-39. Read or Write GPIF Data L and Trigger Read Transaction
`
`Chapter 15. EZ-USB FX Registers
`
`Page 15-19
`
`Exhibit 2032 - Page 313 of 435
`
`
`
`EZ-USB FX Technical Reference Manual
`
`15.15 Read GPIF Data L, No Read Transaction Trigger
`
`SGLDATLNTRIG
`
`Rd GPIF Data L/No Trig Rd Transaction
`
`7836
`
`b7
`
`D7
`
`R
`x
`
`b6
`
`D6
`
`R
`x
`
`b5
`
`D5
`
`R
`x
`
`b4
`
`D4
`
`R
`x
`
`b3
`
`D3
`
`R
`x
`
`b2
`
`D2
`
`R
`x
`
`b1
`
`D1
`
`R
`x
`
`b0
`
`D0
`
`R
`x
`
`Figure 15-40. Read GPIF Data L, No Read Transaction Trigger
`
`15.16 Internal READY, Sync/Async, READY Pin States
`
`READY
`
`Internal Rdy, Sync/Async, Rdy Pin States
`
`7838
`
`b7
`
`INTRDY
`
`R/W
`x
`
`b6
`
`SAS
`
`R/W
`x
`
`b5
`
`b4
`
`b3
`
`b2
`
`b1
`
`b0
`
`RDY5
`
`RDY4
`
`RDY3
`
`RDY2
`
`RDY1
`
`RDY0
`
`R
`x
`
`R
`x
`
`R
`x
`
`R
`x
`
`R
`x
`
`R
`x
`
`Figure 15-41. Internal READY, Sync/Async, READY Pin States
`
`15.17 Abort GPIF Cycles
`
`ABORT
`
`Abort GPIF Cycles
`
`7839
`
`b7
`
`x
`
`W
`x
`
`b6
`
`x
`
`W
`x
`
`b5
`
`x
`
`W
`x
`
`b4
`
`x
`
`W
`x
`
`b3
`
`x
`
`W
`x
`
`b2
`
`x
`
`W
`x
`
`b1
`
`x
`
`W
`x
`
`b0
`
`x
`
`W
`x
`
`Figure 15-42. Abort GPIF Cycles
`
`Page 15-20
`
`EZ-USB FX Technical Reference Manual v1.2
`
`Exhibit 2032 - Page 314 of 435
`
`
`
`15.18 General Purpose I/F Interrupt Enable
`
`GENIE
`
`General Purpose I/F Interrupt Enable
`
`783B
`
`b7
`
`0
`
`W
`x
`
`b6
`
`0
`
`W
`x
`
`b5
`
`0
`
`W
`x
`
`b4
`
`0
`
`W
`x
`
`b3
`
`0
`
`W
`x
`
`b2
`
`b1
`
`b0
`
`DMADONE GPIFWF GPIFDONE
`
`W
`x
`
`W
`x
`
`W
`x
`
`Figure 15-43. Generic Interrupt Enable
`
`15.19 Generic Interrupt Request
`
`GENIRQ
`
`Generic Interrupt Request
`
`783C
`
`b7
`
`0
`
`R/W
`x
`
`b6
`
`0
`
`R/W
`x
`
`b5
`
`0
`
`R/W
`x
`
`b4
`
`0
`
`R/W
`x
`
`b3
`
`0
`
`R/W
`x
`
`b2
`
`b1
`
`b0
`
`DMADONE GPIFWF GPIFDONE
`
`R/W
`x
`
`R/W
`x
`
`R/W
`x
`
`Figure 15-44. Generic Interrupt Request
`
`Chapter 15. EZ-USB FX Registers
`
`Page 15-21
`
`Exhibit 2032 - Page 315 of 435
`
`
`
`EZ-USB FX Technical Reference Manual
`
`15.20 Input/Output Port Registers D and E
`
`For more information, see Section 4.3. "Input/Output Port Registers".
`
`15.20.1 Port D Outputs
`
`OUTD
`
`Port D Outputs
`
`7841
`
`b7
`
`b6
`
`b5
`
`b4
`
`b3
`
`b2
`
`b1
`
`b0
`
`OUTD7
`
`OUTD6
`
`OUTD5
`
`OUTD4
`
`OUTD3
`
`OUTD2
`
`OUTD1
`
`OUTD0
`
`R/W
`0
`
`R/W
`0
`
`R/W
`0
`
`R/W
`0
`
`R/W
`0
`
`R/W
`0
`
`R/W
`0
`
`R/W
`0
`
`Figure 15-45. Port D Outputs
`
`15.20.2 Input Port D Pins
`
`PINSD
`
`Port D Pins
`
`7842
`
`b7
`
`b6
`
`b5
`
`b4
`
`b3
`
`b2
`
`b1
`
`b0
`
`PIND7
`
`PIND6
`
`PIND5
`
`PIND4
`
`PIND3
`
`PIND2
`
`PIND1
`
`PIND0
`
`R
`x
`
`R
`x
`
`R
`x
`
`R
`x
`
`R
`x
`
`R
`x
`
`R
`x
`
`R
`x
`
`Figure 15-46. Input Port D Pins
`
`15.20.3 Port D Output Enable
`
`OED
`
`Port D Output Enable
`
`7843
`
`b7
`
`b6
`
`b5
`
`b4
`
`b3
`
`b2
`
`b1
`
`b0
`
`OED7
`
`OED6
`
`OED5
`
`OED4
`
`OED3
`
`OED2
`
`OED1
`
`OED0
`
`R/W
`0
`
`R/W
`0
`
`R/W
`0
`
`R/W
`0
`
`R/W
`0
`
`R/W
`0
`
`R/W
`0
`
`R/W
`0
`
`Figure 15-47. Port D Output Enable Register
`
`Page 15-22
`
`EZ-USB FX Technical Reference Manual v1.2
`
`Exhibit 2032 - Page 316 of 435
`
`
`
`15.20.4 Port E Outputs
`
`OUTE
`
`Port E Outputs
`
`7845
`
`b7
`
`b6
`
`b5
`
`b4
`
`b3
`
`b2
`
`b1
`
`b0
`
`OUTE7
`
`OUTE6
`
`OUTE5
`
`OUTE4
`
`OUTE3
`
`OUTE2
`
`OUTE1
`
`OUTE0
`
`R/W
`0
`
`R/W
`0
`
`R/W
`0
`
`R/W
`0
`
`R/W
`0
`
`R/W
`0
`
`R/W
`0
`
`R/W
`0
`
`Figure 15-48. Port E Outputs
`
`15.20.5 Input Port E Pins
`
`PINSE
`
`Port E Pins
`
`7846
`
`b7
`
`b6
`
`b5
`
`b4
`
`b3
`
`b2
`
`b1
`
`b0
`
`PINE7
`
`PINE6
`
`PINE5
`
`PINE4
`
`PINE3
`
`PINE2
`
`PINE1
`
`PINE0
`
`R
`x
`
`R
`x
`
`R
`x
`
`R
`x
`
`R
`x
`
`R
`x
`
`R
`x
`
`R
`x
`
`Figure 15-49. Input Port E Pins
`
`15.20.6 Port E Output Enable
`
`OEE
`
`Port E Output Enable
`
`7847
`
`b7
`
`b6
`
`b5
`
`b4
`
`b3
`
`b2
`
`b1
`
`b0
`
`OEE7
`
`OEE6
`
`OEE5
`
`OEE4
`
`OEE3
`
`OEE2
`
`OEE1
`
`OEE0
`
`R/W
`0
`
`R/W
`0
`
`R/W
`0
`
`R/W
`0
`
`R/W
`0
`
`R/W
`0
`
`R/W
`0
`
`R/W
`0
`
`Figure 15-50. Port E Output Enable Register
`
`Chapter 15. EZ-USB FX Registers
`
`Page 15-23
`
`Exhibit 2032 - Page 317 of 435
`
`
`
`EZ-USB FX Technical Reference Manual
`
`15.21 PORTSETUP
`
`PORTSETUP
`
`Timer0 Clock Source, Port to SFR Mapping
`
`7849
`
`b7
`
`0
`
`R/W
`x
`
`b6
`
`0
`
`R/W
`x
`
`b5
`
`0
`
`R/W
`x
`
`b4
`
`0
`
`R/W
`x
`
`b3
`
`0
`
`R/W
`x
`
`b2
`
`0
`
`R/W
`x
`
`b1
`
`b0
`
`TOCLK
`
`SFRPORT
`
`R/W
`x
`
`R/W
`x
`
`Figure 15-51. PORTSETUP
`
`15.22 Interface Configuration
`
`IFCONFIG
`
`Interface Configuration
`
`784A
`
`b7
`
`52ONE
`
`R/W
`0
`
`b6
`
`0
`
`R
`0
`
`b5
`
`0
`
`R
`0
`
`b4
`
`0
`
`R
`0
`
`b3
`
`b2
`
`GSTATE
`
`BUS16
`
`R/W
`0
`
`R/W
`0
`
`b1
`
`IF1
`
`R/W
`0
`
`b0
`
`IF0
`
`R/W
`0
`
`Figure 15-52. Interface Configuration
`
`Bit 7:
`
`52ONE
`
`Set to “1” for the 52-pin package
`
`This bit must be set to “1” for the 52-pin versions of EZ-USB FX. This ensures that certain sig-
`nals that are driven properly for EZ-USB FX low power operation.
`
`Bit 6-4:
`
`Bit 3:
`
`Reserved
`
`GSTATE
`
`Reserved bits, read as 0
`
`Output GSTATE
`
`When GSTATE=1, three bits in Port A take on the signals shown in Table 15-1. The GSTATE
`bits, which indicate GPIF states, are used for diagnostic purposes.
`
`Page 15-24
`
`EZ-USB FX Technical Reference Manual v1.2
`
`Exhibit 2032 - Page 318 of 435
`
`
`
`Table 15-1. Port A Alternate Functions When GSTATE=1.
`
`IO
`Pin
`PA0
`PA1
`PA2
`
`Alternate
`Function
`GSTATE[0]
`GSTATE[1]
`GSTATE[2]
`
`Bit 2:
`
`BUS16
`
`8- or 16-Bit Slave FIFO Operation
`
`This bit selects 8-bit (BUS16=0) or 16-bit (BUS16=1) operation for slave FIFOs A and B. See
`Chapter 7. "EZ-USB FX Slave FIFOs" for full details.
`
`Bit 1-0:
`
`Interface Select
`
` Reconfigure I/O ports
`
`These bits, along with the BUS16 bit, select different groups of signals for various EZ-USB FX
`pins. Table 15-2 shows the selections.
`
`Chapter 15. EZ-USB FX Registers
`
`Page 15-25
`
`Exhibit 2032 - Page 319 of 435
`
`
`
`EZ-USB FX Technical Reference Manual
`
`Table 15-2. Pin Configurations Based on IFCONFIG[1..0]
`
`00
`
`01
`
`IFCONFIG[1..0]
`10
`
`11
`
`PE0
`PE1
`PE2
`PE3
`PE4
`PE5
`PE6
`PE7
`NC
`NC
`NC
`Strap
`Strap
`Strap
`Strap
`Strap
`Strap
`Strap
`Strap
`PORTB
`PORTD
`
`PE0
`PE1
`PE2
`PE3
`PE4
`PE5
`PE6
`PE7
`NC
`NC
`NC
`Strap
`Strap
`Strap
`Strap
`Strap
`Strap
`Strap
`Strap
`D[7..0]
`PORTD
`
`BUS16=1
`adr0
`adr1
`adr2
`adr3
`adr4
`CTL3
`CTL4
`CTL5
`CTL0
`CTL1
`CTL2
`RDY0
`RDY1
`RDY2
`RDY3
`RDY4
`RDY5
`adr5
`XCLK
`GDA[7..0]
`GDB[7..0]
`
`BUS16=0
`adr0
`adr1
`adr2
`adr3
`adr4
`CTL3
`CTL4
`CTL5
`CTL0
`CTL1
`CTL2
`RDY0
`RDY1
`RDY2
`RDY3
`RDY4
`RDY5
`adr5
`XCLK
`GDA7..0]
`PORTD
`
`BUS16=1
`BOUTFLAG
`AINFULL
`BINFULL
`AOUTEMTY
`BOUTEMTY
`PE5
`PE6
`PE7
`AINFLAG
`BINFLAG
`AOUTFLAG
`ASEL
`BSEL
`AOE
`BOE
`SLWR
`SLRD
`X
`XCLK
`AFI[7..0]
`BFI[7..0]
`
`BUS16-=0
`BOUTFLAG
`AINFULL
`BINFULL
`AOUTEMTY
`BOUTEMTY
`PE5
`PE6
`PE7
`AINFLAG
`BINFLAG
`AOUTFLAG
`ASEL
`BSEL
`AOE
`BOE
`SLWR
`SLRD
`X
`XCLK
`AFI[7..0]
`PORTD
`
`NC -Package pin must be left unconnected.
`Strap -Package pin must be either pulled-up to VDD or pulled-down to GND.
`
`Page 15-26
`
`EZ-USB FX Technical Reference Manual v1.2
`
`Exhibit 2032 - Page 320 of 435
`
`
`
`15.23 PORTA and PORTC Alternate Configurations
`
`15.23.1 Port A Alternate Configuration #2
`
`PORTACF2
`
`PORTA Alternate Configuration #2
`
`784B
`
`b7
`
`0
`
`R/W
`0
`
`b6
`
`0
`
`R/W
`0
`
`b5
`
`b4
`
`SLRD
`
`SLWR
`
`R/W
`0
`
`R/W
`0
`
`b3
`
`0
`
`R/W
`0
`
`b2
`
`0
`
`R/W
`0
`
`b1
`
`0
`
`R/W
`0
`
`b0
`
`0
`
`R/W
`0
`
`Figure 15-53. Port A Alternate Configuration #2
`
`Bit 5:
`
`SLRD
`
`Select SLRD/RDY5 signal on PA5 pin
`
`This bit, in conjunction with the PORTACFG.5 Bit and the IFCONFIG[1..0] bits, determines the
`function of PA5, as shown in Table 15-3.
`
`Table 15-3. Port A Bit 5
`
`PORTA Bit 5
`PORTACFG.5=1
`
`PORT-
`ACFG.5=0
`
`PORTACF2.5=0
`
`Port pin PA5
`
`FRD#
`
`PORTACF2.5=1
`IFCONFIG[1..0]=10
`IFCONFIG[1..0]=11
`RDY5
`SLRD
`
`Bit 4:
`
`SLWR
`
`Select SLWR/RDY4 signal on PA4 pin
`
`This bit, in conjunction with the PORTACFG.4 Bit and the IFCONFIG[1..0] bits, determines the
`function of PA4, as shown in Table 15-4.
`
`Table 15-4. Port A Bit 4
`
`PORTA Bit 4
`PORTACFG.4=1
`
`PORT-
`ACFG.4=0
`
`PORTACF2.4=0
`
`Port pin PA4
`
`FWR#
`
`PORTACF2.4=1
`IFCONFIG[1..0]=10
`IFCONFIG[1..0]=11
`RDY4
`SLWR
`
`Chapter 15. EZ-USB FX Registers
`
`Page 15-27
`
`Exhibit 2032 - Page 321 of 435
`
`
`
`EZ-USB FX Technical Reference Manual
`
`15.23.2 Port C Alternate Configuration #2
`
`PORTCCF2
`
`PORTC Alternate Configuration #2
`
`784C
`
`b7
`
`CTL5
`
`R/W
`0
`
`b6
`
`CTL4
`
`R/W
`0
`
`b5
`
`CTL3
`
`R/W
`0
`
`b4
`
`CTL1
`
`R/W
`0
`
`b3
`
`RDY3
`
`R/W
`0
`
`b2
`
`0
`
`R/W
`0
`
`b1
`
`b0
`
`RDY1
`
`RDY0
`
`R/W
`0
`
`R/W
`0
`
`Figure 15-54. Port C Alternate Configuration #2
`
`Bit 7:
`
`CTL5
`
`Select CTL5 on PC7 pin
`
`This bit, in conjunction with the PORTCCFG.7 Bit, determines the function of PC7, as shown
`in Table 15-5.
`
`Table 15-5. Port C Bit 7
`
`PORTCCFG.7=0
`
`PORTCCF2.7=0
`
`Port pin PC7
`
`RD#
`
`PORTC Bit 7
`PORTCCFG.7=1
`PORTCCF2.7=1
`IFCONFIG[1..0]=10
`00, 01, 11 not valid
`CTL5
`X
`
`Bit 6:
`
`CTL4
`
`Select CTL4 on PC6 pin
`
`This bit, in conjunction with the PORTCCFG.6 Bit, determines the function of PC6, as shown
`in Table 15-6.
`
`Table 15-6. Port C Bit 6
`
`PORTCCFG.6=0
`
`PORTCCF2.6=0
`
`Port pin PC6
`
`WR#
`
`PORTC Bit 6
`PORTCCFG.6=1
`PORTCCF2.6=1
`IFCONFIG[1..0]=10
`00, 01, 11 not valid
`CTL4
`X
`
`Page 15-28
`
`EZ-USB FX Technical Reference Manual v1.2
`
`Exhibit 2032 - Page 322 of 435
`
`
`
`Bit 5:
`
`CTL3
`
`Select CTL3 on PC5 pin
`
`This bit, in conjunction with the PORTCCFG.5 Bit, determines the function of PC5, as shown in
`Table 15-7.
`
`Table 15-7. Port C Bit 5
`
`PORTCCFG.5=0
`
`PORTCCF2.5=0
`
`Port pin PC5
`
`T1
`
`PORTC Bit 5
`PORTCCFG.5=1
`PORTCCF2.5=1
`IFCONFIG[1..0]=10
`00, 01, 11 not valid
`CTL3
`X
`
`CTL1
`Bit 4:
`Select CTL1 on PC4 pin
`This bit, in conjunction with the PORTCCFG.4 Bit, determines the function of PC4, as shown in
`Table 15-8.
`
`Table 15-8. Port C Bit 4
`
`PORTCCFG.4=0
`
`PORTCCF2.4=0
`
`Port pin PC4
`
`T0
`
`PORTC Bit 4
`PORTCCFG.4=1
`PORTCCF2.4=1
`IFCONFIG[1..0]=10
`00, 01, 11 not valid
`CTL1
`X
`
`Bit 3:
`
`RDY3
`
`Select RDY3 on PC3 pin
`
`This bit, in conjunction with the PORTCCFG.3 Bit, determines the function of PC3, as shown in
`Table 15-9.
`
`Table 15-9. Port C Bit 3
`
`PORTCCFG.3=0
`
`PORTCCF2.3=0
`
`Port pin PC3
`
`INT1
`
`PORTC Bit 3
`PORTCCFG.3=1
`PORTCCF2.3=1
`IFCONFIG[1..0]=10
`00, 01, 11 not valid
`RDY3
`X
`
`Chapter 15. EZ-USB FX Registers
`
`Page 15-29
`
`Exhibit 2032 - Page 323 of 435
`
`
`
`EZ-USB FX Technical Reference Manual
`
`Bit 2:
`
`Bit 1:
`
`Reserved
`
`Reads as 0
`
`RDY1
`
`Select RDY1 on PC1 pin
`
`This bit, in conjunction with the PORTCCFG.1 Bit, determines the function of PC1, as shown
`in Table 15-10.
`
`Table 15-10. Port C Bit 1
`
`PORTCCFG.1=0
`
`PORTCCF2.1=0
`
`Port pin PC1
`
`TxD0
`
`PORTC Bit 1
`PORTCCFG.1=1
`PORTCCF2.1=1
`IFCONFIG[1..0]=10
`00, 01, 11 not valid
`RDY1
`X
`
`Bit 0:
`
`CTL5
`
`Select CTL5 on PC0 pin
`
`This bit, in conjunction with the PORTCCFG.0 Bit, determines the function of PC0, as shown
`in Table 15-11.
`
`Table 15-11. Port C Bit 0
`
`PORTCCFG.0=0
`
`PORTCCF2.0=0
`
`Port pin PC0
`
`RxD0
`
`PORTC Bit
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