Chapter 8. General Programmable Interface (GPIF)
`
`8.1 What is GPIF?
`
`The General Programmable InterFace (GPIF) is an extremely flexible 8- or 16-bit parallel interface
`that allows designers to reduce system costs by providing a glueless interface between the EZ-
`USB FX and many different types of external peripherals.
`
`The GPIF allows the EZ-USB FX to perform local bus mastering to external peripherals using a
`wide variety of protocols. For example, EIDE/ATAPI, printer parallel port (IEEE P1284), Utopia,
`and other interfaces can be supported using the GPIF block of the EZ-USB FX.
`
`To support a wide range of applications, the GPIF implements an extensive feature set that can be
`modified to suit the design. As with other highly configurable chips, some initialization steps are
`required. To support a range of interface styles, the GPIF provides multiple programmable I/O pins
`and multiple registers to configure those pins.
`
`This chapter provides an overview of GPIF, discusses external connections, and explains the oper-
`ation of the GPIF engine.
`
`Figure 8-1 presents a block diagram illustrating GPIF’s place in the FX System.
`
`Chapter 8. General Programmable Interface (GPIF)
`
`Page 8-1
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`79 00
`
`G PIF
`
`Program
`
`79 7F
`
`G PIFAD R L
`
`C ounter
`
`G PIF
`
`D ata
`U IA
`D M A
`
`C lock
`
`EP Buffers
`
`FIFO s
`
`U SB
`D ata
`
`8051
`
`S G LD AT
`R /W
`
`A D R
`R D Y
`C TL
`
`Flags
`AFI
`BFI
`
`Figure 8-1. GPIF’s Place in the FX System
`
`8.2 Applicable Documents and Tools
`
`EZ-USB FX Data Sheet
`
`EPP Reference Design
`
`Mass Storage Reference Design
`
`GPIF Tool — A Windows application that assists GPIF firmware development. The GPIF
`Tool can be found on the EZ-USB FX Developer’s Kit CD.
`
`Page 8-2
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`
`8.3 Typical GPIF Interface
`
`The GPIF allows the EZ-USB FX connect directly to external peripherals such as ASICs, DSPs, or
`other digital logic that uses an 8- or 16-bit parallel interface.
`
`The GPIF provides external pins that can operate as outputs (CTL0 to CTL5), inputs (RDY0 to
`RDY5), Data bus (GDA[7..0] and GDB[7..0]), and Address Lines (ADR0 to ADR5).
`
`A Waveform Descriptor in internal RAM describes the behavior of each of the GPIF signals. The
`Waveform Descriptor is loaded into the GPIF registers by the 8051 firmware during initialization,
`and it is then used throughout the execution of the 8051 code to perform transactions over the
`GPIF interface.
`
`Figure 8-2 shows a block diagram of a typical interface between the EZ-USB FX and a peripheral
`function.
`
`EZ-USB FX
`
`GPIF
`
`Control Outputs
`
`Ready Inputs
`
`Addresses
`
`Data Bus
`
`Peripheral
`
`Figure 8-2. EZ-USB FX Interfacing to a Peripheral
`
`The following sections detail the features available and steps needed to create an efficient GPIF
`design. This includes definition of the external GPIF connections and the internal register settings,
`along with 8051 firmware needed to execute data transactions over the interface.
`
`Chapter 8. General Programmable Interface (GPIF)
`
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`8.4 External GPIF Connections
`
`8.4.1 The External GPIF Interface
`
`The GPIF provides many general input and output signals with which to interface your external
`peripherals gluelessly to the EZ-USB FX.
`
`The GPIF interface signals are shown in Table 8-1.
`
`Table 8-1. GPIF Pin Descriptions
`
`PIN
`ADR[5:0]
`GDA[7:0]
`GDB[7..0]
`CTL[5:0]
`RDY[5:0]
`
`IN/OUT Description
`O
`Address outputs
`I/O
`Bidirectional A-FIFO data bus
`I/O
`Bidirectional B-FIFO data bus
`O
`Programmable control outputs
`I
`Sampleable ready inputs
`
`Refer to the figure EZ-USB FX 128-pin Package on p. 13 of the CY7C64603/613 Data Sheet.
`
`The Control Outputs (CTL0 to CTL5) are intended to be strobes, read/write lines, and other non-
`bused outputs.
`
`The Ready Inputs (RDY0 to RDY5) sample a signal to allow a transaction to wait (inserting wait
`states), continue, or repeat until the signal is at the appropriate level.
`
`The GPIF Data Bus is a collection of the GDA[7..0] and GDB[7..0] pins.
`
`A GPIF interface 8 bits wide uses pins GDA[7..0].
`
`A GPIF interface 16 bits wide uses pins GDA[7..0] and GDB[7..0].
`
`The GPIF Address lines (ADR0 to ADR5) can generate an automatically incrementing address
`during a burst transaction. For non-burst transactions, these address lines remain static. For
`higher-order address lines that may be needed, other non-GPIF I/O signals should be used.
`
`The GPIF Clock can be either an internal 48MHz clock, or an externally-supplied clock from the
`XCLK pin. If the XCLK_SEL pin is tied high, the GPIF clock is the XCLK pin. Otherwise, the GPIF
`clock is the 48 MHz internal clock.
`
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`
`8.4.2 Connecting GPIF Signal Pins to Hardware
`
`The first step in creating the interface between the EZ-USB FX GPIF and your peripheral is to
`define the hardware interconnects. This physical connection of GPIF signals to your interface sig-
`nals determines the configurations that are necessary by your 8051 firmware.
`
`1. Determine the proper GPIF Data Bus size. If your interface's data bus is 8 bits wide, use the
`GDA[7..0] pins. If your interface's data bus is 16 bits wide, use GDA[7..0] and GDB[7..0].
`
`2. Assign the CTL signals to your interface. Make a list of all interface signals to be driven by
`your peripheral (inputs to the GPIF), and assign them to the RDY0 to RDY5 Inputs. If there are
`more input signals than available RDY inputs, you need to use other, non-GPIF I/O signals and
`sample them manually using 8051 firmware. In this case, you should choose the RDY inputs
`only for signals that must be sampled in the middle of a data transaction.
`
`3. Assign the RDY signals to your interface. Make a list of all interface signals to be driven by
`your peripheral (inputs to the GPIF), and assign them to the RDY0 through RDY5 Inputs. If
`there are more input signals than available RDY inputs, you will need to use other non-GPIF I/
`O signals and sample them manually using 8051 firmware. In this case, you should choose to
`use the RDY inputs only for signals that must be sampled in the middle of a data transaction.
`
`4. Determine the proper GPIF Address connections. If your interface uses an Address Bus,
`use the ADR0 through ADR5 signals for the least significant bits, and other non-GPIF I/O sig-
`nals for the most significant bits. You may leave these signals unconnected if you do not use
`address signals, as with a FIFO.
`
`8.4.3 Example GPIF Hardware Interconnect
`
`The following example illustrates the hardware connections that can be made for a standard inter-
`face: a 27C256 EPROM.
`
`Table 8-2. Example GPIF Hardware Interconnect
`
`Step
`1. Determine the proper GPIF
`Data Bus size.
`2. Assign the CTL signals to
`your interface.
`3. Assign the RDY signals to
`your interface.
`4. Determine the proper GPIF
`Address connections.
`
`Result
`8 bits.
`
`CS# and OE# are inputs to the
`EPROM.
`There are no output ready/wait
`signals from a 27C256 EPROM.
`16 bits of address.
`
`Connection Made
`Connect GDA[7..0] to
`D0..D7 of the EPROM.
`Connect CTL0 to CS#
`and CTL1 to OE#.
`No connection.
`
`Connect ADR0..ADR5 to
`A0..A5 and other I/O
`ports to A6..A15.
`
`The process is the same for larger and more complicated interfaces.
`
`Chapter 8. General Programmable Interface (GPIF)
`
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`8.5 Internal GPIF Operation
`
`8.5.1 The Internal GPIF Engine
`
`The GPIF Engine is controlled by two blocks of registers in 8051 XDATA space:
`
`GPIF Configuration Registers — These registers configure the general settings and
`report the status of the interface to the 8051, a total of 18 registers from 0x7824 to
`0x783C. See the EZ-USB FX Register Summary and the remainder of this chapter for
`details.
`
`(cid:127) Waveform Memories — A block of registers loaded by the 8051 with the Waveform
`Descriptors that program the GPIF interface, a total of 128 bytes from 0x7900 to 0x797F.
`
`The GPIF has 4 Waveform Memories. Each Waveform Memory holds a GPIF program con-
`taining up to 7 programmed Intervals. Each Interval is a 32-bit instruction for the GPIF Engine.
`
`The 8051 must load these registers before initiating GPIF operation.
`
`8.5.2 Global GPIF Configuration
`
`The GPIF configuration registers allow for various modes of operation. These modes control the
`global operation of the GPIF for all waveforms.
`
`8.5.2.1 Data Bus Width
`
`The GPIF can have an 8-bit or 16-bit wide data bus. It is selected by the BUS16 Bit (Bit 2) of the
`IFCONFIG Register:
`
`If BUS16 is 1, the data bus is 16 bits wide.
`
`If BUS16 is 0, the data bus is 8 bits wide.
`
`Refer to the figure EZ-USB FX 128-pin Package on p. 13 of the CY7C64603/613 Data Sheet.
`
`8.5.2.2 Control Output Modes
`
`The GPIF Control pins (CTL0 to CTL5) have several output modes:
`
`CTL0 to CTL3 can actively drive CMOS levels 1 and 0, be open-drain, or tristate.
`
`CTL4 and CTL5 can actively drive CMOS levels 1 and 0, or be open-drain.
`
`If CTL0 to CTL3 are configured to be tristate-able, CTL4 and CTL5 are not available.
`
`Page 8-6
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`
`TRICTL
`(CTLOUTCFG.7)
`1
`0
`1
`0
`
`Table 8-3. CTL Output Modes
`
`CTLOUTCFG[6..0]
`
`CTL0[3..0]
`
`CTL[5..4]
`
`1
`1
`0
`0
`
`0, 1, or tristate
`0 or open-drain
`0, 1, or tri-stateable
`0 or 1
`
`Not Available
`Open-drain
`Not Available
`CMOS
`
`Important: The TRICTL Bit controls the meaning of the OUTPUT field in all currently loaded
`Waveform Programs.
`
`8.5.2.3 Synchronous/Asynchronous Mode
`
`The GPIF interface can be operated in Asynchronous or Synchronous mode:
`
`In Asynchronous mode, the RDY inputs are double-sampled.
`
`In Synchronous mode, the RDY inputs are single-sampled, improving performance.
`
`The synchronous/asynchronous mode is selected via the SAS Bit (Bit 6) of the READY Register:
`
`If SAS = 1, the RDY[5..0] Inputs are synchronous to the GPIF Clock, sampled at only one
`rising edge of the GPIF Clock.
`
`If SAS = 0, the RDY[5..0] Inputs are sampled at two rising edges of the GPIF Clock before the
`appropriate GPIF Branch is taken.
`
`8.5.3 Programming GPIF Waveforms
`
`GPIF Waveforms are programmed by the programmer coding Waveform Descriptors.
`Subsequently, the 8051 stores these descriptors into the Waveform Memories. The Waveform
`Descriptors are the instructions to the GPIF engine — what to do when that Waveform is
`triggered. There are 4 Waveform Memories in the EZ-USB FX, one for each of the following types
`of waveforms:
`
`Single Write Waveform
`
`Single Read Waveform
`
`FIFO Write Waveform
`
`FIFO Read Waveform
`
`Chapter 8. General Programmable Interface (GPIF)
`
`Page 8-7
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`EZ-USB FX Technical Reference Manual
`
`(See the WF_SELECT Register in Section 8.5.5.5. "Waveform Selector".)
`
`Each Waveform Descriptor consists of up to seven 32-bit instructions that program key transition
`points for all GPIF interface signals. These instructions are called Intervals because they have a
`one-to-one correspondence to intervals of time in an actual waveform. For that portion of the
`Waveform, an Interval defines, the
`
`state of the CTL outputs
`
`state of GDA[7..0] and GDB[7..0] (GPIF Data Bus)
`
`use of the RDY inputs
`
`behavior of the GPIF address bus.
`
`Intervals always begin at the rising edge of the GPIF Clock.
`
`8.5.3.1 The GPIF IDLE State
`
`A Waveform consists of up to seven programmable Intervals (I0 to I6). Every Waveform termi-
`nates when the GPIF program branches to a special IDLE interval or IDLE state, which is by
`convention Interval 7 (I7).
`
`To complete a GPIF transaction, the GPIF program always branches to the IDLE state, regard-
`less of the interval that the GPIF program is currently executing. For example, it is possible to
`have a GPIF Waveform that has 3 Intervals: I0, I1 and I7. The GPIF program branches from I1 (or
`I0) to I7 when it wishes to terminate.
`
`The IDLE state is the time between two active GPIF transactions.
`
`The state of the GPIF signals during the IDLE state is determined by the contents of the IDLE_CS
`and IDLE_CTLOUT Registers.
`
`The 8051 programmer must make sure the GPIF is IDLE before starting the next Waveform. The
`8051 senses completion of a Waveform (the Waveform Program branching to the GPIF IDLE
`state) by reading the DONE Bit (Bit 7) in the IDLE_CS Register.
`
`If DONE is 0, the GPIF is Busy generating a Waveform.
`
`If DONE is 1, the GPIF is Done (GPIF is in the IDLE state), ready for the 8051 to start the
`next GPIF transaction.
`
`Important: It is illegal to initiate any operation (except aborting the current transaction) when the
`GPIF is Busy. Doing so yields indeterminate behavior, likely to cause data corruption.
`
`Page 8-8
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`
`8.5.3.1.1 GPIF Data Bus During IDLE
`During the IDLE state, the GPIF Data Bus (GDA[7..0] and GDB[7..0]) can be either driven or
`tristated, depending on how the 8051 program has set the IDLEDRV bit (bit 0) of the IDLE_CS
`Register.
`
`If IDLEDRV is 0, the GPIF Data Bus tristates during IDLE.
`
`If IDLEDRV is 1, the GPIF Data Bus is actively driven during IDLE. The value driven is the
`last value driven by any GPIF Waveform program.
`
`8.5.3.1.2 CTL Outputs During IDLE
`During the IDLE state, the state of CTL[5..0] depends on the following register bits
`
`TRICTL Bit (Bit 7) in the CTLOUTCFG Register (as described in the previous Control Out-
`put Modes.
`
`IDLE_CTLOUT[5..0] Register bits.
`
`The combination of TRICTL and IDLE_CTLOUT[5..0] define CTL[5..0] during IDLE as follows:
`
`If TRICTL is 0, IDLE_CTLOUT[5..0] is the output state of CTL[5..0] during the IDLE state.
`
`If TRICTL is 1, IDLE_CTLOUT[7..4] are the Output Enables for the CTL0 to CTL3 signals,
`and IDLE_CTLOUT[3..0] are the Output values for CTL0 to CTL3.
`
`Table 8-4 below illustrates this relationship.
`
`Table 8-4. Control Outputs (CTLn) During the IDLE State
`
`Control Output
`
`CTL0
`
`CTL1
`
`CTL2
`
`CTL3
`
`CTL4
`
`CTL5
`
`CTLOUTCFG.7
`TRICTL
`0
`1
`0
`1
`0
`1
`0
`1
`0
`1
`0
`1
`
`IDLE_CTLOUT Out-
`put Enable
`Not Available
`Bit 4 (OE0)
`Not Available
`Bit 5 (OE1)
`Not Available
`Bit 6 (OE2)
`Not Available
`Bit 7 (OE3)
`Not Available
`Not Available
`Not Available
`Not Available
`
`IDLE_CTLOUT
`Output Bit
`Bit 0 (CTL0)
`
`Bit 1 (CTL1)
`
`Bit 2 (CTL2)
`
`Bit 3 (CTL3)
`
`Bit 4 (CTL4)
`Not Available
`Bit 5 (CTL5)
`Not Available
`
`Chapter 8. General Programmable Interface (GPIF)
`
`Page 8-9
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`
`The CTL[5..0] lines are also affected by the corresponding bit in the CTLOUTCFG Register.
`
`If the IDLE_CTLOUT Register and TRICTL Bit indicate that a 1 is to be driven, then a 1 in
`the corresponding bit in the CTLOUTCFG Register makes the output an open-drain.
`
`If the IDLE_CTLOUT Register and TRICTL Bit indicate that a 0 is to be driven, then a 0 in
`the corresponding bit in the CTLOUTCFG Register makes the output actively drive a
`CMOS high level.
`
`8.5.3.2 Defining Intervals
`
`Each Waveform is made up of a number of Intervals. A single Interval is defined by a 4-byte Wave-
`form Descriptor, and it is defined as one of two basic types. Each Interval is programmed as either:
`
`Non-Decision Point (NDP) Interval
`
`Decision Point (DP) Interval.
`
`It is possible to change only selected bytes of a Waveform Program. It is not necessary to reload
`the entire program if only a few bytes change. Hence, the 8051 can quickly reconfigure the GPIF
`when it is not Busy.
`
`8.5.3.2.1 Non-Decision Point (NDP) Intervals
`For NDP intervals, the control outputs (CTLn) are defined by the GPIF instruction to be either 1, 0,
`or tristated during the entire interval. These types of intervals have a programmable fixed duration
`in units of XCLK cycles.
`
`For write waveforms, the data bus is either driven or tristated during the interval.
`
`For read waveforms, the data bus is either sampled and stored as the read data or not sampled
`during the interval.
`
`Figure 8-3 below illustrates the basic concept for NDP intervals. A write waveform is shown, and
`for simplicity all the intervals are shown with equal spacing. There are a total of six programmable
`outputs, but only one (CTL 0) is shown in the Figure 8-3.
`
`Remember that the 4-byte Waveform Descriptor defines the characteristics of each interval. For a
`detailed definition of the 4-byte Waveform Descriptor, see Section 8.5.5.5. "Waveform Selector".
`
`Page 8-10
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`

`
`I0
`
`I1
`
`I2
`
`I3
`
`I4
`
`I5
`
`I6
`
`'Z'
`
`VALID
`
`'Z'
`
`ADR[5..0]
`
`GDA[7..0]
`
`CTL0
`
`Figure 8-3. Non-Decision Point (NDP) Intervals
`
`The following paragraphs describe Figure 8-3,
`
`In interval I0:
`GDA[7..0] is programmed to be tri-stated
`CTL0 is programmed to be driven to a logic 1.
`
`In interval I1:
`GDA[7..0] is programmed to be driven.
`CTL0 is still programmed to be driven to a logic 1.
`
`In interval I2:
`GDA[7..0] is programmed to be driven.
`CTL0 is programmed to be driven to a logic 0.
`
`In interval I3:
`GDA[7..0] is programmed to be driven.
`CTL0 is still programmed to be driven to a logic 0.
`
`In interval I4:
`GDA[7..0] is programmed to be driven.
`CTL0 is programmed to be driven to a logic 1.
`
`In interval I5:
`GDA[7..0] is programmed to be tri-stated
`CTL0 is still programmed to be driven to a logic 1.
`
`In interval I6:
`GDA[7..0] is programmed to be tri-stated
`CTL0 is still programmed to be driven to a logic 1.
`
`Chapter 8. General Programmable Interface (GPIF)
`
`Page 8-11
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`
`Since all intervals in this example are coded as NDP intervals, the GPIF automatically branches
`from the last interval (I6) to interval 7, the IDLE state. This is the state in which the GPIF waits until
`the next GPIF waveform is started by the 8051.
`
`8.5.3.2.2 Decision Point (DP) Intervals
`The second type of interval is the Decision Point Interval. Any interval can be designated as a DP
`interval. A DP interval allows the GPIF engine to sample one or more of the RDY inputs (or other
`internal signals) and branch to other intervals based on the current value.
`
`With a decision point interval, the GPIF can perform simple tasks such as wait until a RDY line is
`low before continuing to the next interval. Decision point intervals can also be more complex by
`branching to one interval if the sampled signals result in a logic 1, and a different interval if they
`result in a logic 0.
`
`In a DP interval, the user specifies which two ‘signals’ to sample. The two ‘signals’ can be selected
`from any of:
`
`six external RDY signals
`programmable FIFO flags
`or the INTERNAL_READY Bit in the READY Register.
`
`The user then specifies a logic function (AND, OR, or XOR) to apply to the two selected signals.
`To select only one signal, simply select the same signal twice and specify the logic function as
`AND.
`
`In the Waveform Descriptor for the DP interval, the user then specifies which interval to branch to
`if the resultant logic expression is a 0, and which interval to branch to if the resultant logic expres-
`sion is a 1.
`
`Below is an example waveform created using one decision point interval (I1) and non-decision
`point intervals for the rest of the waveform.
`
`Page 8-12
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`
`I0
`
`I1
`
`I2
`
`I3
`
`I4
`
`I5
`
`I6
`
`'Z'
`
`VALID
`
`'Z'
`
`ADR[5 0]
`
`GDA[7..0]
`
`CTL0
`
`RDY0
`
`Figure 8-4. One Decision Point: Wait States Inserted Until RDY0 Goes Low
`
`I1
`
`I0
`
`I2
`
`I3
`
`I4
`
`I5
`
`I6
`
`'Z'
`
`VALID
`
`'Z'
`
`ADR[5..0]
`
`GDA[7..0]
`
`CTL0
`
`RDY0
`
`Figure 8-5. One Decision Point: No Wait States Inserted:
`RDY0 is Already Low at Decision Point I1
`
`In Figure 8-4 and Figure 8-5, there is a single decision point defined as interval I1. In this example,
`the input ready signal is assumed to be connected to RDY0, and the Waveform Descriptor for I1 is
`
`Chapter 8. General Programmable Interface (GPIF)
`
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`configured to branch to interval I2 if RDY0 is a logic 0 or to branch to interval I1 (wait indefinitely) if
`RDY0 is a logic 1.
`
`In Figure 8-4, the interface remains in I1 until the RDY0 signal is asserted.
`
`In Figure 8-5, the RDY0 signal is 0 when I1 is reached, so the GPIF branches to I2.
`
`8.5.3.3 Interval Waveform Descriptor
`
`Each interval must be defined to perform your desired interface. To do this, each GPIF Interval has
`a Waveform Descriptor made up of a 4-byte word that defines the interval’s characteristics.
`
`The four bytes that make up a single interval’s Waveform Descriptor are:
`
`LENGTH/BRANCH
`OPCODE
`LOGIC FUNCTION
`OUTPUT.
`
`Notice that there are 2 definitions for the Waveform Descriptors depending on whether the interval
`is a decision point (DP = 1) or a non-decision point (DP = 0).
`
`8.5.3.3.1 Non-Decision Point Waveform Descriptor
`
`Bit 3
`Bit 4
`Bit 5
`Bit 6
`Bit 7
`Number of XCLK cycles to stay in this interval (0 means 256 cycles)
`
`Bit 2
`
`Bit 1
`
`Bit 0
`
`LENGTH/BRANCH
`
`7
`x
`
`6
`x
`
`5
`x
`
`4
`GINT
`
`3
`INCAD
`
`2
`NEXT
`
`1
`DATA
`
`0
`DP = 0
`
`OPCODE
`
`6
`
`5
`
`4
`
`3
`
`2
`
`1
`
`0
`
`LOGIC FUNCTION
`
`OUTPUT (if TRICTL Bit = 1)
`
`4
`OE0
`
`3
`CTL3
`
`OUTPUT (if TRICTL Bit = 0)
`
`4
`CTL4
`
`3
`CTL3
`
`2
`CTL2
`
`2
`CTL2
`
`5
`OE1
`
`5
`CTL5
`
`6
`OE2
`
`6
`x
`
`1
`CTL1
`
`1
`CTL1
`
`0
`CTL0
`
`0
`CTL0
`
`7
`Not Used
`
`7
`OE3
`
`7
`x
`
`Page 8-14
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`EZ-USB FX Technical Reference Manual v1.2
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`Exhibit 2032 - Page 188 of 435
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`(cid:127)
`(cid:127)
`(cid:127)
`(cid:127)
`

`
`8.5.3.3.2 Decision Point Waveform Descriptor
`
`Bit 6
`x
`
`Bit 5
`1BRANCH
`
`LENGTH/BRANCH
`
`Bit 4
`
`Bit 3
`
`OPCODE
`
`Bit 2
`0BRANCH
`
`Bit 1
`
`Bit 0
`
`6
`x
`
`6
`
`6
`OE2
`
`6
`x
`
`5
`x
`
`4
`GINT
`
`3
`INCAD
`
`2
`NEXT
`
`1
`DATA
`
`0
`DP = 1
`
`LOGIC FUNCTION
`
`4
`
`3
`
`2
`TERMB
`
`1
`
`0
`
`OUTPUT (if TRICTL Bit = 1)
`
`4
`OE0
`
`3
`CTL3
`
`OUTPUT (if TRICTL Bit = 0)
`
`4
`CTL4
`
`3
`CTL3
`
`2
`CTL2
`
`2
`CTL2
`
`1
`CTL1
`
`1
`CTL1
`
`0
`CTL0
`
`0
`CTL0
`
`5
`TERMA
`
`5
`OE1
`
`5
`CTL5
`
`Bit 7
`x
`
`7
`x
`
`7
`LFUNC
`
`7
`OE3
`
`7
`x
`
`Chapter 8. General Programmable Interface (GPIF)
`
`Page 8-15
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`Exhibit 2032 - Page 189 of 435
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`

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`EZ-USB FX Technical Reference Manual
`
`The following paragraphs describe each of the Waveform Descriptor registers and the fields within
`each register.
`
`OPCODE Register: This register sets a number of interval characteristics.
`
`DP Bit: indicates whether the interval is a:
`
`1 = Decision Point interval.
`0 = Non-Decision Point interval.
`
`DATA Bit: specifies what is to be done with the data bus during this interval.
`
`During a write:
`1 = drive the bus with the output data.
`0 = tri-state (don’t drive the bus).
`
`During a read:
`1 = sample the data bus and store the data.
`0 = don’t sample the data bus.
`
`NEXT Bit: at the beginning of this interval, change the output data to the next byte from the
`outputs FIFO.
`
`1 = move the next data in the output FIFO to the top
`0 = do not advance the FIFO
`
`INCAD Bit: specifies whether to increment the GPIF Address lines ADR0..5.
`
`1 = increment the ADR0..ADR5 bus at the beginning of this interval.
`0 = do not increment the ADR0..ADR5 signals.
`
`GINT Bit: specifies whether or not to generate a GPIF interrupt to the 8051 during this inter-
`val.
`
`1 = generate 8051 GPIF interrupt when this interval is reached.
`0 = do not generate interrupt.
`
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`Exhibit 2032 - Page 190 of 435
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`

`
`OUTPUT Register: This register controls the state of the 6 control outputs (CTL5-0) during the
`entire interval corresponding to this Waveform Descriptor. For the following example, refer to
`8.5.10 "CTLOUTCFG Register".
`
`OEn Bit: specifies if the corresponding CTL output signal is tristated.
`
`1 = drive CTLn:
`
`If the CTLn Bit in the CTLOUTCFG Register is set to 1, the output driver will be
`and open-drain.
`
`If the CTLn Bit in the CTLOUTCFG Register is set to 0, the output driver will be
`driven to CMOS levels.
`
`0 = Tri-state CTLn.
`
`CTLn Bit: specifies the state to set each CTL signal to during this entire interval.
`
`1 = high level
`0 = low level
`
`LOGIC FUNCTION Register: This register is used only for decision point Waveform Descriptors. It
`specifies the inputs (TERMA and TERMB) and the Logic Function (LFUN) to apply to those inputs.
`Together these define which Branch to take in the LENGTH/BRANCH Register.
`
`TERMA and TERMB Bits:
`
`= 000 : RDY0
`= 001 : RDY1
`= 010 : RDY2
`= 011 : RDY3
`= 100 : RDY4
`= 101 : RDY5
`= 110 : Internal programmable FIFO flag
`= 111 : INTERNAL_READY (Bit 7 of the READY Register)
`
`LFUN:
`
`= 00 : perform logical AND on selected inputs
`= 01 : perform logical OR on selected inputs
`= 10 : perform logical XOR on selected inputs
`= 11 : perform logical XOR on selected inputs
`
`The Inputs are sampled at each rising edge of the GPIF Clock (XCLK).
`
`Chapter 8. General Programmable Interface (GPIF)
`
`Page 8-17
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`Exhibit 2032 - Page 191 of 435
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`(cid:127)
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`

`
`EZ-USB FX Technical Reference Manual
`
`The resultant logic function (R_LFUN) is then tested by the GPIF engine to determine which
`instruction to branch to (see the /LENGTH/BRANCH Register below) before the next rising
`edge of the GPIF Clock.
`
`This register is meaningful only for DP Instructions, that is, when the DP Bit of the OPCODE
`Register = 1. (When DP = 0, this register is a don’t care.)
`
`LENGTH / BRANCH: This register has two different meanings depending on whether the instruc-
`tion is a decision point or a non-decision point Interval:
`
`For DP = 0 this is a LENGTH field — the fixed duration of this Interval in units of XCLK
`(48MHz for internal clocking, XCLK if externally clocked). A value of 0 means an interval
`length of 256 clocks.
`
`For DP = 1 this is a BRANCH field - determines the next interval to branch to.
`
`1BRANCH: specifies which interval to branch to if the logic expression equates to a 1. 0 to
`6, or 7 (IDLE)
`0BRANCH: specifies which interval to branch to if the logic expression equates to a 0. 0 to
`6, or 7 (IDLE)
`
`Decision Point Example
`
`To make the GPIF insert wait states (wait for a RDY signal), a reasonable practice is to code a
`Waveform Descriptor that branches to itself if R_LFUN = 0, and to branch to the next instruction if
`R_LFUN = 1. This has the effect of extending the Interval (inserting wait states) indefinitely, until
`the R_LFUN that is programmed is 1.
`
`8.5.3.4 Physical Structure of the Waveform Memories
`
`Up to four different Waveforms can be defined at one time. Each Waveform is made up of up to 7
`Waveform Descriptors and loaded into the Waveform Memory as defined in this section. Each
`Waveform Memory is 32 bytes long, so the 4 Waveform Memories together are 128 bytes long.
`
`Table 8-5. Waveform Memory Types
`
`Waveform
`Memory
`0
`1
`2
`3
`
`8051
`Base XDATA Address
`0x7900
`0x7920
`0x7940
`0x7960
`
`Within each Waveform Memory, the Waveform Descriptors are packed as described in Table 8-6,
`“Waveform Memory Descriptors". Waveform Memory 0 is shown as an example. The other Wave-
`form Memories follow exactly the same structure but at higher XDATA addresses.
`
`Page 8-18
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`Exhibit 2032 - Page 192 of 435
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`(cid:127)
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`

`
`Table 8-6. Waveform Memory Descriptors
`
`Contents
`
`LENGTH/BRANCH[0] (LENGTH/BRANCH field of Instruction 0 of Waveform Program 0)
`
`LENGTH/BRANCH[1] (LENGTH/BRANCH field of Instruction 1 of Waveform Program 0, etc.)
`
`LENGTH/BRANCH[2]
`
`LENGTH/BRANCH[3]
`
`LENGTH/BRANCH[4]
`
`LENGTH/BRANCH[5]
`
`LENGTH/BRANCH[6]
`
`Unused (the Idle state)
`
`OPCODE[0] (OPCODE field of Instruction 0 of Waveform Program 0)
`
`OPCODE[1] (OPCODE field of Instruction 1 of Waveform Program 0, etc.)
`
`OPCODE[2]
`
`OPCODE[3]
`
`OPCODE[4]
`
`OPCODE[5]
`
`OPCODE[6]
`
`Unused (the Idle state)
`
`OUTPUT[0] (OUTPUT field of Instruction 0 of Waveform Program 0)
`
`OUTPUT[1] (OUTPUT field of Instruction 1 of Waveform Program 0, etc.)
`
`OUTPUT[2]
`
`OUTPUT[3]
`
`OUTPUT[4]
`
`OUTPUT[5]
`
`OUTPUT[6]
`
`Unused (the Idle state)
`
`LOGIC FUNCTION[0] (LOGIC FUNCTION field of Instruction 0 of Waveform Program 0)
`
`LOGIC FUNCTION[1] (LOGIC FUNCTION field of Instruction 1 of Waveform Program 0, etc.)
`
`LOGIC FUNCTION[2]
`
`LOGIC FUNCTION[3]
`
`LOGIC FUNCTION[4]
`
`LOGIC FUNCTION[5]
`
`LOGIC FUNCTION[6]
`
`Unused (the Idle state)
`
`XDATA
`Address
`0x7900
`
`0x7901
`
`0x7902
`
`0x7903
`
`0x7904
`
`0x7905
`
`0x7906
`
`0x7907
`
`0x7908
`
`0x7909
`
`0x790A
`
`0x790B
`
`0x790C
`
`0x790D
`
`0x790E
`
`0x790F
`
`0x7910
`
`0x7911
`
`0x7912
`
`0x7913
`
`0x7914
`
`0x7915
`
`0x7916
`
`0x7917
`
`0x7918
`
`0x7919
`
`0x791A
`
`0x791B
`
`0x791C
`
`0x791D
`
`0x791E
`
`0x791F
`
`Chapter 8. General Programmable Interface (GPIF)
`
`Page 8-19
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`Exhibit 2032 - Page 193 of 435
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`

`
`EZ-USB FX Technical Reference Manual
`
`8.5.4 Starting GPIF Waveform Transactions
`
`Important: The following sections are critical to understanding how the GPIF works.
`
`The 8051 can trigger four types of GPIF Transactions:
`
`Single Read Transactions
`Single Write Transactions
`FIFO Read Transactions
`FIFO Write Transactions.
`
`Single Transactions produce a single data transfer using one of the GPIF Waveforms you have
`designed. Single Transactions are typically used to access a control register of a device con-
`nected to the GPIF.
`
`FIFO Transactions involve the A and B FIFOs. Multiple bytes of data can be written to a FIFO and
`a transaction can be started that transfers all of the data using the GPIF Waveforms you have
`designed. FIFO Transactions are typically used to move bursts of data to or from a device con-
`nected to the GPIF.
`
`8.5.4.1 Performing a Single Read Transaction
`
`To perform a Single Read Transaction, follow these steps:
`
`1. Program the 8051 to initialize the GPIF registers and Waveform Descriptors.
`2. Program the 8051 to read the SGLDATLTRIG Register to start a single transaction (using the
`movx instruction).
`3. Program the 8051 to wait for the GPIF to indicate that the transaction is complete.
`
`A Transaction is complete when either DONE = 1 (in the IDLE_CS Register), or a GPIF Com-
`plete interrupt is generated.
`
`4. Depending on the Bus Width Mode and the programmer’s desire to start another Transaction,
`the 8051 can retrieve the data from the SGLDATH, SGLDATLTRIG, and/or the SGLDATLN-
`TRIG Register.
`
`In 16-bit mode only, the 8051 reads the most significant byte of data from the SGLDATH Reg-
`ister.
`
`In 8- and 16-bit modes, the 8051 reads the least significant byte of data by either:
`
`reading SGLDATLTRIG, which reads the least significant byte and starts another Single
`Read Transaction.
`
`reading SGLDATLNTRIG, which reads the least significant byte but does not start
`another Read Transaction.
`
`Page 8-20
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`EZ-USB FX Technical Reference Manual v1.2
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`Exhibit 2032 - Page 194 of 435
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`(cid:127)
`(cid:127)
`(cid:127)
`(cid:127)
`(cid:127)
`(cid:127)
`

`
`The following C program fragment illustrates how to perform a single Read transaction in 8-bit
`mode:
`
`// Declare some byte-wide variables.
`unsigned char dummy, inDataLow, inDataHigh ;
`
`// Initiate a (previously set up) GPIF Read transaction by reading
`// the SGLDATLTRIG Register (into the variable dummy).
`
`dummy = SGLDATLTRIG;
`// Note: we are not yet ready to get the data; this register read
`// merely initiates the Read transaction by starting a GPIF
`// microcode routine.
`
`// If the GPIF microcode can take longer than one 8051 instruction,
`// we must wait for it to complete.
`// Otherwise, when reading the data below, we would be reading it
`// prematurely, and it would probably be garbage.
`
`while (IDLE_CS & 0x80)
` ;
`
`// Spin until the 0x80 bit of
`// the IDLE_CS Register is
`// cleared.
`
`// Get the LS data byte, but do not start a new Read transaction.
`inDataLow = SGLDATLNTRIG;
`
`// For 16-bit mode, we would need to add the following line to
`// get the MS data byte.
`inDataHigh = SGLDATH;
`
`Chapter 8. General Programmable Interface (GPIF)
`
`Page 8-21
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`Exhibit 2032 - Page 195 of 435
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`EZ-USB FX Technical Reference Manual
`
`8.5.4.2 Performing a Single Write Transaction
`
`Single Write Transactions are simpler than Single Read Transactions. To run a Single Write Trans-
`action perform the following steps:
`
`1. Program the 8051 to initialize the GPIF registers and Waveform Descriptors.
`2. Program the 8051 to write the SGLDATLTRIG Register to start a single transaction (using the
`movx instruction).
`In 16-bit mode, the most significant byte of the data is first written to the SGLDATH Regis-
`ter.
`
`In both 8- and 16-bit modes, the 8051 starts a Single Write Transaction by writing to the
`SGLDATLTRIG Register.
`
`3. Program the 8051 to wait for the