EXH IBIT 2008
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`EXHIBIT 2008
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`Trials@uspto.gov
`Tel: 571-272-7822
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` Paper 9
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` Entered: March 21, 2013
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_______________
`
`CHIMEI INNOLUX CORPORATION
`Petitioner
`
`v.
`
`SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
`Patent Owner
`_______________
`
`Case IPR2013-00038
`Patent 7,956,978 B2
`_______________
`
`
`
`Before SALLY C. MEDLEY, KARL D. EASTHOM, and
`KEVIN F. TURNER, Administrative Patent Judges.
`
`EASTHOM, Administrative Patent Judge.
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`Patent Owner Exhibit 2008
`Petition for IPR Review of Patent No. 6,012,103
`Page 1
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`Case IPR2013-00038
`Patent 7,956,978
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`I. BACKGROUND
`Petitioner, Chimei Innolux Corp. (“CMI”), filed a Petition1 to institute an
`inter partes review of claims 7 and 17 of U.S. Patent 7,956,978 owned by
`Semiconductor Energy Laboratory Co., Ltd. (“SEL”). See 35 U.S.C. § 311. In
`response, Patent Owner, SEL, filed a Preliminary Response.2 For the reasons that
`follow, the Board hereby institutes an inter partes review of the ‘978 patent. See
`35 U.S.C. § 314.
`The standard for instituting an inter partes review is set forth in 35 U.S.C.
`§ 314(a):
`THRESHOLD – The Director may not authorize an inter partes
`review to be instituted unless the Director determines that the
`information presented in the petition filed under section 311 and any
`response filed under section 313 shows that there is a reasonable
`likelihood that the petitioner would prevail with respect to at least 1 of
`the claims challenged in the petition.
`Pursuant to the defined threshold under 35 U.S.C. § 314(a), the Board
`institutes an inter partes review of claims 7 and 17 of the ‘978 Patent.
`
`
`A. The ‘978 Patent
`The ‘978 patent describes LCD (liquid-crystal display) devices having two
`opposing substrates bonded together with a sealing material. (See Ex. 1001, col. 1,
`ll. 7-11.) According to the ‘978 patent, prior art LCD devices have non-uniform
`seals which create an uneven gap between the two opposing substrates. The
`uneven gap ultimately results in deteriorated LCD image quality. (See Ex. 1001,
`col. 2, ll. 38-49.) The uneven seal and consequent gap occur because peripheral
`
`
`1 Request for Inter Partes Review of U.S. Patent No. 7,956,978 Under 35 U.S.C.
`§§ 311-319 and 37 C.F.R. § 42.100 Et Seq. (mailed Nov. 9, 2012).
`2 Preliminary Response of the Patent Owner (Feb. 8, 2013).
`2
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`Patent Owner Exhibit 2008
`Petition for IPR Review of Patent No. 6,012,103
`Page 2
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`conductingg lines travverse the seealing regiion in a no
`rcuits and
`drive ci
`n-uniform
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`, for exampple, on twoo sides of aa substratee instead off all four. ((See id. annd
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`manner
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`id. at Fiig. 17; col. 1, l. 62 to col. 2, l. 66.) The invvention of tthe ‘978 paatent solvees
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`problem bby using duummy wiriing sectionns which arre nearly e
`the seal
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`qual in heiight
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`to the otther conduuctive liness traversingg the seal i
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`render thee seal and
`n order to
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`consequuent gap beetween oppposing subbstrates moore uniformm. (See id.
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`at Fig. 1; ccol.
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`3, ll. 20-28; col. 6, ll. 37-41;; col. 7, l. 558 to col. 88, l. 17; coll. 14, ll. 399-47; col. 116,
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`ll. 10-244.)
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`PPatent Ownner SEL’s PPreliminaryy Responsse reproducces and annnotates
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`Figures 1 and 9 from the ‘9778 patent too aid in unnderstandinng the claimmed inventtion:
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`FFigure 1 suppra represeents the topp view of tthe lower ssubstrate oof an
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`exemplaary LCD ddevice whicch incorpoorates, into
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`the area RR1 under seeal 107, thee
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`dummyy wiring strructures deepicted in aadjacent Fiigure 9. (SSee Prelim.
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` Resp. 14--16.)
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`AAs indicated supra, thhese dummmy wiring sstructures rrender the
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`seal and thhe
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`consequuent substrrate-to-subsstrate gap mmore evenn. (See alsoo Prelim. RResp. 14-1
`6
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`ly
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`(SEL diiscussing thhe ‘978 paatent inventtion).) Claaims 7 andd 17 do nott specifical
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`recite duummy struuctures, butt the claimms require aapparent siimilar funcctional
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`3
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`Patent Owner Exhibit 2008
`Petition for IPR Review of Patent No. 6,012,103
`Page 3
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`Case IPR2013-00038
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`structure essentially as follows: a portion of first and second isolated conductive
`layers overlapped with a sealing member which extend longer than a pitch of
`adjacent ones of a plurality of second conductive lines. (See Prelim. Resp. 15 and
`Figures 1 and 9 supra.)
`
`
`B. Illustrative Claim
`
`Claim 7 follows:
`7. A display device comprising:
`
` a
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` first substrate having a first side edge extending in a first direction
`and a second side edge extending in a second direction
`orthogonal to the first direction;
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` plurality of first conductive lines extending over the first substrate in
`the first direction;
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` plurality of second conductive lines extending over the first
`substrate in the second direction;
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` a
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` a
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`an insulating film disposed between the plurality of first conductive
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`lines and the plurality of second conductive lines;
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` a
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` plurality of thin film transistors electrically connected to the
`plurality of first conductive lines and the plurality of second
`conductive lines;
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` plurality of pixel electrodes electrically connected to the plurality of
`thin film transistors;
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` second substrate opposed to the first substrate;
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` a
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` a
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` a
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` sealing member disposed between the first substrate and the second
`substrate, the sealing member having a portion adjacent to the
`first side edge; and
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`at least first and second conductive layers formed from a same layer
`4
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`Patent Owner Exhibit 2008
`Petition for IPR Review of Patent No. 6,012,103
`Page 4
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`as the plurality of second conductive lines, wherein at least a
`part of each of the first and second conductive layers is
`overlapped with the portion of the sealing member,
`
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`wherein a length of the first conductive layer along the first direction
`and a length of the second conductive layer along the first
`direction are longer than a pitch of adjacent ones of the plurality
`of second conductive lines,
`
`
`wherein the first and second conductive layers are electrically isolated
`from both of the plurality of first conductive lines and the
`plurality of second conductive lines, and
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`wherein the first and second conductive layers are electrically isolated
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`from each other.
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`
`
`C. Prior Proceedings
`The ‘978 patent is involved with other related patents in infringement
`litigation styled as Semiconductor Energy Laboratory Co., Ltd. v. Chimei Innolux
`Corp., et al., SACV12-0021-JST (C.D. Cal.) (filed Jan. 5, 2012) [hereinafter the
`CMI Case]. (Pet. 2; Prelim. Resp. 4; Ex. 2001.)
`
`D. The Asserted Grounds
`CMI asserts the following three obviousness grounds of unpatentability
`under 35 U.S.C. § 103:
`Claims 7 and 17 based on Sono, U.S. 5,513,028 (Apr. 30, 1996).
`Claims 7 and 17 based on asserted admitted prior art in the ‘978 patent and
`elsewhere of record described further below (“Admitted Art”), and Sono.
`Claims 7 and 17 based on the asserted Admitted Art, Sono, and Watanabe,
`U.S. 5,504,601 (Apr. 2, 1996).
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`5
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`Patent Owner Exhibit 2008
`Petition for IPR Review of Patent No. 6,012,103
`Page 5
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`II. ANALYSIS
`A. Statutory Threshold Issues
`1. Prosecution History of the ‘978 Patent
`SEL contends that CMI’s petition for inter partes review of the ‘978 patent
`is improper under 35 U.S.C. § 325(d) because during prosecution of the application
`leading to the ‘978 patent, the PTO examiner previously considered Sono,
`Watanabe, Admitted Art, and an expert report and other litigation documents from
`a previous district court trial involving a related patent. (See Prelim. Resp. 7-11.)3
`In general, SEL shows that the documents were listed as part of the prosecution
`record of the ‘978 patent which is a factor under 35 U.S.C. § 325(d) which the
`Board “may take into account.” However, SEL does not allege that the examiner
`of the ‘978 patent application considered “substantially the same . . . arguments,”
`as CMI presents here, another factor which the Board “may take into account”
`under 35 U.S.C. § 325(d).
`Absent a showing of “substantially the same . . . arguments,” id., and
`considering that CMI includes evidence not considered before the ‘978 patent
`examiner, including the declaration of Miltiadis Hatalis, Ph.D. (“Hatalis
`Declaration”) (Ex. 1005), SEL does not show that the inter partes review of the
`‘978 Patent would be improper under 35 U.S.C. § 325(d).
`2. Real Parties-In-Interest
`SEL also contends that this review should be denied because the Petition
`fails to identify all of the real parties-in-interest as required by 35 U.S.C. § 312
`(a)(2) and 37 C.F.R. § 42.8(b)(1). (Prelim. Resp. 3-7.) The Trial Practice Guide
`provides guidance regarding factors to consider in determining whether a party is a
`
`3 SEL mentions “material litigation reports” but only attaches the “Expert Report of
`Dr. Aris Silzars . . .” to its Preliminary Response. (See Prelim. Resp. 9, 10 (citing
`Ex. 2007).)
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`Petition for IPR Review of Patent No. 6,012,103
`Page 6
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`real party-in-interest. As SEL acknowledges, a primary consideration includes
`whether a non-party exercises control over a petitioner’s participation in a
`proceeding. (See Prelim. Resp. 3-4, citing Office Patent Trial Practice Guide, 77
`Fed. Reg. 48759-60 (August 14, 2012).) Other considerations may include
`whether a non-party, in conjunction with control, funds the proceeding and directs
`the proceeding. (Trial Practice Guide at 60.)
`SEL asserts that co-defendants with CMI (“CMO USA,” “Acer America,”
`“ViewSonic,” “VIZIO,” and “Westinghouse”) in the pending CMI Case (see supra
`section I.C) represented to the district court that the co-defendants all participated
`in filing the instant Petition in support of a district court motion to stay, and that
`the co-defendants all agreed to be bound by the Inter Partes Review. (See Prelim.
`Resp. 1-7.) SEL focuses on statements to the district court in which the co-
`defendants refer to “their” Petition which “Defendants have moved expeditiously
`to prepare and file.” (Prelim. Resp. 5.)
`Notwithstanding SEL’s assertions, SEL does not set forth persuasive
`evidence that the district court co-defendants CMO USA, Acer America,
`ViewSonic, VIZIO, and Westinghouse necessarily have any control over this
`proceeding. The statements that SEL refer to are just that. SEL has not shown
`persuasively that the statements mean what SEL suggests they mean. For example,
`the statements made in connection with the joint motion to stay may have been a
`short-hand explanation or joint litigation approach (e.g., speaking as one unified
`voice as opposed to explaining in great length who filed the Petition, etc.) to the
`district court of the events leading up to the filing of the instant Petition. The
`collective filing of a motion to stay, where the co-defendants collectively refer to
`the instant Petition, need not indicate control, without more proof. It is likely that
`no such stay would have been granted without all co-defendants agreeing to the
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`estoppel provision.
`Moreover, SEL has not shown, for example, that the co-defendants CMO
`USA, Acer America, ViewSonic, VIZIO, and Westinghouse necessarily co-
`authored the Petition or exerted control over its contents, or will exert any control
`over the remaining portions of this proceeding. SEL has failed to provide
`persuasive evidence that the co-defendants in the CMI Case exercised control or
`provided funding for the instant Petition, let alone exercised control and funding.
`That the co-defendants agree to be bound by the decision of this inter partes
`review insofar as the co-pending litigation is concerned does not dictate that the
`co-defendants are real parties-in-interest in this proceeding. Accordingly, SEL has
`not demonstrated that CMI has failed to list all the real parties-in-interest under 35
`U.S.C. § 312 (a)(2) and 37 C.F.R. § 42.8(b).
`
`B. Claim Construction
`The Board interprets each claim in an inter partes review using the
`“broadest reasonable construction in light of the specification of the patent in
`which it appears.” 37 C.F.R. § 42.100(b). See also Office Patent Trial Practice
`Guide, 77 Fed. Reg. 48756, 48766 (Aug. 14, 2012) (Claim Construction).
`“Generally speaking, we indulge a ‘heavy presumption’ that a claim term carries
`its ordinary and customary meaning.” See CCS Fitness, Inc. v. Brunswick Corp.,
`288 F.3d 1359, 1366 (Fed. Cir. 2002). Tempering the presumption, claims “must
`be read in view of the specification. . . . [T]he specification is always highly
`relevant to the claim construction analysis. Usually, it is dispositive; it is the single
`best guide to the meaning of a disputed term.” See Phillips v. AWH Corp., 415
`F.3d, 1303, 1317 (Fed. Circ. 2005) (en banc).
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`8
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`r distance between, aadjacent seecond condductive linees.”
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`TThe followiing claim cconstructioon applies.
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`and the paarties agreee, that pitchh
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`PPitch. Distaance. The ‘978 patennt implies,
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`means ddistance. ((See Fig. 9 (depictingg P1 and P22 as indicaating distannce).) For
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`examplee, Dr. Silzaars, SEL’s trial experrt (supra nnote 3), inddicates that
`distance
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`relates tto “a pitch of adjacennt second cconductive
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`lines.” (EEx. 2007, 222.) CMI
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`similarlly refers to “‘pitch’ o
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`(Pet. 244.)
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`BBlack Matrix. A layeer which blocks light
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`to anotherr layer or thhe same laayer
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`renderinng it “blackk.” (See EEx. 1003, cool. 3, ll. 644-66; Ex. 1
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`001, col. 22, ll. 59-644;
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`Ex. 10005, ¶ 34, n.333; Ex. 20
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`07, 12-13.) Further ddiscussionn about thiss claim
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`construcction appears below.
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`AAll other terms are givven their oordinary annd customaary meaninng that thosse
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`terms wwould have to a persoon of ordinaary skill inn the art in
`light of th
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`e ‘978 pateent
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`specificcation.
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` C. Assserted Groounds of UUnpatentabiility
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`. Sono
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`reproducees figures ffrom
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`Relying on the Hatalis Declaratiion (Ex. 10005), CMI
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`the ‘9788 patent annd Sono (Ex. 1005) annd explainns how Sonno disclosees or renderrs
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`obviouss the limitaations recited in claimms 7 and 177. (See Pe
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`t. 14-32.)
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`SSono’s Figuure 1, depicting an LCCD devicee, appears nnext:
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`1 R
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`3, col. 1, lll.
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`er
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`uneven se
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`SSono’s Figuure 1 depiccts a prior aart device hhaving an
`al 32. As
`the pixel
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`depictedd, the unevven seal 322 creates ann uneven liiquid crysttal 33 over
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`display area thereuunder whicch distorts the LCD iimage. (Seee Ex. 100
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`15-45.)
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`SSono’s soluution generrally involvves produccing dummmy electroddes and oth
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`dummyy circuit eleements or wwiring undder the seall to producce a uniformm surface
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`id crystal aand seal. ((See Ex. 10003, Abstraact, col. 2,
` ll.
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`upon whhich to forrm the liqu
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`-34.)
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`14-24; ccol. 3, ll. 1
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`dummyy pixel areaas 7, 7’:
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`SSono’s Figuure 4 beloww shows, innter alia, aa pixel dispplay area 88, 8’ and
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`FFigure 4 alsso depicts eelectrodes 4 and thinn film transsistors 3 (TTFT) in thee
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`dummyy pixel and pixel areas. The dummmy electrrodes and ttransistors
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` in the dummmy
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`pixel arreas may bee on all fouur sides of f the pixel aarea and issolated fromm peripherral
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`and dispplay circuits by cuttinng wires orr not makinng electriccal connecttions. (Seee Ex.
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`1003, cool. 3, ll. 377-53; col. 44, ll. 17-32
`.)
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`FFigure 5 below showss electrode
`near ectrodes 4 nmy pixel eles 4, includding dumm
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`1:
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`the subsstrate edgees, in an inssulator 22 on top of ssemiconduuctor TFT ssubstrate 2
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`Figure 5 alsso depicts sseal 25 andd liquid cryystal 24 beetween twoo substratess
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`and shieeld 29 abovve the two substratess. (See Ex.. 1003, coll. 4, ll. 34-446.)
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`TThe dummyy pixel elecctrodes andd TFTs maay be connnected to diisplay 1 annd
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`scanninng 2 lines (ssee Figure 4) but neeed not be coonnected tto peripherral driving
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`circuits.. (See Ex.
`1003, col.
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` 4, ll. 34-446.)
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`FFigures 7 annd 8 beloww representt different vviews of thhe LCD deevice inclu
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`the centtral pixel ddisplay areaa 71 and peeripheral ddriving circcuits 72-755:
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`ding
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`Figure 8 reppresents a cross-sectiional view
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`of Figure
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`7. (See Exx. 1003, cool. 2,
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`ll. 39-422.)
`the
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`SSono explaiins that perripheral sccanning cirrcuits 72, 773 are creatted during
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`same prrocess as ddummy circcuits 74, 755 and that tthe sealantt 76 overlaaps all fourr
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`patterneed circuits 72-75 in oorder to prooduce a uniiform crysstal gap (beetween
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`substrattes 78 and 79) and exxcellent immage qualityy. (See Exx. 1003, co
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`l. 5, ll. 13--15;
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`col. 6, ll. 28-39.) The four ““patterns 72-75 of a ssame step aare provideed on four
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`sides off a pixel areea 71 on thhe semiconnductor subbstrate 78.”” (Id. at ll
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`. 29-32.)
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`WWith respecct to claimss 7 and 17,, CMI geneerally citess to Sono’ss Figures 44, 7,
`as
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`and 8 annd points to dummy ppixel areass 7 and 7’ aand dummmy circuits 774 and 75
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`satisfyinng the claimm limitatioon “at leastt first and ssecond connductive laayers formeed
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`from a ssame layerr as the pluurality of seecond condductive linnes, whereinn at least aa
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`part of eeach of thee first and ssecond connductive laayers is oveerlapped wwith the porrtion
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`of the seealing memmber.” (Seee Pet. 19-221 and 28--30.)
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`SSEL contests CMI’s rreading forr several reeasons. Reegarding thhe overlap
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`requiremment, CMII reasons thhat Sono’s sealing mmember 76 ddoes not ovverlap the
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`dummyy pixel areaas 7 and 7’. (See id. aat 21 (“the dummy arrea (dummmy pixels) ddo
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`not overlap the sealing area”).) SEL similarly maintains that CMI conflates Sono’s
`teachings related to the dummy pixel areas 7, 7’and dummy circuit areas 74, 75.
`(See Prelim. Resp. 22-28.) In other words, SEL maintains that Sono distinguishes
`“dummy areas” (as dummy pixel areas 7, 7’) from Sono’s dummy circuit areas 74,
`75, and thereby fails to teach the overlap element recited in the claims.
`SEL’s argument does not overcome CEL’s showing. Sono generally
`discloses overlapping the “dummy areas” and other circuit or wiring areas with the
`sealant 76. For example, as CMI notes, Sono states that a “‘sealing area [76] may
`be provided on an area of substantially same height as that of the display area . . .
`not only on circuit elements but also on wirings or dummy areas of a same step
`height.’” (See Pet. 23 (quoting Ex. 1003, col. 7, ll. 39-42).) CMI also points out
`that Sono teaches that “‘the shape of a step, to be formed adjacent to the pixel area
`may be made the same as, or substantially same as or similar to that of the pixel
`area by a dummy area, a circuit element or a wiring alone or by a combination
`thereof.’” (Pet. 21-22 (quoting Ex. 1003, col. 7, ll. 46-50).)
`As indicated supra, CMI also relies on dummy scanning circuit areas 74 and
`75 to satisfy the first and second conductive layers recited in claims 7 and 17. (See
`Pet. 21-23 citing Ex. 1003, at Figs. 7-8.) Sono supports CMI’s characterization of
`Figures 7 and 8 by describing “liquid crystal sealing areas 76 on said patterns”; i.e.,
`“patterns 72-75 of a same step are provided on the four sides of pixel area 71 on
`the semiconductor substrate 78.” (Ex. 1003, col. 6, ll. 28-37.)
`In other words, Sono contemplates that the sealing area 76 can overlap
`circuit elements and wirings, including, but not limited to, dummy circuits 74, 75,
`and dummy pixel areas 7, 7’, all in order to obtain a uniform seal and gap.
`SEL also contests CMI’s reading of the “same layer” requirement in the
`claims: “at least first and second conductive layers formed from a same layer as the
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`plurality of second conductive lines.” CMI maintains that Sono teaches that the
`dummy circuit 74 includes first and second conductive layers which are formed
`from part of the same layer as the second conductive lines 1. (See Pet. 19, 21-23,
`28-30.)
`SEL argues that Sono does not teach a plurality of second conductive lines
`(Prelim. Resp. 24) and that “the rectangular blocks in semiconductor substrate 78
`associated with elements 73 and 75 appear to be source and drain regions of a
`transistor, not ‘multiple conducting lines.’” (See id. at 25 (discussing Hatalis
`Declaration).) SEL also asserts that “such rectangular blocks” are not “conductive
`layers.” (Id. at 24.) SEL similarly asserts that Dr. Hatalis’s opinion that the
`dummy circuits 74 and 75 include wiring and other circuits under the sealing area
`76 is in error because Figures 7 and 8 show no such wiring, and, as addressed
`supra, Dr. Hatalis allegedly conflates Sono’s dummy circuits and dummy areas.
`(See id. at 24-30.)
`SEL’s arguments are not persuasive partly for the reasons discussed above.
`For example, Sono describes elements 73 and 75 as pertaining respectively to real
`and dummy peripheral display or scanning circuits as noted above – not TFTs as
`SEL argues. (See Ex. 1003, col. 5, ll. 1-13; col. 6, ll. 27-37.) In light of this
`disclosure, the designations 73 and 75 in Figure 8 generally point to circuit regions
`(i.e., conductive layers) at the peripheries of the LCD lower substrate and under the
`sealant 76 as Figures 7 and 8 also indicate.
` As also indicated above, Sono teaches that “[t]he present embodiment can
`provide a uniform liquid crystal cell gap, because patterns 72-75 of same step are
`provided on the four sides of a pixel area 71 on the semiconductor substrate, and
`liquid crystal sealing areas are provided on said patterns.” (Ex. 1003, col. 6, ll. 27-
`31.) Sono discloses that “excellent reproducibility is ensured because dummy
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`circuits 74, 75 can be prepared in the same process as for the peripheral scanning
`circuits.” (Ex. 1003, col. 6, ll. 34-36 (emphasis added).)
`CMI similarly quotes Sono’s disclosure of a “‘same step’” for the scanning,
`driving and dummy circuits 72-75 (see Pet. 21 (quoting Ex. 1003 at col. 5, ll. 8-11)
`and Sono’s disclosure of “‘dummy pixels of a same configuration, having same
`wirings, switching elements, pixel electrodes etc. as in the display area [wherein] .
`. . additional steps are not required’” (id. (quoting Ex. 1003 at col. 3, ll. 17-27).) In
`other words, Sono teaches using a minimal number of process steps to create metal
`layers in the display region 71 (which includes dummy pixel regions 7, 7’). Sono
`also teaches using a minimal number of process steps to create the metal circuit
`layers in the peripheral circuits 72-75. In conjunction, as indicated supra, Sono
`generally teaches uniformity of height of the metal layers across the device “in any
`manner” (Ex. 1003, col. 3, ll. 14-15) and specifically across the boundary between
`the two general regions under the sealant in order to create a uniform substrate-to-
`substrate gap. (See id. at ll. 1-6.)
`For example, Sono’s symmetrical patterns 72-75 include similar wiring and
`dummy circuits under the sealing areas to ensure a uniform sealing gap. Figure 7
`represents scan and driving lines 1, 2 (see Fig. 4 which has lines 1, 2 corresponding
`to similar unnumbered conductive lines in Fig. 7) between the pixel area 71 and
`peripheral circuit areas 72 and 73, and Figure 7 also shows a portion of these lines
`traversing the sealing area 76 (with the circuit areas 72-75). Therefore, given
`Sono’s teaching of using a minimal number of process steps to create uniform
`wiring and metal steps across the sealant gap, CMI has shown that Sono suggests
`making a portion of the driving and scanning lines 1, 2 from the same layer as the
`dummy pixel areas or the peripheral circuits 72-75. (See Pet. 19-23.)
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`SSEL also mmaintains thhat Sono dooes not rennder obviouus the claimm 7 and 177
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`limitatioon “whereiin a lengthh of the firsst conductivve layer allong the firrst directioon
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`and a leength of thee second coonductive layer alongg the first
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`direction aare longer tthan
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`a pitch oof adjacentt ones of thhe pluralityy of secondd conducti
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`Resp. 30-37.) Disscussing Fiigure 4 of Sono, SELL argues thhat the firstt and seconnd
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`conducttive layers,, which SEEL identifiees as the hoorizontal sscanning linnes 2, are nnot
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`formed from the ssame layer as the plurrality of coonductive llines 1, whhich SEL
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`identifiees as the veertical signnal lines. ((See Prelimm. Resp. 344-36.)
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`SSEL’s annootated Figuure 4 from Sono appeears next.
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`SSEL’s annootated Figuure 4 showss horizontaal lines 2 loonger thann a pitch of f
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`adjacennt vertical lines 1. (Seee Prelim. Resp. 35.))
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`SSEL maintaains that linnes 1 and 22 in Sono ““are only ppotentially
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`the samme layer.” ((Prelim. Reesp. 36.) SSEL’s arguument is noot germanee to CMI’s
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`positionn. In other
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`words, evven if SEL is correct tthat Sono ddoes not diisclose thaat the
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`horizonntal lines 2 and verticaal lines 1 aare formed d “from a saame layer”” as claimss 7
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`and 17 rrecite, CMMI does not rely on Figure 4 in tthe mannerr SEL arguues. Ratherr, as
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`discusseed further bbelow, CMMI relies onn the dummmy circuit aarea 74 forr the first aand
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`recited second conductive layers and the vertical lines 1 for the recited second
`conductive lines. (See Pet. 23-24.)4
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`Specifically, CMI relies on Sono’s teachings directed to metal step lengths
`in the dummy circuit area 74 under the sealant 76, wherein the step length spans at
`least five conductive scanning or display line 2 pitch lengths. (See Pet. 23-24
`(relying on Ex. 1003 at col. 3, ll. 40-43).) In context, Sono refers to “the width of
`such step” as “five scanning lines or display lines” (Ex. 1003, col. 3, l. 40) not only
`in relation to “dummy pixels” but also in relation to “said step . . . formed by the
`circuit elements or wiring provided in the peripheral area” (id. at ll. 28-29). These
`peripheral areas, as discussed supra, include the dummy driver or scanner circuits
`74, 75. (See id. at col. 3, 39-40; col. 6, ll. 34-37.)
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`Dr. Hatalis’s testimony corroborates CMI’s reliance on the dummy area as
`including first and second conductive layers of the claimed length. Dr. Hatalis
`testifies that the peripheral dummy circuit areas would have long conductive layer
`runs along dummy shift register circuits because Sono teaches that the dummy
`circuits 74 and 75 mimic the peripheral shift register circuits 72 and 73. (See Ex.
`1005 ¶¶ 25, 38, 39.) SEL responds by characterizing Dr. Hatalis’s testimony as
`“mere conjecture” (Prelim. Resp. 25) but bases the characterization on the
`unsupported premise that Sono does not teach or suggest making the peripheral
`circuits 72-75 the same. (See id. at 24-25.) As discussed supra, Sono specifically
`teaches making the peripheral circuits the same to ensure a uniform substrate-to-
`substrate gap.
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`SEL has shown that Sono suggests first and second conductive layers in
`dummy area 74 running perpendicularly to conducting lines 1 formed from the
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`4 CMI also does not rely on Sono’s dummy pixel electrodes and TFTs which SEL’s
`related litigation expert report addresses. (See Ex. 2007, 22.) In other words, that
`portion of the report does not aid the inquiry here.
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`same layer thereof and each having a layer length of at least five conducting line 1
`pitch lengths – in order to ensure a uniform seal. (See Pet. 23; Ex. 1003, Figs. 4,
`7.) SEL’s arguments do not overcome CMI’s showing that Sono teaches or
`suggests the above-discussed recited relationships between the conductive lines
`and layers with respect to overlap, same layer, respective directions, and pitch
`length as set forth in claims 7 and 17.
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`SEL also argues that Sono does not suggest that the first and second
`conductive layers are isolated electrically from one another and from the second
`conductive lines as claims 7 and 17 require. (Prelim. Resp. 38-40.) CMI relies on
`Dr. Hatalis and points out that isolation saves power and that Sono’s dummy
`circuits are isolated naturally from one another because the dummy circuits do not
`serve an electrical function. CMI further relies on Sono’s teaching, discussed
`supra, that the dummy pixels are isolated from the scanning lines or display lines.
`(See Pet. 24-25 (citing Hatalis Decl. at ¶ 43).) Sono generally depicts isolated (i.e.,
`unconnected) dummy circuits 74 and 75 (Fig. 7) and teaches “locally cutting of the
`wiring” within dummy pixel circuits to create electrical isolation from driving and
`scanning lines as noted supra. (See Ex. 1003, col. 3, ll. 47-51.)
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`Accordingly, based on the foregoing discussion, SEL’s arguments do not
`overcome CMI’s showing that Sono suggests isolating different metal dummy step
`regions from one another and from conducting lines.
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`SEL also argues that CMI’s showing regarding the black matrix recited in
`claim 17 is deficient. (Prelim. Resp. at 40-42.) CMI relies on teachings in Sono
`describing an opaque layer or shield plate. (See Pet. 16, 30-31, 44-45.) CMI
`explains that Sono’s opaque layer renders the dummy circuits and dummy pixels
`black to create a sharper image. (See Pet. 30-31.)
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`Figures 5 and 6 and associated descriptions in Sono reasonably support
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`CMI’s position. Sono teaches “render[ing] the displayed image sharper by
`forming an opaque layer in a portion corresponding to the dummy area, thereby
`rendering said dummy area completely black.” (Ex. 1003, col. 3, ll. 64-66.) Sono
`also discloses an opaque layer at least over peripheral portions of the display. (See
`id. at col. 3, l. 67 to col. 4, l. 5.) Sono similarly teaches surrounding a display area
`“by a completely black area, so that the displayed image appears sharper.” (Id. at
`Fig. 6; col. 4, ll. 62-64.)
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`SEL’s argument is two-fold. First, SEL maintains that even if Sono’s
`opaque or shield layer is a black matrix, it is not over first and second conductive
`line intersections and first and second conductive layers, as claim 17 requires.
`However, as the quotations supra and Figure 6 indicate, Sono teaches or suggests
`covering peripheral display areas which would include the dummy pixel and circuit
`areas which in turn would include