CY7C68053
`MoBL-USB™ FX2LP18 USB
`Microcontroller
`
`■ Integrated, Industry Standard Enhanced 8051
`❐ 48 MHz, 24 MHz, or 12 MHz CPU operation
`❐ Four clocks per instruction cycle
`❐ Three counter/timers
`❐ Expanded interrupt system
`❐ Two data pointers
`■ 1.8 V Core Operation
`■ 1.8 V to 3.3 V I/O Operation
`■ Vectored USB Interrupts and GPIF/FIFO Interrupts
`■ Separate Data Buffers for Setup and Data Portions of a
`CONTROL Transfer
`■ Integrated I2C Controller, runs at 100 or 400 kHz
`■ Four Integrated FIFOs
`❐ Integrated glue logic and FIFOs lower system cost
`❐ Automatic conversion to and from 16-bit buses
`❐ Master or slave operation
`❐ Uses external clock or asynchronous strobes
`❐ Easy interface to ASIC and DSP ICs
`■ Available in Industrial Temperature Grade
`■ Available in one Pb-free Package with up to 24 GPIOs
`❐ 56-pin VFBGA (24 GPIOs)
`
`
`
`1. Features
`■ USB 2.0 9 V USB-IF high speed and full speed compliant (TID#
`40000188)
`■ Single-chip integrated USB 2.0 transceiver, smart SIE, and
`enhanced 8051 microprocessor
`■ Ideal for mobile applications (cell phone, smart phones, PDAs,
`MP3 players)
`❐ Ultra low power
`❐ Suspend current: 20 µA (typical)
`■ Software: 8051 Code runs from:
`❐ Internal RAM, which is loaded from EEPROM
`■ 16 kBytes of on-chip code/data RAM
`■ Four programmable BULK/INTERRUPT/ISOCHRONOUS
`endpoints
`❐ Buffering options: double, triple, and quad
`■ Additional Programmable (BULK/INTERRUPT) 64-Byte
`Endpoint
`■ 8 or 16-Bit External Data Interface
`■ Smart Media Standard ECC Generation
`■ GPIF (General Programmable Interface)
`❐ Allows direct connection to most parallel interface
`❐ Programmable waveform descriptors and configuration
`registers to define waveforms
`❐ Supports multiple Ready and Control outputs
`Logic Block Diagram
`
`24 MHz
`Ext. XTAL
`
`High-performance microprocessor
`using standard tools
`with lower-power options
`
`MoBL-USB FX2LP18
`
`I2C
`Master
`
`Additional IOs (24)
`
`Abundant IO
`
`GPIF
`
`RDY (2)
`CTL (3)
`
`ECC
`
`General
`Programmable I/F
`To Baseband Processors/
`Application Processors/
`ASICS/DSPs
`
`4 KB
`FIFO
`
`8/16
`
`Up to 96 MBytes/sec
`Burst Rate
`
`Address(16)/DataBus(8)
`
`VCC
`
`x20
`PLL
`
`/0.5
`/1.0
`/2.0
`
`1.5K
`Connected for
`Full-Speed
`
`8051 Core
`12/24/48 MHz,
`Four Clocks/Cycle
`
`D+
`
`D–
`
`USB
`2.0
`XCVR
`
`CY
`Smart
`USB
`1.1/2.0
`Engine
`
`16 KB
`RAM
`
`Integrated
`Full- and High-Speed
`XCVR
`
`Enhanced USB Core
`Simplifies 8051 Code
`
`“Soft Configuration”
`Easy Firmware Changes
`
`FIFO and Endpoint Memory
`(Master or Slave Operation)
`
`Cypress Semiconductor Corporation
`Document # 001-06120 Rev *J
`
`•
`
`198 Champion Court
`
`•
`
`San Jose, CA 95134-1709
`408-943-2600
`•
` Revised October 28, 2010
`
`[+] Feedback
`
`Exhibit 2036 - Page 01 of 42
`
`

`

`CY7C68053
`
`Contents
`Applications ......................................................................3
`Functional Overview ........................................................3
`USB Signaling Speed ..................................................3
`8051 Microprocessor ...................................................3
`I2C™ Bus ....................................................................4
`Buses ..........................................................................4
`USB Boot Methods ......................................................4
`ReNumeration™ ..........................................................4
`Bus-Powered Applications ..........................................4
`Interrupt System ..........................................................4
`Reset and Wakeup ......................................................6
`Program/Data RAM .....................................................7
`Register Addresses .....................................................7
`Endpoint RAM .............................................................7
`External FIFO Interface ...............................................9
`GPIF ............................................................................9
`ECC Generation[6] ................................................................... 10
`USB Uploads and Downloads ...................................10
`Autopointer Access ...................................................10
`I2C Controller .............................................................10
`Pin Assignments ............................................................11
`CY7C68053 Pin Descriptions ...................................13
`Register Summary ..........................................................17
`Absolute Maximum Ratings ..........................................24
`Operating Conditions .....................................................24
`DC Characteristics ........................................................24
`
`AC Electrical Characteristics ........................................ 25
`USB Transceiver ....................................................... 25
`GPIF Synchronous Signals ....................................... 25
`Slave FIFO Synchronous Read ................................. 26
`Slave FIFO Asynchronous Read ............................... 27
`Slave FIFO Synchronous Write ................................. 28
`Slave FIFO Asynchronous Write ............................... 29
`Slave FIFO Synchronous Packet End Strobe ........... 29
`Slave FIFO Asynchronous Packet End Strobe ........ 30
`Slave FIFO Output Enable ....................................... 31
`Slave FIFO Address to Flags/Data ........................... 31
`Slave FIFO Synchronous Address ........................... 32
`Slave FIFO Asynchronous Address ......................... 32
`Sequence Diagram .................................................... 33
`Ordering Information ...................................................... 37
`Ordering Code Definitions ......................................... 37
`Package Diagram ............................................................ 38
`PCB Layout Recommendations .................................... 39
`Acronyms ........................................................................ 40
`Document Conventions ................................................. 40
`Units of Measure ....................................................... 40
`Document History Page ................................................. 41
`Sales, Solutions, and Legal Information ...................... 42
`Worldwide Sales and Design Support ....................... 42
`Products .................................................................... 42
`PSoC Solutions ......................................................... 42
`
`Document # 001-06120 Rev *J
`
`Page 2 of 42
`
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`Exhibit 2036 - Page 02 of 42
`
`

`

`Cypress Semiconductor Corporation’s MoBL-USB™ FX2LP18
`(CY7C68053) is a low voltage (1.8 V) version of the EZ-USB®
`FX2LP (CY7C68013A), which is a highly integrated, low power
`USB 2.0 microcontroller. By integrating the USB 2.0 transceiver,
`serial interface engine (SIE), enhanced 8051 microcontroller,
`and a programmable peripheral interface in a single chip,
`Cypress has created a very cost effective solution that provides
`superior time-to-market advantages with low power to enable
`bus powered applications.
`The ingenious architecture of MoBL-USB FX2LP18 results in
`data transfer rates of over 53 Mbytes per second, the maximum
`allowable USB 2.0 bandwidth, while still using a low cost 8051
`microcontroller in a package as small as a 56VFBGA (5 mm x
`5 mm). Because it incorporates the USB 2.0 transceiver, the
`MoBL-USB FX2LP18 is more economical, providing a smaller
`footprint solution than USB 2.0 SIE or external transceiver
`implementations. With MoBL-USB FX2LP18, the Cypress Smart
`SIE handles most of the USB 1.1 and 2.0 protocol in hardware,
`freeing the embedded microcontroller for application-specific
`functions and decreasing development time to ensure USB
`compatibility.
`The General Programmable Interface (GPIF) and Master/Slave
`Endpoint FIFO (8 or 16-bit data bus) provide an easy and
`glueless interface to popular interfaces such as ATA, UTOPIA,
`EPP, PCMCIA, and most DSP/processors.
`The MoBL-USB FX2LP18 is also referred to as FX2LP18 in this
`document.
`2. Applications
`There are a wide variety of applications for the MoBL-USB
`FX2LP18. It is used in cell phones, smart phones, PDAs, and
`MP3 players, to name a few.
`The ‘Reference Designs’ section of the Cypress web site
`provides additional tools for typical USB 2.0 applications. Each
`reference design comes complete with firmware source and
`object code, schematics, and documentation. For more
`information, visit http://www.cypress.com.
`3. Functional Overview
`The functionality of this chip is described in the sections below.
`3.1 USB Signaling Speed
`FX2LP18 operates at two of the three rates defined in the USB
`Specification Revision 2.0, dated April 27, 2000.
`■ Full speed, with a signaling bit rate of 12 Mbps
`■ High speed, with a signaling bit rate of 480 Mbps
`FX2LP18 does not support the low speed signaling mode of
`1.5 Mbps.
`
`CY7C68053
`
`3.2 8051 Microprocessor
`The 8051 microprocessor embedded in the FX2LP18 family has
`256 bytes of register RAM, an expanded interrupt system, and
`three timer/counters.
`
`3.2.1 8051 Clock Frequency
`FX2LP18 has an on-chip oscillator circuit that uses an external
`24 MHz (±100-ppm) crystal with the following characteristics:
`■ Parallel resonant
`■ Fundamental mode
`■ 500 µW drive level
`■ 12 pF (5% tolerance) load capacitors
`An on-chip PLL multiplies the 24 MHz oscillator up to 480 MHz,
`as required by the transceiver/PHY; internal counters divide it
`down for use as the 8051 clock. The default 8051 clock
`frequency is 12 MHz. The clock frequency of the 8051 can be
`changed by the 8051 through the CPUCS register, dynamically.
`Figure 1. Crystal Configuration
`
`C1
`
`24 MHz
`
`C2
`
`12 pF
`
`12 pF
`
`20 × PLL
`
`12 pF capacitor values assumes a trace capacitance
`of 3 pF per side on a four-layer FR4 PCA
`
`The CLKOUT pin, which can be tristated and inverted using
`internal control bits, outputs the 50% duty cycle 8051 clock, at
`the selected 8051 clock frequency — 48, 24, or 12 MHz.
`
`3.2.2 Special Function Registers
`Certain 8051 Special Function Register (SFR) addresses are
`populated to provide fast access to critical FX2LP18 functions.
`These SFR additions are shown in Table 1 on page 4. Bold type
`indicates non standard, enhanced 8051 registers. The two SFR
`rows that end with ‘0’ and ‘8’ contain bit-addressable registers.
`The four I/O ports A–D use the SFR addresses used in the
`standard 8051 for ports 0–3, which are not implemented in
`FX2LP18. Because of the faster and more efficient SFR
`addressing, the FX2LP18 I/O ports are not addressable in
`external RAM space (using the MOVX instruction).
`
`Document # 001-06120 Rev *J
`
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`
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`Exhibit 2036 - Page 03 of 42
`
`

`

`Table 1. Special Function Registers
`x
`8x
`9x
`IOA
`IOB
`0
`EXIF
`1
`SP
`MPAGE
`2
`DPL0
`3
`DPH0
`DPL1
`4
`DPH1
`5
`DPS
`6
`7
`PCON
`8
`TCON
`9
`TMOD
`A
`TL0
`B
`TL1
`C
`TH0
`D
`TH1
`CKCON
`E
`F
`
`SCON0
`SBUF0
`AUTOPTRH1
`AUTOPTRL1
`Reserved
`AUTOPTRH2
`AUTOPTRL2
`Reserved
`
`Ax
`IOC
`INT2CLR
`
`IE
`
`EP2468STAT
`EP24FIFOFLGS
`EP68FIFOFLGS
`
`AUTOPTRSET-UP
`
`CY7C68053
`
`Cx
`SCON1
`SBUF1
`
`Ex
`Dx
`PSW ACC
`
`Fx
`B
`
`T2CON
`
`EICON
`
`EIE
`
`EIP
`
`Bx
`IOD
`IOE
`OEA
`OEB
`OEC
`OED
`OEE
`
`IP
`
`EP01STAT
`GPIFTRIG
`
`GPIFSGLDATH
`GPIFSGLDATLX
`GPIFSGLDATLNOX
`
`RCAP2L
`RCAP2H
`TL2
`TH2
`
`simulate a USB disconnect, the firmware sets DISCON to 1. To
`reconnect, the firmware clears DISCON to 0.
`Before reconnecting, the firmware sets or clears the RENUM bit
`to indicate whether the firmware or the Default USB Device
`handles device requests over endpoint zero: if RENUM = 0, the
`Default USB Device handles device requests; if RENUM = 1, the
`firmware does.
`3.7 Bus-Powered Applications
`The FX2LP18 fully supports bus-powered designs by
`enumerating with less than 100 mA as required by the USB 2.0
`specification.
`3.8 Interrupt System
`The FX2LP18 interrupts are described in this section.
`
`3.3 I2C™ Bus
`FX2LP18 supports the I2C bus as a master only at
`100 or 400 KHz. SCL and SDA pins have open-drain outputs
`and hysteresis inputs. These signals must be pulled up to either
`VCC or VCC_IO, even if no I2C device is connected. (Connecting
`to VCC_IO may be more convenient.)
`3.4 Buses
`This 56-pin package has an 8- or 16-bit ‘FIFO’ bidirectional data
`bus, multiplexed on I/O ports B and D.
`3.5 USB Boot Methods
`During the power up sequence, internal logic checks the I2C port
`for the connection of an EEPROM whose first byte is 0xC2. If
`found, it boot-loads the EEPROM contents into internal RAM
`(0xC2 load). If no EEPROM is present, an external processor
`must emulate an I2C slave. The FX2LP18 does not enumerate
`using internally stored descriptors (for example, Cypress’s
`VID/PID/DID is not used for enumeration).[1]
`3.6 ReNumeration™
`Because the FX2LP18’s configuration is soft, one chip can take
`on the identities of multiple distinct USB devices.
`When first plugged into USB, the FX2LP18 enumerates
`automatically and downloads firmware and USB descriptor
`tables over the USB cable. Next, the FX2LP18 enumerates
`again, this time as a device defined by the downloaded
`information. This patented two-step process, called
`ReNumeration™, happens instantly when the device is plugged
`in, with no hint that the initial download step has occurred.
`Two control bits in the USBCS (USB Control and Status) register
`control the ReNumeration process: DISCON and RENUM. To
`Note
`1. The I2C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly.
`
`3.8.1 INT2 Interrupt Request and Enable Registers
`FX2LP18 implements an autovector feature for INT2. There are
`27 INT2 (USB) vectors. See the MoBL-USB™ Technical
`Reference Manual (TRM) for more details.
`
`3.8.2 USB Interrupt Autovectors
`The main USB interrupt is shared by 27 interrupt sources. To
`save the code and processing time that is normally required to
`identify the individual USB interrupt source, the FX2LP18
`provides a second level of interrupt vectoring, called
`‘Autovectoring.’ When a USB interrupt is asserted, the FX2LP18
`pushes the program counter onto its stack then jumps to address
`0x0043, where it expects to find a ‘jump’ instruction to the USB
`interrupt service routine.
`The FX2LP18 jump instruction is encoded as shown in Table 2
`on page 5.
`
`Document # 001-06120 Rev *J
`
`Page 4 of 42
`
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`Exhibit 2036 - Page 04 of 42
`
`

`

`If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP
`register), the FX2LP18 substitutes its INT2VEC byte. Therefore,
`if the high byte (‘page’) of a jump-table address is preloaded at
`
`location 0x0044, the automatically inserted INT2VEC byte at
`0x0045 directs the jump to the correct address out of the 27
`addresses within the page.
`
`CY7C68053
`
`Table 2. INT2 USB Interrupts
`Priority
`INT2VEC Value
`1
` 00
`2
` 04
`3
` 08
`4
`0C
`5
`10
`6
`14
`7
`18
`8
`1C
`9
`20
`10
`24
`11
`28
`12
`2C
`13
`30
`14
`34
`15
`38
`16
`3C
`17
`40
`18
`44
`19
`48
`20
`4C
`21
`50
`22
`54
`23
`58
`24
`5C
`25
`60
`26
`64
`27
`68
`28
`6C
`29
`70
`30
`74
`31
`78
`32
`7C
`
`Source
`SUDAV
`SOF
`SUTOK
`SUSPEND
`USB RESET
`HISPEED
`EP0ACK
`
`EP0-IN
`EP0-OUT
`EP1-IN
`EP1-OUT
`EP2
`EP4
`EP6
`EP8
`IBN
`
`EP0PING
`EP1PING
`EP2PING
`EP4PING
`EP6PING
`EP8PING
`ERRLIMIT
`
`Notes
`
`Setup data available
`Start of frame (or microframe)
`Setup token received
`USB suspend request
`Bus reset
`Entered high speed operation
`FX2LP18 ACK’d the control handshake
`Reserved
`EP0-IN ready to be loaded with data
`EP0-OUT has USB data
`EP1-IN ready to be loaded with data
`EP1-OUT has USB data
`IN: buffer available. OUT: buffer has data
`IN: buffer available. OUT: buffer has data
`IN: buffer available. OUT: buffer has data
`IN: buffer available. OUT: buffer has data
`IN-Bulk-NAK (any IN endpoint)
`Reserved
`EP0 OUT was pinged and it NAK’d
`EP1 OUT was pinged and it NAK’d
`EP2 OUT was pinged and it NAK’d
`EP4 OUT was pinged and it NAK’d
`EP6 OUT was pinged and it NAK’d
`EP8 OUT was pinged and it NAK’d
`Bus errors exceeded the programmed limit
`
`EP2ISOERR
`EP4ISOERR
`EP6ISOERR
`EP8ISOERR
`
`Reserved
`Reserved
`ISO EP2 OUT PID sequence error
`ISO EP4 OUT PID sequence error
`ISO EP6 OUT PID sequence error
`ISO EP8 OUT PID sequence error
`
`Document # 001-06120 Rev *J
`
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`Exhibit 2036 - Page 05 of 42
`
`

`

`Figure 2. Reset Timing Plots
`
`RESET#
`
`VCC
`
`RESET#
`
`VCC
`
`VIL
`
`1.8 V
`1.62 V
`
`0 V
`
`CY7C68053
`
`VIL
`1.8 V
`
`0 V
`
`TRESET
`
`Power on Reset
`
`TRESET
`
`Powered Reset
`
`3.9 Reset and Wakeup
`The reset and wakeup pins are described in detail in this section.
`
`3.9.1 Reset Pin
`The input pin, RESET#, resets the FX2LP18 when asserted.
`This pin has hysteresis and is active LOW. When a crystal is
`used with the CY7C68053, the reset period must allow for the
`stabilization of the crystal and the PLL. This reset period must be
`approximately 5 ms after VCC has reached 3.0 V. If the crystal
`input pin is driven by a clock signal the internal PLL stabilizes in
`200 μs after VCC has reached 3.0 V[2]. Figure 2 shows a power
`on reset condition and a reset applied during operation. A power
`on reset is defined as the time reset is asserted while power is
`being applied to the circuit. A powered reset is defined as a reset
`in which the FX2LP18 has previously been powered on and
`operating and the RESET# pin is asserted.
`Cypress provides an application note which describes and
`recommends power on reset implementation, which can be
`found on the Cypress web site. For more information on reset
`implementation for the MoBL-USB family of products, visit the
`Cypress web site at http://www.cypress.com.
`
`
`
`Table 3. Reset Timing Values
`Condition
`Power on reset with crystal
`Power on reset with external
`clock
`Powered reset
`
`TRESET
`
`5 ms
`200 μs + clock stability time
`
`200 μs
`
`3.9.2 Wakeup Pins
`The 8051 puts itself and the rest of the chip into a power-down
`mode by setting PCON.0 = 1. This stops the oscillator and PLL.
`When WAKEUP is asserted by external logic, the oscillator
`restarts, after the PLL stabilizes, and then the 8051 receives a
`wakeup interrupt. This applies whether or not FX2LP18 is
`connected to the USB.
`
`The FX2LP18 exits the power down (USB suspend) state using
`one of the following methods:
`■ USB bus activity (if D+/D– lines are left floating, noise on these
`lines may indicate activity to the FX2LP18 and initiate a
`wakeup)
`■ External logic asserts the WAKEUP pin
`■ External logic asserts the PA3/WU2 pin
`The second wakeup pin, WU2, can also be configured as a
`general purpose I/O pin. This allows a simple external R-C
`network to be used as a periodic wakeup source. Note that
`WAKEUP is active LOW by default.
`
`3.9.3 Lowering Suspend Current
`Good design practices for CMOS circuits dictate that any unused
`input pins must not be floating between VIL and VIH. Floating
`input pins will not damage the chip, but can substantially
`increase suspend current. To achieve the lowest suspend
`current, confiigure unused port pins as outputs. Connect unused
`input pins to ground. Some examples of pins that need attention
`during suspend are:
`■ Port pins. For Port A, B, D pins, take extra care in shared bus
`situations.
`❐ Connect completely unused pins to VCC_IO or GND.
`❐ In a single-master system, the firmware must output enable
`all the port pins and drive them high or low, before FX2LP18
`enters the suspend state.
`❐ In a multi-master system (FX2LP18 and another processor
`sharing a common data bus), when FX2LP18 is suspended,
`the external master must drive the pins high or low. The
`external master must not let the pins float.
`■ CLKOUT. If CLKOUT is not used, it must be tri-stated during
`normal operation, but driven during suspend.
`■ IFCLK, RDY0, RDY1. These pins must be pulled to VCC_IO or
`GND or driven by another chip.
`
`Note
`2.
`If the external clock is powered at the same time as the CY7C680xx and has a stabilization wait period, it must be added to the 200 μs.
`
`Document # 001-06120 Rev *J
`
`Page 6 of 42
`
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`Exhibit 2036 - Page 06 of 42
`
`

`

`CY7C68053
`
`3.11 Register Addresses
`Figure 4. Register Address Memory
`
`FFFF
`
`F000
`EFFF
`
`E800
`E7FF
`E7C0
`E7BF
`E780
`E77F
`E740
`E73F
`E700
`E6FF
`
`E500
`E4FF
`E480
`E47F
`E400
`E3FF
`E200
`E1FF
`
`4 kBytes EP2-EP8
`buffers
`(8 x 512)
`
`2 kBytes RESERVED
`
`64 Bytes EP1IN
`
`64 Bytes EP1OUT
`
`64 Bytes EP0 IN/OUT
`
`64 Bytes RESERVED
`
`8051 Addressable Registers
`(512)
`
`Reserved (128)
`
`128 Bytes GPIF Waveforms
`
`Reserved (512)
`
`512 Bytes
`8051 xdata RAM
`
`E000
`3.12 Endpoint RAM
`This section describes the FX2LP18 Endpoint RAM.
`
`3.12.1 Size
`■ 3 × 64 bytes (Endpoints 0, 1)
`■ 8 × 512 bytes (Endpoints 2, 4, 6, 8)
`
`3.12.2 Organization
`■ EP0
`■ Bidirectional endpoint zero, 64-byte buffer
`■ EP1IN, EP1OUT
`■ 64-byte buffers: bulk or interrupt
`■ EP2, 4, 6, 8
`■ Eight 512-byte buffers: bulk, interrupt, or isochronous. EP4 and
`EP8 can be double buffered, while EP2 and 6 can be double,
`triple, or quad buffered. For high speed endpoint configuration
`options, see Figure 5 on page 8.
`
`3.12.3 Setup Data Buffer
`A separate 8-byte buffer at 0xE6B8-0xE6BF holds the setup data
`from a CONTROL transfer.
`
`■ CTL0-2. If tri-stated via GPIFIDLECTL, these pins must be
`pulled to VCC_IO or GND or driven by another chip.
`■ RESET#, WAKEUP#. These pins must be pulled to VCC_IO or
`GND or driven by another chip during suspend.
`
`Figure 3. FX2LP18 Internal Code Memory
`
`FFFF
`
`E200
`E1FF
`
`E000
`
`7.5 kBytes
`USB regs and
`4K FIFO buffers
`
`0.5 kBytes RAM
`Data
`
`. . .
`
`16 kBytes RAM
`Code and Data
`
`3FFF
`
`0000
`
`3.10 Program/Data RAM
`This section describes the FX2LP18 RAM.
`
`3.10.1 Size
`The FX2LP18 has 16 kBytes of internal program/data RAM. No
`USB control registers appear in this space.
`Memory maps are shown in Figure 3 and Figure 4.
`
`3.10.2 Internal Code Memory
`This mode implements the internal 16-kByte block of RAM
`(starting at 0) as combined code and data memory. Only the
`internal 16 kBytes and scratch pad 0.5 kBytes RAM spaces
`have the following access:
`■ USB download
`■ USB upload
`■ Setup data pointer
`■ I2C interface boot load
`
`Document # 001-06120 Rev *J
`
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`Exhibit 2036 - Page 07 of 42
`
`

`

`CY7C68053
`
`3.12.4 Endpoint Configurations (High Speed Mode)
`Endpoints 0 and 1 are the same for every configuration. Endpoint
`0 is the only CONTROL endpoint, and endpoint 1 can be either
`BULK or INTERRUPT. The endpoint buffers can be configured
`in any one of the 12 configurations shown in the vertical columns
`of Figure 5. When operating in full speed BULK mode only the
`first 64 bytes of each buffer are used. For example, in high speed
`
`the maximum packet size is 512 bytes, but in full speed it is 64
`bytes. Even though a buffer is configured to be a 512 byte buffer,
`in full speed only the first 64 bytes are used. The unused
`endpoint buffer space is not available for other operations. An
`example endpoint configuration is:
`EP2–1024 double buffered; EP6–512 quad buffered (column 8).
`
`Figure 5. Endpoint Configuration
`
`64
`64
`64
`
`EP2
`512
`512
`
`512
`512
`
`EP6
`
`1024
`
`1024
`
`6
`
`64
`64
`64
`
`EP2
`512
`512
`
`512
`512
`
`EP6
`512
`512
`
`512
`512
`5
`
`1
`
`EP0 IN&OUT
`EP1 IN
`EP1 OUT
`
`64
`64
`64
`
`EP2
`512
`512
`EP4
`512
`512
`
`EP6
`512
`512
`EP8
`512
`512
`
`1
`
`64
`64
`64
`
`EP2
`512
`512
`EP4
`512
`512
`
`EP6
`512
`512
`
`512
`512
`
`2
`
`64
`64
`64
`
`EP2
`512
`512
`EP4
`512
`512
`
`EP6
`
`1024
`
`1024
`
`3
`
`64
`64
`64
`
`EP2
`512
`512
`
`512
`512
`
`EP6
`512
`512
`EP8
`512
`512
`4
`
`3.12.5 Default Full Speed Alternate Settings
`
`Table 4. Default Full Speed Alternate Settings[3, 4]
`Alternate Setting
`0
`64
`0
`0
`0
`0
`0
`0
`
`ep0
`ep1out
`ep1in
`ep2
`ep4
`ep6
`ep8
`
`64
`64 bulk
`64 bulk
`64 bulk out (2×)
`64 bulk out (2×)
`64 bulk in (2×)
`64 bulk in (2×)
`
`64
`64
`64
`
`64
`64
`64
`
`64
`64
`64
`
`64
`64
`64
`
`64
`64
`64
`
`64
`64
`64
`
`EP2
`
`1024
`
`EP2
`
`1024
`
`EP2
`
`1024
`
`1024
`
`1024
`
`1024
`
`EP6
`512
`512
`EP8
`512
`512
`
`7
`
`EP6
`512
`512
`
`512
`512
`
`8
`
`EP6
`
`1024
`
`1024
`
`9
`
`1024
`
`1024
`
`EP2 EP2 EP2
`512
`512
`512
`EP6
`512
`
`1024
`
`1024
`
`512
`
`1024
`1024
`
`512
`EP8 EP8
`512
`512
`
`512
`
`10
`
`512
`
`11
`
`1024
`
`1024
`
`12
`
`2
`
`64
`64 int
`64 int
`64 int out (2×)
`64 bulk out (2×)
`64 int in (2×)
`64 bulk in (2×)
`
`3
`
`64
`64 int
`64 int
`64 iso out (2×)
`64 bulk out (2×)
`64 iso in (2×)
`64 bulk in (2×)
`
`Notes
`3.
`‘0’ means ‘not implemented.’
`4.
`‘2×’ means ‘double buffered.’
`
`Document # 001-06120 Rev *J
`
`Page 8 of 42
`
`[+] Feedback
`
`Exhibit 2036 - Page 08 of 42
`
`

`

`3.12.6 Default High Speed Alternate Settings
`
`Table 5. Default High Speed Alternate Settings[3, 4]
`Alternate Setting
`0
`64
`0
`0
`0
`0
`0
`0
`
`ep0
`ep1out
`ep1in
`ep2
`ep4
`ep6
`ep8
`
`1
`
`64
`512 bulk[5]
`512 bulk[5]
`512 bulk out (2×)
`512 bulk out (2×)
`512 bulk in (2×)
`512 bulk in (2×)
`
`3.13 External FIFO Interface
`The architecture, control signals, and clock rates are presented
`in this section.
`
`3.13.1 Architecture
`The FX2LP18 slave FIFO architecture has eight 512-byte blocks
`in the endpoint RAM that directly serve as FIFO memories and
`are controlled by FIFO control signals (such as IFCLK, SLCS#,
`SLRD, SLWR, SLOE, PKTEND, and flags).
`In operation, some of the eight RAM blocks fill or empty from the
`SIE while the others are connected to the I/O transfer logic. The
`transfer logic takes two forms: the GPIF for internally generated
`control signals or the slave FIFO interface for externally
`controlled transfers.
`
`3.13.2 Master/Slave Control Signals
`The FX2LP18 endpoint FIFOs are implemented as eight
`physically distinct 256x16 RAM blocks. The 8051/SIE can switch
`any of the RAM blocks between two domains, the USB (SIE)
`domain and the 8051-I/O Unit domain. This switching is
`instantaneous, giving zero transfer time between ‘USB FIFOs’
`and ‘Slave FIFOs’. Because they are physically the same
`memory, no bytes are actually transferred between buffers.
`At any given time, some RAM blocks are filling and emptying with
`USB data under SIE control, while other RAM blocks are
`available to the 8051, the I/O control unit, or both. The RAM
`blocks operate as single port in the USB domain, and dual port
`in the 8051-I/O domain. The blocks can be configured as single,
`double, triple, or quad buffered as previously shown.
`The I/O control unit implements either an internal master (M for
`master) or external master (S for Slave) interface.
`In Master (M) mode, the GPIF internally controls FIFOADR[1:0]
`to select a FIFO. The two ready (RDY) pins can be used as flag
`inputs from an external FIFO or other logic. The GPIF can be run
`from either an internally derived clock or externally supplied
`clock (IFCLK), at a rate that transfers data up to 96 megabytes/s
`(48 MHz IFCLK with 16-bit interface).
`
`CY7C68053
`
`2
`
`64
`64 int
`64 int
`512 int out (2×)
`512 bulk out (2×)
`512 int in (2×)
`512 bulk in (2×)
`
`3
`
`64
`64 int
`64 int
`512 iso out (2×)
`512 bulk out (2×)
`512 iso in (2×)
`512 bulk in (2×)
`
`In Slave (S) mode, the FX2LP18 accepts either an internally
`derived clock or externally supplied clock (IFCLK, maximum
`frequency 48 MHz) and SLCS#, SLRD, SLWR, SLOE, PKTEND
`signals from external logic. When using an external IFCLK, the
`external clock must be present before switching to the external
`clock with the IFCLKSRC bit. Each endpoint can individually be
`selected for byte or word operation by an internal configuration
`bit, and a Slave FIFO Output Enable signal (SLOE) enables data
`of the selected width. External logic must insure that the output
`enable signal is inactive when writing data to a slave FIFO. The
`slave interface can also operate asynchronously, where the
`SLRD and SLWR signals act directly as strobes, rather than a
`clock qualifier as in synchronous mode. The signals SLRD,
`SLWR, SLOE, and PKTEND are gated by the signal SLCS#.
`
`3.13.3 GPIF and FIFO Clock Rates
`An 8051 register bit selects one of two frequencies for the
`internally supplied interface clock: 30 MHz and 48 MHz.
`Alternatively, an externally supplied clock of 5 MHz–48 MHz
`feeding the IFCLK pin can be used as the interface clock. IFCLK
`can be configured to function as an output clock when the GPIF
`and FIFOs are internally clocked. An output enable bit in the
`IFCONFIG register turns this clock output off. Another bit within
`the IFCONFIG register inverts the IFCLK signal whether
`internally or externally sourced.
`3.14 GPIF
`The GPIF is a flexible 8- or 16-bit parallel interface driven by a
`user programmable finite state machine. It allows the
`CY7C68053 to perform local bus mastering, and can implement
`a wide variety of protocols such as ATA interface, parallel printer
`port, and Utopia.
`The GPIF has three programmable control outputs (CTL), and
`two general purpose ready inputs.The data bus width can be 8
`or 16 bits. Each GPIF vector defines the state of the control
`outputs, and determines what state a ready input (or multiple
`inputs) must be before proceeding. The GPIF vector can be
`programmed to advance a FIFO to the next data value, advance
`an address, and so on. A sequence of the GPIF vectors makes
`up a single waveform that is executed to perform the desired
`data move between the FX2LP18 and the external device.
`
`Note
`5. Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. Nnever transfer packets larger than 64 bytes to EP1.
`
`Document # 001-06120 Rev *J
`
`Page 9 of 42
`
`[+] Feedback
`
`Exhibit 2036 - Page 09 of 42
`
`

`

`CY7C68053
`
`3.16 USB Uploads and Downloads
`The core has the ability to directly edit the data contents of the
`internal 16-kByte RAM and of the internal 512-byte scratch pad
`RAM using a vendor-specific command. This capability is
`normally used when ‘soft’ downloading user code and is
`available only to and from internal RAM, only when the 8051 is
`held in reset. The available RAM spaces are 16 kBytes from
`0x0000–0x3FFF (code/data) and 512 bytes from
`0xE000–0xE1FF (scratch pad data RAM).[7]
`3.17 Autopointer Access
`FX2LP18 provides two identical autopointers. They are similar to
`the internal 8051 data pointers, but with an additional feature:
`they can optionally increment after every memory access. The
`autopointers are available in external FX2LP18 registers, under
`control of a mode bit (AUTOPTRSET-UP.0). Using the external
`FX2LP18 autopointer access (at 0xE67B – 0xE67C) allows the
`autopointer to access all RAM. Also, the autopointers can point
`to any FX2LP18 register or endpoint buffer space.
`3.18 I2C Controller
`FX2LP18 has one I2C port that is driven by two internal
`controllers. One controller automatically operates at boot time to
`load the VID/PID/DID, configuration byte, and firmware. The
`second controller is used by the 8051, once running, to control
`external I2C devices. The I2C port operates in master mode only.
`3.18.1 I2C Port Pins
`The I2C pins SCL and SDA must have external 2.2K ohm pull up
`resistors even if no EEPROM is connected to the FX2LP18. The
`value of the pull up resistors required may vary, depending on
`the combination of VCC_IO and the supply used for the EEPROM.
`The pull up resistors used must be such that when the EEPROM
`pulls SDA low, the voltage level meets the VIL specification of the
`FX2LP18. For example, if the EEPROM runs off a 3.3 V supply
`and VCC_IO is 1.8 V, the pull up resistors recommended are 10K
`ohm. This requirement may also vary depending on the devices
`being run on the I2C pins. Refer to the I2C specifications for
`details.
`External EEPROM device address pins must be configured
`properly. See Table 6 on page 11 for configuring the device
`address pins.
`If no EEPROM is connected to the I2C port, EEPROM emulation
`is required by an external processor. This is because the
`FX2LP18 comes out of reset with the DISCON bit set, so the
`device will not enumerate without an EEPROM (C2 load) or
`EEPROM emulation.
`
`3.14.1 Three Control OUT Signals
`The 56-pin package brings out three of these signals,
`CTL0–CTL2. The 8051 programs the GPIF unit to define the CTL
`waveforms. CTLx waveform edges can be programmed to make
`transitions as fast as once per clock cycle (20.8 ns using a
`48 MHz clock).
`
`3.14.2 Two Ready IN Signals
`The FX2LP18 package brings out all two Ready inputs
`(RDY0–RDY1). The 8051 programs the GPIF unit to test the
`RDY pins for GPIF branching.
`
`3.14.3 Long Transfer Mode
`In master mode, the 8051 appropriately sets GPIF transaction
`count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1, or
`GPIFTCB0) for unattended transfers of up to 232 transactions.
`The GPIF automatically throttles data flow to prevent under or
`overflow until the full number of requested transactions
`complete. The GPIF decrements the value in these registers to
`represent the current status of the transaction.
`3.15 ECC Generation[6]
`The MoBL-USB can calculate Error Correcting Codes (ECCs) on
`data that passes across its GPIF or Slave FIFO interfaces. There
`are two ECC configurations: two ECCs, each calculated over
`256 bytes (SmartMedia Standard) and one ECC calculated over
`512 bytes.
`The ECC can correct any 1-bit error or detect any 2-bit error.
`
`3.15.1 ECC Implementation
`The two ECC configurations are selected by the ECCM bit.
`
`3.15.1.1 ECCM = 0
`Two 3-byte ECCs are