15.
`
` Registers
`
`Introduction
`15.1
`This section describes the MoBL-USB FX2LP18 registers in the order they appear in the memory map, see Figure 5-3 on
`page 81. The registers are named according to the following conventions.
`Most registers deal with endpoints. The general register format is DDDnFFF, where:
`❐ DDD is endpoint direction, IN or OUT with respect to the USB host.
`n is the endpoint number, where:
`❐ ’ISO’ indicates isochronous endpoints as a group.
`FFF is the function, where:
`❐ CS is a control and status register
`❐ IRQ is an Interrupt Request bit
`❐ IE is an Interrupt Enable bit
`❐ BC, BCL, and BCH are byte count registers. BC is used for single byte counts, and BCH/BCL are used as the high and
`low bytes of 16-bit byte counts.
`❐ DATA is a single-register access to a FIFO.
`❐ BUF is the start address of a buffer.
`
`Example Register Format
`15.1.1
`❐ EP1INBC is the Endpoint 1 IN byte count.
`
`Other Conventions
`15.1.2
`USB–Indicates a global (not endpoint-specific) USB function.
`ADDR–Is an address.
`VAL–Means valid.
`FRAME–Is a frame count.
`PTR–Is an address pointer.
`
`MoBL-USB™ TRM, Document # 001-11981 Rev. *B
`
`237
`
`Exhibit 2033 - Page 237 of 346
`
`

`
`Registers
`
`Register Name
`b7
`bitname
`R, W access
`Default val
`
`b6
`bitname
`R, W access
`Default val
`
`b5
`bitname
`R, W access
`Default val
`
`Register Function
`b4
`b3
`bitname
`bitname
`R, W access
`R, W access
`Default val
`Default val
`
`b2
`bitname
`R, W access
`Default val
`
`b1
`bitname
`R, W access
`Default val
`
`Address
`b0
`bitname
`R, W access
`Default val
`
`The register table above illustrates the register description format used in this chapter.
`■ The top line shows the register name, functional description, and address in the memory.
`■ The second line shows the bit position in the register.
`■ The third line shows the name of each bit in the register.
`■ The fourth line shows CPU accessibility: R(ead), W(rite), or R/W.
`■ The fifth line shows the default value. These values apply after a hard reset.
`
`Special Function Registers (SFR)
`15.2
`MoBL-USB FX2LP18 implements many control registers as SFRs (Special Function Registers). These SFRs are shown in
`Table 15-1. bold type indicates SFRs which are not in the standard 8051, but are included in the MoBL-USB FX2LP18.
`
`Table 15-1. MoBL-USB FX2LP18 Special Function Registers (SFR)
`x
`8x
`9x
`Ax
`IOA
`IOB
`IOC
`0
`EXIF
`INT2CLR
`1
`SP
`MPAGE
`INT4CLR
`2
`DPL0
`3
`DPH0
`DPL1
`4
`DPH1
`5
`DPS
`6
`7
`PCON
`8
`TCON
`9
`TMOD
`A
`TL0
`B
`TL1
`C
`TH0
`D
`TH1
`CKCON
`E
`F
`
`IE
`
`EP2468STAT
`EP24FIFOFLGS
`EP68FIFOFLGS
`
`SCON0
`SBUF0
`AUTOPTRH1
`AUTOPTRL1
`
`AUTOPTRH2
`AUTOPTRL2
`
`Bx
`IOD
`IOE
`OEA
`OEB
`OEC
`OED
`OEE
`
`IP
`
`EP01STAT
`GPIFTRIG
`
`Cx
`SCON1
`SBUF1
`
`Dx
`PSW
`
`Ex
`ACC
`
`Fx
`B
`
`T2CON
`
`EICON
`
`EIE
`
`EIP
`
`RCAP2L
`RCAP2H
`TL2
`TH2
`
`AUTOPTR-SETUP
`
`GPIFSGLDATH
`GPIFSGLDATLX
`GPIFSGLDATLNOX
`
`All un-labeled SFRs are reserved.
`
`238
`
`MoBL-USB™ TRM, Document # 001-11981 Rev. *B
`
`Exhibit 2033 - Page 238 of 346
`
`

`
`Registers
`
`15.3 About SFRs
`Because the SFRs are directly addressable internal registers, firmware can access them quickly, without the overhead of
`loading the data pointer and performing a MOVX instruction. For example, the firmware reads the Port B pins using a single
`instruction, as shown below.
`Single instruction to read port B:
`mov
`a,IOB
`In the same manner, firmware writes the value 0x55 to Port C using only one MOV instruction, as shown below.
`Single instruction to read port C:
`mov
`IOC,#55h
`SFRs in Table 15-1 on page 238 rows 0 and 8 are bit-addressable; individual bits of the registers may be efficiently set,
`cleared, or toggled using special bit-addressing instructions (for example, setb IOB.2 sets bit 2 of the IOB register).
`
`IOA
`
`IOB
`
`b7
`D7
`R/W
`x
`
`b7
`D7
`R/W
`x
`
`AUTOPTRH1
`b7
`A15
`R/W
`0
`
`AUTOPTRL1
`b7
`A7
`R/W
`0
`
`AUTOPTRH2
`b7
`A15
`R/W
`0
`
`b6
`D6
`R/W
`x
`
`b6
`D6
`R/W
`x
`
`b6
`A14
`R/W
`0
`
`b6
`A6
`R/W
`0
`
`b6
`A14
`R/W
`0
`
`b5
`D5
`R/W
`x
`
`b5
`D5
`R/W
`x
`
`b5
`A13
`R/W
`0
`
`b5
`A5
`R/W
`0
`
`b5
`A13
`R/W
`0
`
`Port A (bit addressable)
`b4
`b3
`D4
`D3
`R/W
`R/W
`x
`x
`
`Port B (bit addressable)
`
`b4
`D4
`R/W
`x
`
`b3
`D3
`R/W
`x
`
`Autopointer 1 Address HIGH
`b4
`b3
`A12
`A11
`R/W
`R/W
`0
`0
`
`Autopointer 1 Address LOW
`b4
`b3
`A4
`A3
`R/W
`R/W
`0
`0
`
`Autopointer 2 Address HIGH
`b4
`b3
`A12
`A11
`R/W
`R/W
`0
`0
`
`b2
`D2
`R/W
`x
`
`b2
`D2
`R/W
`x
`
`b2
`A10
`R/W
`0
`
`b2
`A2
`R/W
`0
`
`b2
`A10
`R/W
`0
`
`b1
`D1
`R/W
`x
`
`b1
`D1
`R/W
`x
`
`b1
`A9
`R/W
`0
`
`b1
`A1
`R/W
`0
`
`b1
`A9
`R/W
`0
`
` SFR 0x80
`b0
`D0
`R/W
`x
`
`SFR 0x90
`
`b0
`D0
`R/W
`x
`
`SFR 0x9A
`b0
`A8
`R/W
`0
`
`SFR 0x9B
`b0
`A0
`R/W
`0
`
`SFR 0x9D
`b0
`A8
`R/W
`0
`
`MoBL-USB™ TRM, Document # 001-11981 Rev. *B
`
`239
`
`Exhibit 2033 - Page 239 of 346
`
`

`
`Registers
`
`AUTOPTRL2
`b7
`A7
`R/W
`0
`
`IOC
`
`b7
`D7
`R/W
`x
`
`INT2CLR
`b7
`x
`W
`x
`
`INT4CLR
`b7
`x
`W
`x
`
`b6
`A6
`R/W
`0
`
`b6
`D6
`R/W
`x
`
`b6
`x
`W
`x
`
`b6
`x
`W
`x
`
`b5
`A5
`R/W
`0
`
`b5
`D5
`R/W
`x
`
`b5
`x
`W
`x
`
`b5
`x
`W
`x
`
`Autopointer 2 Address LOW
`b4
`b3
`A4
`A3
`R/W
`R/W
`0
`0
`
`Port C (bit addressable)
`b4
`b3
`D4
`D3
`R/W
`R/W
`x
`x
`
`Interrupt 2 Clear
`b3
`x
`W
`x
`
`b4
`x
`W
`x
`
`Interrupt 4 Clear
`b3
`x
`W
`x
`
`b4
`x
`W
`x
`
`b2
`A2
`R/W
`0
`
`b2
`D2
`R/W
`x
`
`b2
`x
`W
`x
`
`b2
`x
`W
`x
`
`b1
`A1
`R/W
`0
`
`b1
`D1
`R/W
`x
`
`b1
`x
`W
`x
`
`b1
`x
`W
`x
`
`SFR 0x9E
`b0
`A0
`R/W
`0
`
`SFR 0xA0
`b0
`D0
`R/W
`x
`
`SFR 0xA1
`b0
`x
`W
`x
`
`SFR 0xA2
`b0
`x
`W
`x
`
`Writing any value to INT2CLR or INT4CLR clears the INT2 or INT4 interrupt request bit for the INT2/INT4 interrupt currently
`being serviced.
`
`Writing to one of these registers has the same effect as clearing the appropriate interrupt request bit in the MoBL-USB
`FX2LP18 external register space. For example, suppose the EP2 Empty Flag interrupt is asserted. The MoBL-USB
`FX2LP18 automatically sets bit 1 of the EP2FIFOIRQ register (in External Data memory space, at 0xE651), and asserts
`the INT4 interrupt request.
`Using autovectoring, the MoBL-USB FX2LP18 automatically calls (vectors to) the EP2_FIFO_EMPTY 2 Interrupt Service
`Routine (ISR). The first task in the ISR is to clear the interrupt request bit, EP2FIFOIRQ.1. The firmware can do this either
`by accessing the EP2FIFOIRQ register (at 0xE651) and writing a ‘1’ to bit 1, or simply by writing any value to INT4CLR.
`The first method requires the use of the data pointer, which must be saved and restored along with the accumulator in an
`ISR. The second method is much faster and does not require saving the data pointer, so it is preferred.
`
`240
`
`MoBL-USB™ TRM, Document # 001-11981 Rev. *B
`
`Exhibit 2033 - Page 240 of 346
`
`

`
`EP2468STAT
`b7
`EP8F
`R
`0
`
`b6
`EP8E
`R
`1
`
`b5
`EP6F
`R
`0
`
`Endpoint(s) 2,4,6,8 Status Flags
`b4
`b3
`EP6E
`EP4F
`R
`R
`1
`1
`
`b2
`EP4E
`R
`0
`
`b1
`EP2F
`R
`1
`
`The bits in EP2468STAT correspond to Endpoint Status bits in the MoBL-USB FX2LP18 register file, as follows:
`
`Registers
`
`SFR 0xAA
`b0
`EP2E
`R
`0
`
`Bit
`
`EPSTAT SFR
`
`Table 15-2. SFR and MoBL-USB FX2LP18 Register File Correspondences
`MoBL-USB FX2LP18
`MoBL-USB FX2LP18 Register File
`Register.Bit
`Address
`E6A6
`E6A6
`E6A5
`E6A5
`E6A4
`E6A4
`E6A3
`E6A3
`
`7
`6
`5
`4
`3
`2
`1
`0
`
`EP8 Full flag
`EP8 Empty flag
`EP6 Full flag
`EP6 Empty flag
`EP4 Full flag
`EP4 Empty flag
`EP2 Full flag
`EP2 Empty flag
`
`EP8CS.3
`EP8CS.2
`EP6CS.3
`EP6CS.2
`EP4CS.3
`EP4CS.2
`EP2CS.3
`EP2CS.2
`
`Note The Endpoint status bits represent the Packet Status.
`
`EP24FIFOFLGS
`b7
`0
`R
`0
`
`EP68FIFOFLGS
`b7
`0
`R
`0
`
`AUTOPTRSETUP
`b7
`0
`R/W
`0
`
`b6
`EP4PF
`R
`0
`
`b6
`EP8PF
`R
`1
`
`b6
`0
`R/W
`0
`
`Endpoint(s) 2, 4 Slave FIFO Status Flags
`b4
`b3
`EP4FF
`0
`R
`R
`0
`0
`
`Endpoint(s) 6, 8 Slave FIFO Status Flags
`b4
`b3
`EP8FF
`0
`R
`R
`0
`0
`
`b2
`EP2PF
`R
`0
`
`b2
`EP6PF
`R
`1
`
`b1
`EP2EF
`R
`1
`
`b1
`EP6EF
`R
`1
`
`Autopointer(s) 1 and 2 Setup
`b4
`b3
`0
`0
`R/W
`R/W
`0
`0
`
`b2
`APTR2INC
`R/W
`1
`
`b1
`APTR1INC
`R/W
`1
`
`b5
`EP4EF
`R
`1
`
`b5
`EP8EF
`R
`1
`
`b5
`0
`R/W
`0
`
`SFR 0xAB
`b0
`EP2FF
`R
`0
`
`SFR 0xAC
`b0
`EP6FF
`R
`0
`
`SFR 0xAF
`b0
`APTREN
`R/W
`0
`
`MoBL-USB FX2LP18 provides two identical autopointers. They are similar to the internal ‘DPTR’ data pointers, but with an
`additional feature: each can automatically increment after every memory access. Using one or both of the autopointers, firm-
`ware can perform very fast block memory transfers.
`The AUTOPTRSETUP register is configured as follows:
`■ Set APTRnINC=0 to freeze the address pointer, APTRnINC=1 to automatically increment it for every read or write of an
`XAUTODATn register. This bit defaults to 1, enabling the auto-increment feature.
`■ Set APTREN=1 to enable the autopointer for on-chip memory access.
`The firmware then writes a 16-bit address to AUTOPTRHn/Ln. Then, for every read or write of an XAUTODATn register, the
`address pointer automatically increments (if APTRnINC=1).
`
`MoBL-USB™ TRM, Document # 001-11981 Rev. *B
`
`241
`
`Exhibit 2033 - Page 241 of 346
`
`

`
`Registers
`
`IOD
`
`b7
`D7
`R/W
`x
`
`b6
`D6
`R/W
`x
`
`b5
`D5
`R/W
`x
`
`Port D (bit addressable)
`b4
`b3
`D4
`D3
`R/W
`R/W
`x
`x
`
`b2
`D2
`R/W
`x
`
`b1
`D1
`R/W
`x
`
`SFR 0xB0
`b0
`D0
`R/W
`x
`
`MoBL-USB FX2LP18 IO ports PORTA-PORTD appear as bit-addressable SFRS. Reading a register or bit returns the logic
`level of the port pin that’s two CLKOUT-clocks old. Writing a register bit writes the port latch. Whether or not the port latch
`value appears on the IO pin depends on the state of the pin’s OE (Output Enable) bit. The IO pins may also be assigned alter-
`nate function values, in which case the IOx and OEx bit values are overridden on a bit-by-bit basis.
`IOD is bit-addressable. Use Bit 2 to set PORTD - single instruction:
`setb
`IOD.2
`; set bit 2 of IOD SFR
`
`IOE
`
`b7
`D7
`R/W
`x
`
`b6
`D6
`R/W
`x
`
`b5
`D5
`R/W
`x
`
`Port E
`
`b3
`D3
`R/W
`x
`
`b4
`D4
`R/W
`x
`
`b2
`D2
`R/W
`x
`
`b1
`D1
`R/W
`x
`
`SFR 0xB1
`b0
`D0
`R/W
`x
`
`IO port PORTE is also accessed using an SFR, but unlike the PORTA-PORTD SFRs, it is not bit-addressable.
`Use OR to set bit 3:
`mov
`a,IOE
`or
`a,#00001000b
`mov
`IOE,a
`
`; set bit 3
`
`242
`
`MoBL-USB™ TRM, Document # 001-11981 Rev. *B
`
`Exhibit 2033 - Page 242 of 346
`
`

`
`OEA
`
`OEB
`
`OEC
`
`OED
`
`OEE
`
`b7
`D7
`R/W
`0
`
`b7
`D7
`R/W
`0
`
`b7
`D7
`R/W
`0
`
`b7
`D7
`R/W
`0
`
`b7
`D7
`R/W
`0
`
`b6
`D6
`R/W
`0
`
`b6
`D6
`R/W
`0
`
`b6
`D6
`R/W
`0
`
`b6
`D6
`R/W
`0
`
`b6
`D6
`R/W
`0
`
`b5
`D5
`R/W
`0
`
`b5
`D5
`R/W
`0
`
`b5
`D5
`R/W
`0
`
`b5
`D5
`R/W
`0
`
`b5
`D5
`R/W
`0
`
`Port A Output Enable
`b4
`b3
`D4
`D3
`R/W
`R/W
`0
`0
`
`Port B Output Enable
`b4
`b3
`D4
`D3
`R/W
`R/W
`0
`0
`
`Port C Output Enable
`b4
`b3
`D4
`D3
`R/W
`R/W
`0
`0
`
`Port D Output Enable
`b4
`b3
`D4
`D3
`R/W
`R/W
`0
`0
`
`Port E Output Enable
`b4
`b3
`D4
`D3
`R/W
`R/W
`0
`0
`
`b2
`D2
`R/W
`0
`
`b2
`D2
`R/W
`0
`
`b2
`D2
`R/W
`0
`
`b2
`D2
`R/W
`0
`
`b2
`D2
`R/W
`0
`
`b1
`D1
`R/W
`0
`
`b1
`D1
`R/W
`0
`
`b1
`D1
`R/W
`0
`
`b1
`D1
`R/W
`0
`
`b1
`D1
`R/W
`0
`
`Registers
`
`SFR 0xB2
`b0
`D0
`R/W
`0
`
`SFR 0xB3
`b0
`D0
`R/W
`0
`
`SFR 0xB4
`b0
`D0
`R/W
`0
`
`SFR 0xB5
`b0
`D0
`R/W
`0
`
`SFR 0xB6
`b0
`D0
`R/W
`0
`
`The bits in 0EA - 0EE turn on the output buffers for the five IO Ports PORTA-PORTE. Set a bit to ‘1’ to turn on the output
`buffer, set it to ‘0’ to turn the buffer off.
`
`EP01STAT
`b7
`0
`R
`0
`
`b6
`0
`R
`0
`
`b5
`0
`R
`0
`
`Endpoint 0 and 1 Status
`b4
`b3
`0
`0
`R
`R
`0
`0
`
`b2
`EP1INBSY
`R
`0
`
`b1
`EP1OUTBSY
`R
`0
`
`SFR 0xBA
`b0
`EP0BSY
`R
`0
`
`MoBL-USB™ TRM, Document # 001-11981 Rev. *B
`
`243
`
`Exhibit 2033 - Page 243 of 346
`
`

`
`Registers
`
`GPIFTRIG
`see Section 15.15
`b7
`DONE
`R/W
`1
`
`GPIFSGLDATH
`b7
`D15
`R/W
`x
`
`GPIFSGLDATLX
`b7
`D7
`R/W
`x
`
`GPIFSGLDATLNOX
`b7
`D7
`R
`x
`
`b6
`0
`R
`0
`
`b6
`D14
`R/W
`x
`
`b6
`D6
`R/W
`x
`
`b6
`D6
`R
`x
`
`Endpoint 2,4,6,8 GPIF Slave
`FIFO Trigger
`
`b4
`0
`R
`0
`
`b3
`0
`R
`0
`
`GPIF Data HIGH (16-bit mode only)
`b4
`b3
`D12
`D11
`R/W
`R/W
`x
`x
`
`GPIF Data LOW w/Trigger
`b4
`b3
`D4
`D3
`R/W
`R/W
`x
`x
`
`GPIF Data LOW w/No Trigger
`b4
`b3
`D4
`D3
`R
`R
`x
`x
`
`b5
`0
`R
`0
`
`b5
`D13
`R/W
`x
`
`b5
`D5
`R/W
`x
`
`b5
`D5
`R
`x
`
`b2
`R/W
`R/W
`x
`
`b2
`D10
`R/W
`x
`
`b2
`D2
`R/W
`x
`
`b2
`D2
`R
`x
`
`SFR 0xBB
`
`b0
`EP0
`R/W
`x
`
`SFR 0xBD
`b0
`D8
`R/W
`x
`
`SFR 0xBE
`b0
`D0
`R/W
`x
`
`SFR 0xBF
`b0
`D0
`R
`x
`
`b1
`EP1
`R/W
`x
`
`b1
`D9
`R/W
`x
`
`b1
`D1
`R/W
`x
`
`b1
`D1
`R
`x
`
`Most of these SFR registers are also accessible in external RAM space, at the addresses shown in Table 15-3.
`
`Table 15-3. SFR Registers and External RAM Equivalent
`SFR Register Name
`Hex
`External Ram Register Address and Name
`EP2468STAT
`AA
`EPxCS
`EP24FIFOFLGS
`AB
`EP68FIFOFLGS
`AC
`EP01STAT
`BA
`GPIFTRIG
`BB
`GPIFSGLDATH
`BD
`GPIFSGLDATLX
`BE
`GPIFSGLDATLNOX
`BF
`
`EPxFIFOFLGS
`
`EP0CS, EP1OUTCS, EP1INCS
`EPxGPIFTRIG
`XGPIFSGLDATH
`XGPIFSGLDATLX
`XGPIFSGLDATLNOX
`
`E6A3-E6A6
`
`E6A7-E6AA
`
`E6A0-E6A2
`E6D4, E6DC, E6E4, E6EC
`E6F0
`E6F1
`E6F2
`
`244
`
`MoBL-USB™ TRM, Document # 001-11981 Rev. *B
`
`Exhibit 2033 - Page 244 of 346
`
`

`
`Registers
`
`15.4 GPIF Waveform Memories
`15.4.1
`GPIF Waveform Descriptor Data
`
`WAVEDATA
`b7
`D7
`R/W
` x
`
`b6
`D6
`R/W
` x
`
`GPIF Waveform Descriptor 0, 1, 2, 3 Data
`b4
`b3
`D4
`D3
`R/W
`R/W
`x
` x
`
`b2
`D2
`R/W
`x
`
`b5
`D5
`R/W
` x
`
`b1
`D1
`R/W
`x
`
`E400-E47F*
`b0
`D0
`R/W
`x
`
`*Accessible only when IFCFG1:0 = 10.
`The four GPIF waveform descriptor tables are stored in this space. See the General Programmable Interface chapter on
`page 135 for details.
`
`15.5 General Configuration Registers
`15.5.1
`CPU Control and Status
`
`CPUCS
`
`b7
`0
`R
`0
`
`b6
`0
`R
`0
`
`b5
`PORTCSTB
`R/W
`0
`
`CPU Control and Status
`b4
`b3
`CLKSPD1
`CLKSPD0
`R/W
`R/W
`0
`0
`
`b2
`CLKINV
`R/W
`0
`
`b1
`CLKOE
`R/W
`1
`
`E600
`
`b0
`8051RES
`R
`0
`
`Bit 5
`
`PORTCSTB
`
`PORTC access generates RD and WR strobes
`The 100-pin MoBL-USB FX2LP18 packages have two output pins, RD and WR, that can be used to
`synchronize data transfers on IO PORTC. When PORTCSTB=1, this feature is enabled. Any read of
`PORTC activates a RD strobe, and any write to PORTC activates a WR strobe. The RD and WR
`strobes are asserted for two CLKOUT cycles; the WR strobe asserts two CLKOUT cycles after the
`PORTC pins are updated.
`
`Bit 4-3
`
`CLKSPD1:0
`
`CPU Clock Speed
`
`CLKSPD1
`0
`0
`1
`1
`
`CLKSPD0
`0
`1
`0
`1
`
`CPU Clock
`12 MHz (Default)
`24 MHz
`48 MHz
`Reserved
`
`These bits set the CPU clock speed. On a hard reset, these bits default to 00 (12 MHz). Firmware may modify these bits at any time.
`
`Bit 2
`
`CLKINV
`
`Bit 1
`
`CLKOE
`
`Bit 0
`
`8051RES
`
`Invert CLKOUT Signal
`CLKINV=0: CLKOUT signal not inverted (as shown in all timing diagrams).
`CLKINV=1: CLKOUT signal inverted.
`
`Drive CLKOUT Pin
`CLKOE=1: CLKOUT pin driven.
`CLKOE=0: CLKOUT pin floats.
`
`8051 Reset
`The USB host writes ‘1’ to this bit to reset the 8051, and ‘0’ to run the 8051. Only the USB host writes
`to this bit (via the 0xA0 firmware load command).
`
`MoBL-USB™ TRM, Document # 001-11981 Rev. *B
`
`245
`
`Exhibit 2033 - Page 245 of 346
`
`

`
`Registers
`
`15.5.2
`
`Interface Configuration (Ports, GPIF, slave FIFOs)
`
`IFCONFIG
`b7
`IFCLKSRC
`R/W
`1
`
`b6
`3048MHZ
`R/W
`0
`
`Bit 7
`
`IFCLKSRC
`
`Interface Configuration (Ports, GPIF, slave FIFOs)
`b4
`b3
`IFCLKPOL
`ASYNC
`R/W
`R/W
`0
`0
`
`b5
`IFCLKOE
`R/W
`0
`
`b2
`GSTATE
`R/W
`0
`
`b1
`IFCFG1
`R/W
`0
`
`E601
`
`b0
`IFCFG0
`R/W
`0
`
`FIFO/GPIF Clock Source
`This bit selects the clock source for both the FIFOs and GPIF. If IFCLKSRC=0, the external clock on
`the IFCLK pin is selected. If IFCLKSRC=1 (default), an internal 30- or 48-MHz (default) clock is used.
`
`Bit 6
`
`3048MHZ
`
`Internal FIFO/GPIF Clock Frequency
`This bit selects the internal FIFO and GPIF clock frequency.
`
`3048MHZ
`0
`1
`
`FIFO and GPIF Clock
`30 MHz (default)
`48 MHz
`
`IFCLK pin output enable
`0=Tri-state
`1=Drive
`
`Invert the IFCLK signal
`This bit indicates that the IFCLK signal is inverted.
`When IFCLKPOL=0, the clock has the polarity shown in all the timing diagrams in this manual.
`When IFCLKPOL=1, the clock is inverted.
`
`Figure 15-1. IFCLK Configuration
`
`IFCFG.4
`
`IFCFG.5
`
`01
`
`IFCFG.6
`
`01
`
`30 MHz
`48 MHz
`
`IFCLK
`Pin
`
`IFCFG.4
`
`01
`
`IFCFG.7
`
`10
`
`Internal
`IFCLK
`Signal
`
`Bit 5
`
`IFCLKOE
`
`Bit 4
`
`IFCLKPOL
`
`Bit 3
`
`ASYNC
`
`Slave FIFO Asynchronous Mode
`When ASYNC=0, the Slave FIFOs operate synchronously: a clock is supplied either internally or
`externally on the IFCLK pin; the FIFO control signals function as read and write enable signals for the
`clock signal.
`When ASYNC=1, the Slave FIFOs operate asynchronously: no clock signal input to IFCLK is
`required; the FIFO control signals function directly as read and write strobes.
`
`246
`
`MoBL-USB™ TRM, Document # 001-11981 Rev. *B
`
`Exhibit 2033 - Page 246 of 346
`
`

`
`Registers
`
`Bit 2
`
`GSTATE
`
`Drive GSTATE [2:0] on PORTE [2:0]
`When GSTATE=1, three bits in Port E take on the signals shown below. The GSTATE bits,
`which indicate GPIF states, are used for diagnostic purposes.
`
`IO Pin
`PE0
`PE1
`PE2
`
`Alternate Function
`GSTATE[0]
`GSTATE[1]
`GSTATE[2]
`
`Bit 1-0
`
`IFCFG1:0
`
`Select Interface Mode (Ports, GPIF, or Slave FIFO)
`
`IFCFG1
`0
`0
`1
`
`1
`
`IFCFG0
`0
`1
`0
`
`1
`
`Configuration
`
`Ports
`Reserved
`GPIF Interface (internal master)
`Slave FIFO Interface (external
`master)
`
`These bits control the following MoBL-USB FX2LP18 interface signals, as shown below.
`
`IFCFG1:0 = 00
`(Ports)
`
`IFCFG1:0 = 10
`(GPIF Master)
`
`IFCFG1:0 = 11
`(Slave FIFO)
`
`PD7
`PD6
`PD5
`PD4
`PD3
`PD2
`PD1
`PD0
`PB7
`PB6
`PB5
`PB4
`PB3
`PB2
`PB1
`PB0
`INT0/PA0
`INT1/PA1
`PA2
`WU2/PA3
`PA4
`PA5
`PA6
`PA7
`
`FD[15]
`FD[14]
`FD[13]
`FD[12]
`FD[11]
`FD[10]
`FD[9]
`FD[8]
`FD[7]
`FD[6]
`FD[5]
`FD[4]
`FD[3]
`FD[2]
`FD[1]
`FD[0]
`INT0/PA0
`INT1/PA1
`PA2
`WU2/PA3
`PA4
`PA5
`PA6
`PA7
`
`FD[15]
`FD[14]
`FD[13]
`FD[12]
`FD[11]
`FD[10]
`FD[9]
`FD[8]
`FD[7]
`FD[6]
`FD[5]
`FD[4]
`FD[3]
`FD[2]
`FD[1]
`FD[0]
`INT0/PA0
`INT1/PA1
`SLOE
`WU2/PA3
`FIFOADR0
`FIFOADR1
`PKTEND
`PA7/FLAGD/SLCS
`
`PC7:0
`PC7:0
`PC7:0
`PE7:0
`PE7:0
`PE7:0
`Note Signals shown in bold type do not change with IFCFG; they are shown for completeness.
`
`MoBL-USB™ TRM, Document # 001-11981 Rev. *B
`
`247
`
`Exhibit 2033 - Page 247 of 346
`
`

`
`Registers
`
`15.5.3
`
`Slave FIFO FLAGA-FLAGD Pin Configuration
`
`PINFLAGSAB
`see Section 15.15
`b7
`FLAGB3
`R/W
`0
`
`PINFLAGSCD
`see Section 15.15
`b7
`FLAGD3
`R/W
`0
`
`b6
`FLAGB2
`R/W
`0
`
`b6
`FLAGD2
`R/W
`0
`
`Slave FIFO FLAGA and FLAGB Pin Configuration
`
`E602
`
`b5
`FLAGB1
`R/W
`0
`
`b4
`FLAGB0
`R/W
`0
`
`b3
`FLAGA3
`R/W
`0
`
`b2
`FLAGA2
`R/W
`0
`
`Slave FIFO FLAGC and FLAGD Pin Configuration
`
`b5
`FLAGD1
`R/W
`0
`
`b4
`FLAGD0
`R/W
`0
`
`b3
`FLAGC3
`R/W
`0
`
`b2
`FLAGC2
`R/W
`0
`
`b1
`FLAGA1
`R/W
`0
`
`b1
`FLAGC1
`R/W
`0
`
`b0
`FLAGA0
`R/W
`0
`
`E603
`
`b0
`FLAGC0
`R/W
`0
`
`The MoBL-USB FX2LP18 has four FIFO flag output pins, FLAGA, FLAGB, FLAGC and FLAGD. These flags can be pro-
`grammed to represent various FIFO flags using four select bits for each FIFO. The PINFLAGSAB register controls the FLAGA
`and FLAGB signals, and the PINFLAGSCD register controls the FLAGC and FLAGD signal. The 4-bit coding for all four flags
`is the same, as shown in Table 15-4. In the ‘FLAGx’ notation, ‘x’ can be A, B, C or D.
`
`Table 15-4. FIFO Flag Pin Functions
`FLAGx3
`FLAGx2
`FLAGx1
`
`FLAGx0
`
`Pin Function
`
`0
`0
`0
`0
`0
`0
`1
`0
`0
`1
`0
`0
`0
`1
`0
`0
`1
`0
`1
`1
`0
`1
`1
`0
`0
`0
`1
`0
`0
`1
`1
`0
`1
`1
`0
`1
`0
`1
`1
`0
`1
`1
`1
`1
`1
`1
`1
`1
`Note FLAGD defaults to EP2PF (fixed flag).
`
`0
`1
`0
`1
`0
`1
`0
`1
`0
`1
`0
`1
`0
`1
`0
`1
`
`FLAGA=PF, FLAGB=FF, FLAGC=EF, FLAGD=EP2PF
`(Actual FIFO is selected by FIFOADR[0,1] pins)
`
`Reserved
`
`EP2 PF
`EP4 PF
`EP6 PF
`EP8 PF
`EP2 EF
`EP4 EF
`EP6 EF
`EP8 EF
`EP2 FF
`EP4 FF
`EP6 FF
`EP8 FF
`
`248
`
`MoBL-USB™ TRM, Document # 001-11981 Rev. *B
`
`Exhibit 2033 - Page 248 of 346
`
`

`
`For the default (0000) selection, the four FIFO flags are indexed as shown in the first table entry. The input pins FIFOADR1
`and FIFOADR0 select to which of the four FIFOs the flags correspond. These pins are decoded as follows:
`
`Registers
`
`FIFOADR1 pin
`0
`0
`1
`1
`
`FIFOADR0 pin
`0
`1
`0
`1
`
`Selected FIFO
`EP2
`EP4
`EP6
`EP8
`
`For example, if FLAGA[3:0]=0000 and the FIFO address pins are driven to [01], then FLAGA is the EP4-Programmable Flag,
`FLAGB is the EP4-Full Flag, and FLAGC is the EP4-Empty Flag, and FLAGD defaults as PA7. Set PORTACFG.7 = 1 to use
`FLAGD which by default is EP2PF(fixed flag).
`The other (non-zero) values of FLAGx[3:0] allow the designer to independently configure the four flag outputs FLAGA-FLAGD
`to correspond to any flag—Programmable, Full, or Empty—from any of the four endpoint FIFOS. This allows each flag to be
`assigned to any of the four FIFOS, including those not currently selected by the FIFOADDR pins. For example, external logic
`could be filling the EP2IN FIFO with data while also checking the full flag for the EP4OUT FIFO.
`
`15.5.4
`
`FIFO Reset
`
`FIFORESET
`see Section 15.15
`b7
`NAKALL
`W
`x
`
`b6
`0
`W
`x
`
`Restore FIFOs to Default State
`
`b5
`0
`W
`x
`
`b4
`0
`W
`x
`
`b3
`EP3
`W
`x
`
`b2
`EP2
`W
`x
`
`b1
`EP1
`W
`x
`
`E604
`
`b0
`EP0
`W
`x
`
`Write 0x80 to this register to NAK all transfers from the host, then write 0x02, 0x04, 0x06, or 0x08 to reset an individual FIFO
`(for example, to restore endpoint FIFO flags and byte counts to their default states), then write 0x00 to restore normal opera-
`tion.
`
`Bit 3-0
`
`EP3:0
`
`Endpoint
`By writing the desired endpoint number (2,4,6,8), MoBL-USB FX2LP18 logic resets the individual
`endpoint.
`
`MoBL-USB™ TRM, Document # 001-11981 Rev. *B
`
`249
`
`Exhibit 2033 - Page 249 of 346
`
`

`
`Registers
`
`15.5.5
`
`Breakpoint, Breakpoint Address High, Breakpoint Address Low
`
`b6
`0
`R
`0
`
`b5
`0
`R
`0
`
`Breakpoint Control
`b4
`b3
`0
`BREAK
`R
`R/W
`0
`0
`
`b2
`BPPULSE
`R/W
`0
`
`b1
`BPEN
`R/W
`0
`
`E605
`
`b0
`0
`R
`0
`
`BREAKPT
`b7
`0
`R
`0
`
`Bit 3
`
`Break
`
`Bit 2
`
`BPPULSE
`
`Bit 1
`
`BPEN
`
`BPADDRH
`b7
`A15
`R/W
`x
`
`BPADDRL
`b7
`A7
`R/W
`x
`
`Bit 15-0 A15:0
`
`b6
`A14
`R/W
`x
`
`b6
`A6
`R/W
`x
`
`Enable Breakpoint
`The BREAK bit is set when the CPU address bus matches the address held in the bit breakpoint
`address registers (0xE606/07). The BKPT pin reflects the state of this bit. Write a ‘1’ to the BREAK bit
`to clear it. It is not necessary to clear the BREAK bit if the pulse mode bit (BPPULSE) is set.
`
`Breakpoint Pulse Mode
`Set this bit to ‘1’ to pulse the BREAK bit (and BKPT pin) high for 8 CLKOUT cycles when the 8051
`address bus matches the address held in the breakpoint address registers. When this bit is set to ‘0’,
`the BREAK bit (and BKPT pin) remains high until it is cleared by firmware.
`
`Breakpoint Enable
`If this bit is ‘1’, a BREAK signal is generated whenever the 16-bit address lines match the value in the
`Breakpoint Address Registers (BPADDRH:L). The behavior of the BREAK bit and associated BKP
`pin signal is either latched or pulsed, depending on the state of the BPPULSE bit.
`
`b5
`A13
`R/W
`x
`
`b5
`A5
`R/W
`x
`
`Breakpoint Address High
`b4
`b3
`A12
`A11
`R/W
`R/W
`x
`x
`
`Breakpoint Address Low
`b4
`b3
`A4
`A3
`R/W
`R/W
`x
`x
`
`b2
`A10
`R/W
`x
`
`b2
`A2
`R/W
`x
`
`b1
`A9
`R/W
`x
`
`b1
`A1
`R/W
`x
`
`E606
`
`E607
`
`b0
`A8
`R/W
`x
`
`b0
`A0
`R/W
`x
`
`High and Low Breakpoint Address
`When the current 16-bit address (code or XDATA) matches the BPADDRH/BPADDRL address, a
`breakpoint event occurs. The BPPULSE and BPEN bits in the BREAKPT register control the action
`taken on a breakpoint event.
`
`15.5.6
`
`230 Kbaud Clock (T0, T1, T2)
`
`UART230
`b7
`0
`R
`0
`
`Bit 1- 0
`
`230UARTx
`
`b6
`0
`R
`0
`
`b5
`0
`R
`0
`
`230 KBaud Clock for T1
`b4
`b3
`0
`0
`R
`R
`0
`0
`
`b2
`0
`R
`0
`
`b1
`230UART1
`R/W
`0
`
`E608
`
`b0
`230UART0
`R/W
`0
`
`Set 230 KBaud Operation
`Setting these bits to 1 overrides the timer inputs to the USARTs, and USART0 and USART1 will use
`the 230 KBaud clock rate. This mode provides the correct frequency to the USART regardless of the
`CPU clock frequency (12, 24, or 48 MHz).
`
`250
`
`MoBL-USB™ TRM, Document # 001-11981 Rev. *B
`
`Exhibit 2033 - Page 250 of 346
`
`

`
`15.5.7
`
`Slave FIFO Interface Pins Polarity
`
`Slave FIFO Interface Pins Polarity
`
`b6
`0
`R
`0
`
`b5
`PKTEND
`R/W
`0
`
`b4
`SLOE
`R/W
`0
`
`b3
`SLRD
`R/W
`0
`
`b2
`SLWR
`R/W
`0
`
`b1
`EF
`R/W
`0
`
`Registers
`
`E609
`
`b0
`FF
`R/W
`0
`
`FIFOPINPOLAR
`see Section 15.15
`b7
`0
`R
`0
`
`Bit 5
`
`PKTEND
`
`Bit 4
`
`SLOE
`
`Bit 3
`
`SLRD
`
`Bit 2
`
`SLWR
`
`Bit 1
`
`EF
`
`Bit 0
`
`FF
`
`FIFO Packet End Polarity
`This bit selects the polarity of the PKTEND FIFO input pin. 0 selects the polarity shown in the data
`sheet (active low). 1 selects active high.
`
`FIFO Output Enable Polarity
`This bit selects the polarity of the SLOE FIFO input pin. 0 selects the polarity shown in the data sheet
`(active low). 1 selects active high.
`
`FIFO Read Polarity
`This bit selects the polarity of the SLRD FIFO input pin. 0 selects the polarity shown in the data sheet
`(active low). 1 selects active high.
`
`FIFO Write Polarity
`This bit selects the polarity of the SLWR FIFO input pin. 0 selects the polarity shown in the data sheet
`(active low). 1 selects active high.
`
`Empty Flag Polarity
`This bit selects the polarity of the Empty Flag output pin. 0 selects the polarity shown in the data
`sheet (active low). 1 selects active high.
`
`Full Flag Polarity
`This bit selects the polarity of the Full Flag output pin. 0 selects the polarity shown in the data sheet
`(active low). 1 selects active high.
`
`15.5.8
`
`Chip Revision ID
`
`REVID
`
`b7
`RV7
`R
`0
`
`Bit 7-0
`
`RV7:0
`
`b6
`RV6
`R
`0
`
`b5
`RV5
`R
`0
`
`Chip Revision ID
`b4
`b3
`RV4
`RV3
`R
`R
`0
`0
`
`b2
`RV2
`R
`0
`
`b1
`RV1
`R
`0
`
`E60A
`
`b0
`RV0
`R
`1
`
`Chip Revision Number
`These register bits define the silicon revision.
`
`MoBL-USB™ TRM, Document # 001-11981 Rev. *B
`
`251
`
`Exhibit 2033 - Page 251 of 346
`
`

`
`Registers
`
`15.5.9
`
`Chip Revision Control
`
`REVCTL
`See Section 15.15
`b7
`0
`R
`0
`
`b6
`0
`R
`0
`
`Chip Revision Control
`
`E60B
`
`b5
`0
`R
`0
`
`b4
`0
`R
`0
`
`b3
`0
`R
`0
`
`b2
`0
`R
`0
`
`b1
`DYN_OUT
`R/W
`0
`
`b0
`ENH_PKT
`R/W
`0
`
`Important Note DYN_OUT and ENH_PKT default to ‘0’ on a hard reset. Cypress highly recommends setting both
`bits to ‘1’.
`
`Bit 1
`
`DYN_OUT
`
`Bit 0
`
`ENH_PKT
`
`Disable Auto-Arming at the 0-1 transition of AUTOOUT
`When DYN_OUT=0, the core automatically arms the endpoints when AUTOOUT is switched from ‘0’
`to “1’. This means that firmware must reset the endpoint (and risk losing endpoint data) when switch-
`ing between Auto-Out mode and Manual-Out mode.
`When DYN_OUT=1, the core disables auto-arming of the endpoints when AUTOOUT transitions
`from ‘0’ to ‘1’. This feature allows CPU intervention when switching between AUTO and Manual mode
`without having to reset the endpoint.
`Note When DYN_OUT=1 and AUTOOUT=1, the CPU is responsible for ‘priming the pump’ by
`initially arming the endpoints (OUTPKTEND w/SKIP=1 to pass packets to host).
`
`Enhanced Packet Handling
`When ENH_PKT=0, the CPU can neither source OUT packets nor skip IN packets; it has only the
`following capabilities:
`OUT packets: Skip or Commit
`IN packets: Commit or Edit/Source
`
`When ENH_PKT=1, the CPU has additional capabilities:
`OUT packets: Skip, Commit, or Edit/Source
`IN packets: Skip, Commit, or Edit/Source
`
`252
`
`MoBL-USB™ TRM, Document # 001-11981 Rev. *B
`
`Exhibit 2033 - Page 252 of 346
`
`

`
`Registers
`
`15.5.10 GPIF Hold Time
`GPIFHOLDAMOUNT
`b7
`0
`R
`0
`
`b6
`0
`R
`0
`
`b5
`0
`R
`0
`
`b4
`0
`R
`0
`
`b3
`0
`R
`0
`
`b2
`0
`R
`0
`
`b1
`
`E60C
`
`b0
`
`HOLDTIME[1:0]
`RW
`RW
`0
`0
`
`For any transaction where the GPIF writes data onto FD[15:0], this register determines how long the data is held. Valid
`choices are ‘0’, ‘½’, or ‘1’ IFCLK cycle. This register applies to any data written by the GPIF to FD[15:0], whether through a
`flow state or not.
`For non-flow states, the hold amount is really just a delay of the normal (non-held) presentation of FD[15:0] by the amount
`specified in HOLDTIME[1:0].
`For flow states in which the GPIF is the master on the bus (FLOWSTB.SLAVE = 0), the hold amount is with respect to the
`activating edge (see FLOW_MASTERSTB_EDGE) of Master Strobe (which will be a CTL pin in this case).
`For flow states in which the GPIF is the slave on the bus (FLOWSTB.SLAVE = 1), the hold amount is really just a delay of the
`normal (non-held) presentation of FD[15:0] by the amount specified in HOLDTIME[1:0] in reaction to the activating edge of
`Master Strobe (which will be a RDY pin in this case). Note the hold amount is NOT directly with respect to the activating edge
`of Master Strobe in this case. It is with respect to when the data would normally come out in response to Master Strobe includ-
`ing any latency to synchronize Master Strobe.
`In all cases, the data will be held for the desired amount even if the ensuing GPIF state calls for the data bus to be tri-stated.
`In other words the FD[15:0] output enable will be held by the same amount as the data itself.
`
`Bits 1-0 HOLDTIME[1:0]
`
`GPIF Hold Time
`00 = 0 IFCLK cycles
`01 = ½ IFCLK cycle
`10 = 1 IFCLK cycle
`11 = Reserved
`
`15.6
`
`Endpoint Configuration
`
`15.6.1
`
`Endpoint 1-OUT/Endpoint 1-IN Configurations
`
`EP1OUTCFG
`EP1INCFG
`b7
`VALID
`R/W
`1
`
`Bit 7
`
`VALID
`
`b6
`0
`R
`0
`
`b5
`TYPE1
`R/W
`1
`
`Endpoint 1-OUT Configuration
`Endpoint 1-IN Configuration
`b4
`b3
`TYPE0
`0
`R/W
`R
`0
`0
`
`b2
`0
`R
`0
`
`b1
`0
`R
`0
`
`E610
`E611
`
`b0
`0
`R
`0
`
`Activate an Endpoint
`Set VALID=1 to activate an endpoint, and VALID=0 to de-activate it. All endpoints default to VALID.
`An endpoint whose VALID bit is 0 does not respond to any USB traffic.
`
`Bit 5-4
`
`TYPE1:0
`
`Defines the Endpoint Type
`These bits define the endpoint type, as shown in the table below.
`
`TYPE1
`0
`0
`1
`1
`
`TYPE0
`0
`1
`0
`1
`
`Endpoint Type
`
`Invalid
`Invalid
`BULK (default)
`INTERRUPT
`
`MoBL-USB™ TRM, Document # 001-11981 Rev. *B
`
`253
`
`Exhibit 2033 - Page 253 of 346
`
`

`
`Registers
`
`15.6.2
`
`Endpoint 2, 4, 6 and 8 Configuration
`
`EP2CFG
`b7
`VALID
`R/W
`1
`
`EP4CFG
`b7
`VALID
`R/W
`1
`
`EP6CFG
`b7
`VALID
`R/W
`1
`
`EP8CFG
`b7
`VALID
`R/W
`1
`
`b6
`DIR
`R/W
`0
`
`b6
`DIR
`R/W
`0
`
`b6
`DIR
`R/W
`1
`
`b6
`DIR
`R/W
`1
`
`b5
`TYPE1
`R/W
`1
`
`b5
`TYPE1
`R/W
`1
`
`b5
`TYPE1
`R/W
`1
`
`b5
`TYPE1
`R/W
`1
`
`Endpoint 2 Configuration
`b4
`b3
`TYPE0
`SIZE
`R/W
`R/W
`0
`0
`
`Endpoint 4 Configuration
`b4
`b3
`TYPE0
`0
`R/W
`R
`0
`0
`
`Endpoint 6 Configuration
`b4
`b3
`TYPE0
`SIZE
`R/W
`R/W
`0
`0
`
`Endpoint 8 Configuration
`b4
`b3
`TYPE0
`0
`R/W
`R
`0
`0
`
`b2
`0
`R
`0
`
`b2
`0
`R
`0
`
`b2
`0
`R
`0
`
`b2
`0
`R
`0
`
`b1
`BUF1
`R/W
`1
`
`b1
`0
`R
`0
`
`b1
`BUF1
`R/W
`1
`
`b1
`0
`R
`0
`
`E612
`
`E613
`
`E614
`
`E615
`
`b0
`BUF0
`R/W
`0
`
`b0
`0
`R
`0
`
`b0
`BUF0
`R/W
`0
`
`b0
`0
`R
`0
`
`These registers configure the large, data-handling endpoints.
`
`Bit 7
`
`VALID
`
`Bit 6
`
`DIR
`
`Bit 5-4
`
`TYPE
`
`Activate an Endpoint
`Set VALID=1 to activate an endpoint, and VALID=0 to de-activate it. All endpoints default to valid. An
`endpoint whose VALID bit is 0 does not respond to any USB traffic.
`
`Sets Endpoint Direction
`0 = OUT, 1 = IN
`
`Defines the Endpoint Type
`These bits define the endpoint type, as shown in the table below. The TYPE bits apply to all of the
`large-endpoint configuration registers.
`
`TYPE1
`0
`0
`1
`1
`
`TYPE0
`0
`1
`0
`1
`
`Endpoint Type
`
`Invalid
`ISOCHRONOUS
`BULK (default)
`INTERRUPT
`
`Bit 3
`
`SIZE
`
`Bit 1-0
`
`BUF
`
`Sets Size of Endpoint Buffer
`0 = 512 bytes, 1 = 1024 bytes
`Endpoints 4 and 8 can only be 512 bytes. Endpoints 2 and 6 are selectable.
`
`Buffering Type/Amount
`The amount of endpoint buffering is presented in the table below.
`
`BUF1
`0
`0
`1
`1
`
`BUF0
`0
`1
`0
`1
`
`Buffering
`Quad
`Invalid
`Double
`Triple
`
`254
`
`MoBL-USB™ TRM, Document # 001-11981 Rev. *B
`
`Exhibit 2033 - Page 254 of 346
`
`

`
`Registers
`
`Note The Valid bit is ignored when buffer space is allocated by the EZ-USB (for example, BUF[1:0] takes precedence over the Valid bit).
`When you are not using all of the endpoints in the endpoint configuration, disable the unused endpoints by writing a zero into the “valid” bit of
`the corresponding EPxCFG register without disturbing the default state of the other bits in the register.
`
`For example, if the endpoint configuration 11 (see 1.18 MoBL-USB FX2LP18 Endpoint Buffers on page 28), which uses only endpoints 2
`and 8, must be used, configure the endpoints as follows.
`EP2CFG = 0xDB;
`SYNCDELAY;
`EP8CFG = 0x92;
`SYNCDELAY;
`EP4CFG &= 0x7F;
`SYNCDELAY;
`EP6CFG &=0x7F;
`SYNCDELAY;
`
`15.6.3
`
`Endpoint 2, 4, 6 and 8/Slave FIFO Configuration
`
`EP2FIFOCFG
`see Section 15.15
`EP4FIFOCFG
`see Section 15.15
`EP6FIFOCFG
`see Section 15.15
`EP8FIFOCFG
`see Section 15.15
`b7
`0
`R
`0
`
`Bit 6
`
`INFM1
`
`Bit 5
`
`OEP1
`
`Bit 4
`
`AUTOOUT
`
`Endpoint 2/Slave FIFO Configuration
`
`Endpoint 4/Slave FIFO Configuration
`
`Endpoint 6/Slave FIFO Configuration
`
`Endpoint 8/Slave FIFO Configuration
`
`E618
`
`E619
`
`E61A
`
`E61B
`
`b6
`INFM1
`R/W
`0
`
`b5
`OEP1
`R/W
`0
`
`b4
`AUTOOUT
`R/W
`0
`
`b3
`AUTOIN
`R/W
`0
`
`b2
`ZEROLENIN
`R/W
`1
`
`b1
`0
`R
`0
`
`b0
`WORDWIDE
`R/W
`1
`
`IN Full Minus One
`When a FIFO configuration register’s ‘INEARLY’ or INFM bit is set to 1, the FIFO flags for that
`endpoint become valid one sample earlier than when the FULL condition occurs. These bits take
`effect only when the FIFOs are operating synchronously—according to an internally- or externally
`supplied clock. Having the FIFO flag indications a clock early simplifies some synchronous interfaces
`(applies only to IN endpoints).
`
`OUT Empty Plus One
`When a FIFO configuration register’s ‘OUTEARLY’ or OEP1 bit is set to 1, the FIFO flags for that end
`point become valid one sample earlier than when the EMPTY condition occurs. These bits take effect
`only when the FIFOs are operating synchronously—according to an internally- or externally-supplied
`clock. Having the FIFO flag indications a clock early simplifies some synchronous interfaces (applies
`only to OUT endpoints).
`
`Instantaneous Connection to Endpoint FIFO
`This bit applies only to OUT endpoints.
`When AUTOOUT=1, as soon as a buffer fills with USB data, the buffer is automatically and instanta-
`neously committed to the endpoint FIFO bypassing the CPU. The endpoint FIFO flags and buffer
`counts immediately indicate the change in FIFO status. Refer to the description of the DYN_OUT bit
`in section 15.5.9 Chip Revision Control on page 252.
`When AUTOOUT=0, as soon as a buffer fills with USB data, an endpoint interrupt is asserted. The
`connection of the buffer to the endpoint FIFO is under control of the firmware, rather than automati-
`cally being connected. Using this method, the firmware can inspect the data in OUT packets, and
`based on what it finds, choose to include that packet in the endpoint FIFO or not. The firmware can
`even modify the packet data, and then commit it to the endpoint FIFO. Refer to Enhanced Packet
`Handling in section 15.5.9 Chip Revision Control on page 252.
`The SKIP bit (in the EPxBCL registers) chooses between skipping and committing packet data. Refer
`to OUTPKTEND in section 15.6.8 Force OUT Packet End on page 266.
`
`MoBL-USB™ TRM, Document # 001-11981 Rev. *B
`
`255
`
`Exhibit 2033 - Page 255 of 346
`
`

`
`Registers
`
`Bit 3
`
`AUTOIN
`
`Bit 2
`
`ZEROLENIN
`
`Bit 0
`
`WORDWIDE
`
`Auto Commit to SIE
`This bit applies only to IN endpoints.
`MoBL-USB FX2LP18 has EPxAUTOINLEN registers that allow the firmware to configure endpoints to
`sizes smaller than the physical memory sizes used to implement the endpoint buffer