`
`Declaration
`
`This dissertation contains the results of research undertaken by the author between October
`
`1995 and December 1998 at the Engineering Department of Cambridge University. No part
`
`of this dissertation is the result of work done in collaboration with others, except where
`
`explicitly described or cited within the text. The contents have not been submitted, in whole
`
`or in part, for any other University degree or diploma.
`
`Kim Leong Tan
`
`Cambridge, February 1999
`
`
`
`
`
`
`
`
`
`To Sims
`To Sian
`
`and
`and
`
`ourfamilies
`ourfimtifz’es
`
`
`
`v
`
`
`
`
`
`
`
`CONTENTS
`
`viii
`
`4.4.2 The replay of non-zero orders for phase-mismatched holograms ...................... 62
`
`4.5 Conclusions ...... ...................... ...... ............ .......... ......... .............. .... ........................... ... 63
`
`CHAPTERS
`
`Applications of coupling intensity and discrete hologram replay descriptions
`
`65
`
`5 .1 Introduction ................................................................................................................. 65
`
`5 .2 The design limitations of a large 1 :N holographic switch ............ .... ........ ..... .............. 65
`
`5.2.1 On-beam-axis coupling efficiency and off-beam-axis crosstalk power. ............ 67
`
`5.2.2 The number of hologram repeats for a l:N holographic switch ........................ 68
`
`5.2.3 Prospective 1 :N switch using a highly specified SLM ... ..... ......... ..................... 72
`
`5.3 Deterministic routing hologram generation ..................................................... ............ 75
`
`5.3.1 1-D hologram generation by choosing a combination of x 0 phase elements ..... 76
`
`5.3.2 Offsetting the 1-D combinations to provide 2-D routing patterns ..................... 78
`
`5.3.3 The advantages of the skip-rotate hologram generation technique ............ ........ 79
`
`5.4 Conclusions ................................................................................................................. 80
`
`CHAPTER 6
`
`FLC on CMOSNLSI Si spatial light modulators for holographic applications
`
`81
`
`6.1 Introduction ............................. ................. ... ..... .................. ............................ .... .... ..... 81
`
`6.2 Polarisation rotation as a means of phase modulation ........ ....................................... . 82
`
`6.2.1 Multi-level modulation .. ......... .. ................................. ... ..... ..... ......... ....... ... ..... ... 82
`
`6.2.2 Binary modulation .............................................................................................. 86
`
`6.3 Fast four-level phase-only modulation by polarisation rotation .................................. 88
`
`6.3 .1 Analysis of enhanced switching using a double-pass configuration ... .. ... .. ....... 89
`
`6.3 .2 Double-pass devices .. .......................... .......... ....... ............... ... .................... ... ..... 91
`
`6.4 Processing digital data input for analogue devices ................................. ... ... ......... ..... 93
`
`6.4.1 Global DA Cs .................. ........ .. .. ...... .. .................. ................. ............................. 94
`
`6.4.2 Column-select DA Cs ......................................................................................... 95
`
`6.4.3 Pixel-level DA Cs ............. ............................. .... ... .... ...... .... ..... ............ ......... .. .... 96
`
`6.4.4 Choice of DAC location for the demonstrator chip ........................................... 98
`
`6.5 Pixel design for coherent optical phase modulation ........ ... ...... ......... ...... ............... .... . 98
`
`
`
`CONTENTS
`
`ix
`
`6.5.1 Enhanced optical reflectors for the binary SLM .. ... .... ....................................... 98
`
`6.5.2 Transmissive pixels for quaternary SLM ........................................................... 99
`
`6.6 Semiconductor fabrication process ................... .......................................................... 99
`
`6.6.1 CBH lOV 2-µm CMOS process .... .. ... ............................................................. . 100
`
`6.6.2 CBY 50V 2-µm DMOS process ...................................................................... 103
`
`6.7 Conclusions ................................... .. ........................................... ........ ....... ................ 106
`
`CHAPTER 7
`
`Circuit design and layout of the Roses chip
`
`108
`
`7 .1 Introduction ..... ........................ .......................... ...... ................... ............. ... ... ............ 108
`
`7 .2 Specifications for the binary and quaternary modulators .......... .... ........ .. .................. 109
`
`7 .2.1 The reflective binary array .................................... ........ ................. ...... .... ........ 110
`
`7.2.2 The transmissive quaternary array ...... .... ... ...................................................... 111
`
`7 .3 Overall floor-plan ................................... ..... ........ ... ................................... ... ............. 111
`
`7.4 Features and simulated performance of the Roses chip ............................................ 113
`
`7 .5 Circuit design for binary modulation ..................................... ..... .............................. 116
`
`7.5 .1 Binary driver schematics and functionality ..................................................... 116
`
`7.5.2 Asynchronous global blanking ........ ........................................... ........... .......... . 118
`
`7.5.3 Standard geometry MOSFET design .................. ............................ .......... ....... 118
`
`7 .5 .4 Current-limiting in sizing level shifter transistors ........ ......... .......................... 118
`
`7 .5 .5 Speed versus current-limiting trade-off in sizing buffering transistors ........... 118
`
`7 .6 Layout of the binary backplane ............ ... ..... .. .. ..... ....................... .... .. ..... .................. 119
`
`7 .6.1 Standard geometry MOSFET layout.. .............................................................. 119
`
`7.6.2 Protecting supply lines from peak current effects .................... ........................ 119
`
`7 .6.3 Increasing the decoupling-capacitance of power lines ........................ ............ 120
`
`7 .6.4 Routing driver outputs to the pixel array .................. ....... ................................ 120
`
`7.6.5 Pixel tabs to contact MET3 pixels ............................ ......... ...... ........................ 120
`
`7.7 Circuit design for four-level modulation ...... ................................. .... ............... .... ..... 121
`
`7.7.1 Quaternary driver schematics and functionality .... ..... ............. ........................ 121
`
`7.7.2 Standard geometry MOSFET design ....................................... ... ............. ........ 123
`
`
`
`CONTENTS
`
`x
`
`7 .7.3 Converting drive voltages by digital selection of power rails ...... .. .. ...... ...... .. . 123
`
`7.7.4 Current limiting by sizing select transistors ............................ .. .. .... ............ .. ... 123
`
`7.8 Layout of the quaternary backplane .... .. .. .. ..................... ......... ......... .... .... .. ............... 124
`
`7 .8.1 Layout of the quaternary drivers ...................... .. ........ ............................... .. .. ... 124
`
`7 .8.2 Layout of the quaternary pixel array ........................ .. ............... .. ....... .. ........ .... 124
`
`7.9 Buffering of control signals ............ .. ... ....... .... ...... .... ... .. ... .. .. .. ........ .. .. ....................... 126
`
`7.10 Bonding pads ..... .... .... .. ........ ... ...... ... .. .... ..... ... ............... ..... ...... ........... ... .. ................ 126
`
`7 .11 Functionality tests .... ... .. .. ... .. ..... .... ... ..... .... .. ... ..... .. ..... ....... ...... .... .... ... ...................... 127
`
`7 .11.1 Test of the dynamic shift register data latching and shifting .. .. .. ........ ....... .... 127
`
`7.11.2 Test of frame update, level shifting and DIA conversion .......... ...... .. .. .. .. ...... 127
`
`7.12 Conclusions ...................................... .... ... ....... ... .................. .. ...... .... .. ....... ............... 129
`
`CHAPTERS
`
`Characterisation of fabricated Roses devices
`
`130
`
`8.1 Introduction ....................................... .. ........ .. ... ..... ..... ... ... ............... .. .... ...... .. ...... .. .... 130
`
`8.2 Initial tests of an unprocessed wafer .. ............ .. ............ .... ....... ....... .. ........ .. ....... .. .. .. .. 130
`
`8.2.1 Binary array .. .. .. ......................... .. ... .... ........ .. ... ..... .. .... .... .. .... .......... .. ................ 131
`
`8.2.2 Quaternary array .............. .. .......... ........ .. .......... .... .. .. ... .. ........ .... .... .. .. ...... .. .. ..... 133
`
`8.3 Processing silicon backplane devices and SLM assembly ................................ ........ 135
`
`8.3 .1 Optical quality mirror deposition ......... .. ..... .. ..................................... ....... .. .... . 135
`
`8.3 .2 Al-etch of protective mirror coating .... .. ...................... .. .... .. .. ... .... .............. .. ... 135
`
`8.3.3 Assembly of silicon backplane SLMs .... ... .... .. ................... .. .... .. .... .. .... ... ..... .... 135
`
`8.4 Tests of assembled SLMs ..... .... ..... .................. ............ ........ .... ................ ...... ...... ...... 136
`
`8.4.1 Initial optical inspection using the probe-station ...... ... .... ..... .... .. ..... .. .. .......... .. 136
`
`8.4.2 SLM interface and carrier design ... .. ........ .. .. .... ..... ..... .. .. .. ...... .. ... ..... .. .............. 139
`
`8.4.3 Imaging optical modulating using a polarising microscope ...... .. .. .... .... ... ... .... 140
`
`8 .5 Holographic SLM demonstrator ...... .. ...... .... .... .. ... .. ... .............. .. ... .. ........ .. .... .. ........... 143
`
`8.5.1 Replay field mapping using intensity modulation ... ... ... .. ..... .. .. ..... .................. 143
`
`8.5 .2 Reflective binary-phase holographic operation .... .... .. .... .. .. .. .. .. .. .. ................... 151
`
`8.6 Drive schemes issues for holographic applications ........................ .... .... .. .... .. .......... . 156
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
