United ‘States Patent [19]
`Sasuga et a1.
`
`US005432626A
`Patent Number:
`Date of Patent:
`
`[11]
`[45]
`
`5,432,626
`Jul. 11, 1995
`
`[54] LIQUID CRYSTAL DISPLAY DEVICE WITH
`SHIELD CASING CONNECTED TO FRAME
`HOLDING THE DISPLAY ABOVE LOWER
`CASING HOLDING LIGHT SOURCE
`[75] Inventors: Masiimi Sasuga; Junichi Ohwada;
`Akira Kobayashi; Masaru Fujita;
`all of Mobara;
`Hiroshi Nakamoto,
`Ryu Ono, Chiba; Tsutomu Isono,
`Ohtaki, all of Japan
`[73] Assignee: Hitachi, Ltd., Tokyo, Japan
`[21] Appl. No.: 29,622
`Mar. 11, 1993
`[22] Filed:
`Foreign Application Priority Data
`[30]
`4-053452
`Mar. 12, 1992 [JP]
`Japan
`[51] Int. c1.6
`G02F 1/1333; GOZF 1/1335
`[52] US. (:1.
`359/83; 359/50
`359/50, 43, 83
`
`[58] Field of Search [56]
`References Cited
`US. PATENT DOCUMENTS
`3,050,160 8/1962 Chesser
`4,294,517 10/1981 Jakubek
`
`189/36
`359/50
`
`4,367,467 1/ 1983 Emile, Jr. ..
`4,390,103 6/1983 Husbard
`4,486,077 12/1984 Torresdal
`4 755,035 7/1988 Kopish et a1.
`4 772,100 9/1988 Suenaga
`4,878,738 11/1989 Hanami
`5 146,354 9/1992 Plesinger
`
`.
`
`FOREIGN PATENT DOCUMENTS
`1-219823 9/1989 Japan
`
`359/48
`
`Primary Examiner-Anita Pellman Gross
`Attorney, Agent, or Firm—Antonelli, Terry, Stout &
`Kraus
`ABSTRACT
`[57]
`A liquid crystal display device which includes a shield
`casing made of a metal plate and having ?xing pawls
`and ?xing hooks, an middle frame for holding a liquid
`crystal display, and a lower casing for packaging back
`lights. The ?xing pawls of said shield casing are bent in
`corresponding recesses formed in the middle frame.
`Also, the ?xing hooks of said shield casing are ?tted on
`corresponding projections formed on the lower casing.
`
`7 Claims, 37 Drawing Sheets
`
`LGD_001314
`
`LG Display Ex. 1009
`
`

`
`US. Patent
`
`July 11, 1995
`
`Sheet 1 0f 37
`
`5,432,626
`
`GL (92)
`
`DL (d1, (12)
`
`GT (92)
`
`AS
`
`SDZ (d2, d3)
`SD1(d2, d3)
`
`FIG. 1
`
`92
`
`ITOl (d1
`
`BM
`
`FIL
`
`LGD_001315
`
`

`
`U.S. Patent
`
`July 11, 1995
`
`Sheet 2 of 37
`
`5,432,626
`
`F1612
`
`FIHR)
`
`BM IT02(COM) FIL(G)
`
` POL2
`
`Ktfijjjjjjikjjjjj
`71j.—1§—lwj?—‘?
`
`SIO
`
`SUB2
`
`;—.jjj“j“"“jj\ S10
`\
`.\\\'\\'IIIIlIIIIlIIII%4ZIIIIIIIU
`Wllllllli
`V
`“\‘
`K\\\‘\\\\\‘\\\\‘
`“V
`m
`-?--'k;jj »‘ 8 «-5 P S V 2
`
`P S V1
`G1
`
`{
`"""
`'
`'."/[Arr/7//’///"'//7.’/7,'2;": 117.22
`\
`
`IIIIIIIIII.
`
`L‘
`
`VV
`
`LGD_0O1316
`
`,
`,
`v.\\’
`|_‘‘‘-.‘‘‘“‘‘ D‘if§‘“I
`
`LGD_001316
`
`

`
`US. Patent
`
`July 11, 1995
`
`Sheet 3 of 37
`
`5,432,626
`
`Cadd
`
`ITOl, d1
`
`/
`
`‘
`
`mll‘llll ’
`
`VII"II””III”IIII~
`
`qIIIIIIIIIIIIIIIIIIIIIIIII)a n
`l‘.‘“\‘‘‘_‘‘‘“‘ GI
`
`GI
`
`S I 0
`
`PLl
`
`LGD_001317
`
`

`
`US. Patent
`
`July 11, 1995
`
`Sheet 4 of 37
`
`5,432,626
`
`m
`
`[E]
`
`m
`
`_1
`
`I
`
`IF!
`
`l
`
`[HI
`
`l
`
`F-TI
`
`yi:{>
`
`Yi+1 CD
`
`LGD_001318
`
`

`
`US. Patent
`
`July 11, 1995
`
`Sheet 5 of 37
`
`5,432,626
`
`FIG’. 5
`
`[I]
`
`GL (92)
`
`H/H
`
`LGD_001319
`
`

`
`US. Patent
`
`July 11, 1995
`
`Sheet 6 0f 37
`
`5,432,626
`
`FIG’. 5
`
`JL JL
`EL) 35
`
`d2, d3
`
`\JITOI (d1)
`/L_\
`DL (d2, d3)"
`\V
`
`I "'L
`
`I ‘1
`
`l
`
`L
`
`_1 ___[
`
`_1
`
`LGD_001320
`
`

`
`U.S. Patent
`
`Jul
`
`11
`
`5
`
`5,432,626
`
`FIG’. 7
`
`LGD_001321
`
`

`
`US. Patent
`
`July 11, 1995
`
`Sheet 8 of 37
`
`5,432,626
`
`LGD_001322
`
`

`
`US. Patent
`
`5,432,626
`
`{12.6
`
`\\\\\\\\\\\\\\\\\\\\\
`
`
`
`Aim .QTm
`
`LGD_001323
`
`

`
`U.S. Patent
`
`July 11, 1995
`
`Sheet 10 of 37
`
`5,432,626
`
`.1/4h7/////////////////////////////////I////l////l
`
`.//////.//////////////7////////////////////////////////
`
`\\\5s\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\%V\\\\\\\\\\%.\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\&‘
`
`
`
`.'.""'l.I.2""!_\\§\\\\\\\\\\\\\\ .w».Xn«WK\§A.o\\
`
`
`‘
`
`
`
`A3..3:13
`
`LGD 001324
`
`LGD_001324
`
`

`
`U.S. Patent
`
`July 11, 1995
`
`Sheet 11 of 37
`
`5,432,626
`
`Fl
`W
`ii
`E b"i
`
`if“
`AR
`
`11 an
`we
`
`’):
`
`C}:
`
`1’
`
`3:’
`
`(1:
`
`tr
`
`Hg
`
`SUP
`
`VERTICAL -SCANNING CKT
`
`CONVERTER
`POWER SUPPLY
`
`LGD_0O1325
`
`LGD_001325
`
`

`
`US. Patent
`
`July 11, 1995
`
`Sheet 12 of 37
`
`5,432,626
`
`FIG. 12
`
`Vlc
`
`LGD_001326
`
`

`
`US. Patent
`
`July 11, 1995
`
`Sheet 13 of 37'
`
`5,432,626
`
`
`.\\\\\\\\\\\\\\\\\\\\\\\\ 7/1
`////////////////I7/
`
`Amv
`
`as 3232:: 2
`
`E. Z: 322 2;
`
`i155 2
`
`A8
`:2 S: 222 2”
`
`32.2.32
`
`\\\\\\\\\\\\\\\\\\k
`
`:3 3232:: 5
`
`3202 S E 2: 322 t:
`
`OHm g
`
`LGD_001327
`
`

`
`US. Patent
`
`July 11, 1995
`
`Sheet 14 0f 37
`
`5,432,626
`
`r///////////!////I//////l
`
`a v
`:2 E m
`
`$5 3L
`
`a: a; 5;
`
`A m v
`
`A m v
`
`
`
`5.: 2:2: E
`
`5.2.3530 a;
`
`:u 2: 222 in
`
`:8 r m a z E
`
`H6
`
`LGD_001328
`
`

`
`US. Patent
`
`July 11, 1995
`
`Sheet 15 of 37
`
`5,432,626
`
`\\\\\\\\\\\\\\\ N
`
`7////////////////////?h1
`
`E; 2:55 s
`
`:3 3232:: 2
`
`:3 2E: z
`E .2 .2 =5 :5 E
`
`7////////////////////?n,
`
`E: :5 E: 2
`
`53 2E: z;
`
`a: 2E: a;
`$3 2 2:: s
`
`52:54:“ A H v
`
`20v
`
`213
`:3 :5: o:
`
`
`
`:3 3232:: 0.:
`
`E. 5:2: 3
`
`MN .QTm
`
`l .44.
`\\\\ , I. Iv H U
`
`1 \
`
`K0, 5
`
`LGD_001329
`
`

`
`US. Patent
`
`July 11, 1995
`
`Sheet 16 of 37
`
`5,432,626
`
`Z
`
`"I I
`
`“V:
`
`La,
`
`[-4
`
`|._.........._____----_-.._.._-__..___.._______.._
`
`.<
`
`i
`
`<
`
`<
`
`i
`
`1
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`l
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`l
`l
`I
`I
`I
`I
`I
`I
`I
`I
`I
`l
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`l
`l
`I
`I
`l
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`LGD_001330
`
`

`
`US. Patent
`
`July 11, 1995
`
`Sheet 17 of 37
`
`5,432,626
`
`__-_________-...._____--_________:_5______._________________________-_______
`Z
`
`1
`l
`l
`I
`I
`I
`I
`I
`I
`l
`l
`l
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`l
`l
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`l
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`l
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`|
`I
`l
`l
`I
`I
`I
`I
`l
`
`:38 N9:
`
`LGD_001331
`
`

`
`US. Patent
`
`July 11, 1995
`
`Sheet 18 0f 37
`
`5,432,626
`
`£08 3.:
`
`5
`
`5
`
`:58 N9:
`
`LGD_001332
`
`

`
`US. Patent
`
`July 11, 1995
`
`Sheet 19 of 37
`
`5,432,626
`
`:iHoBH
`
`Aov Anv Asv
`
`
`
`
`£03 3.2 a: 4;
`
`%\ .Q\b~
`
`LGD_001333
`
`

`
`U.S. Patent
`
`July .11, 1995
`
`Sheet 20 of 37
`
`5,432,626
`
`
`
` i.‘I‘\‘s“‘\‘§..'4''‘
`
`\\\\\\\\\\\\\\\\\\\\\\\.
`
`hi‘‘‘‘~‘‘.
`
`\\\\\\\\\\\\.V"”’5:O
`\\\\\\\
`at
`
`.7////.7/////////.7///////////////////////////////////4u‘‘\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\§.‘Li
`'.|'nI‘“lIlI
`
`LGD 001334
`
`LGD_001334
`
`
`
`

`
`U.S. Patent
`
`July 11, 1995
`
`Sheet 21 of 37
`
`5,432,626
`
`3“
`CHI
`BIN
`
`
`BF2
`
`
`
`
`
`SR5
`
`TTM
`
`
`
`ADP
`
`PRE
`
`LGD_0O1335
`
`LGD_001335
`
`

`
`U.S. Patent
`
`July 11, 1995
`
`Sheet 22 of 37
`
`5,432,626
`
`FIG. 23
`
`LGD 001336
`
`LGD_001336
`
`

`
`U.S. Patent
`
`July 11, 1995
`
`Sheet 23 of 37
`
`5,432,626
`
`FIG. 24
`
`LGD_0O1337
`
`LGD_001337
`
`

`
`U.S. Patent
`
`July 11, 1995
`
`Sheet 24 of 37
`
`5,432,626
`
`FIG’. 25
`
`LGD_0O1338
`
`LGD_001338
`
`

`
`U.S. Patent
`
`July 11, 1995
`
`Sheet 25 of 37
`
`5,432,626
`
`FIG’. 26
`
`FGP
`
`FGP
`
`LGD_0O1339
`
`LGD_001339
`
`

`
`U.S. Patent
`
`July 11, 1995
`
`Sheet 26 of 37
`
`5,432,626
`
`FIG’. 27
`
`LGD_0O1340
`
`LGD_001340
`
`

`
`U.S. Patent
`
`July 11, 1995
`
`Sheet 27 of 37
`
`5,432,626
`
`FIG’. 26’
`
`LGD_OO1341
`
`LGD_001341
`
`

`
`5,432,626
`
`LGD_001342
`
`

`
`U.S. Patent
`
`July 11, 1995
`
`Sheet 29 of 37
`
`5,432,626
`
`““""c>"::"
`
`°
`
`COH
`
`CJ
`
`COH
`
`3”[_']nmuoO.
`
`0
`
`0
`
`:1
`
`n T
`
`:
`
`
`
`.In:Ia:l]Dfltnnn
`
`BC2
`
`LGD_0O1343
`
`LGD_001343
`
`

`
`U.S. Patent
`
`July 11, 1995
`
`Sheet 30 of 37
`
`5,432,626
`
`FIG’. 3]
`
`PCB1
`
`PCB1
`
`FC
`
`LGD_001344
`
`LGD_001344
`
`

`
`U.S. Patent
`
`July 11, 1995
`
`Sheet 31 of 37
`
`5,432,626
`
`FIG’. 32
`
`LGD_0O1345
`
`LGD_001345
`
`

`
`U.S. Patent
`
`July 11, 1995
`
`Sheet 32 of 37
`
`5,432,626
`
`LGD_0O1346
`
`LGD_001346
`
`

`
`1
`
`LV
`
`L
`
`9
`
`U!M E}
`
`HL
`
`FKP
`
`=5
`RM II
`
`IHL
`
`o
`
`FKP
`
`1
`
`38
`¢
`
`0
`
`FKP H
`
`.1
`I
`
`I
`
`I
`
`.U
`
`LGD_001347
`
`

`
`U.S. Patent
`
`July 11, 1995
`
`Sheet 34 of 37
`
`5,432,626
`
`FIG’. 35
`
`LGD_0O1348
`
`LGD_001348
`
`

`
`LGD_001349
`
`

`
`.
`
`3?
`
`I
`
`F
`
`LGD_001350
`
`

`
`U.S. Patent
`
`July 11, 1995
`
`Sheet 37 of 37
`
`5,432,626
`
`
`
`TF 1
`
`36
`BL
`RM\
`
`.
`.
`__ _!a§_
`
`
`
`
`LGD_OO1351
`
`LGD_001351
`
`

`
`1
`
`5,432,626
`
`LIQUID CRYSTAL DISPLAY DEVICE WITH
`SHIELD CASING CONNECTED TO FRAME
`HOLDING THE DISPLAY ABOVE LOWER
`CASING HOLDING LIGHT SOURCE
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`The present invention relates to a liquid crystal dis-
`play device and, more particularly, to a liquid crystal
`display device of active matrix type using thin film
`transistors or the like.
`2. Prior Art
`
`In a liquid crystal display device of active matrix
`type, non-linear devices (e.g., switching devices) are
`disposed in a manner to correspond to a plurality of
`pixel electrodes arranged in matrix, respectively. The
`liquid crystal in each pixel is always drive, in principle,
`(at a duty ratio of 1.0). In comparison with the so-called
`“simple matrix type” which employs a time division
`driving system, therefore, the active system has better
`contrast and has become an indispensable technique
`particularly in a color liquid crystal display device. A
`typical example of the switching devices is a thin film
`transistor (TFT).
`A liquid crystal display circuit (or a liquid crystal
`display panel) is constructed: by superposing a lower
`substrate, which is formed, over a lower transparent
`glass substrate with reference to a liquid crystal layer,
`sequentially with a thin film transistor, a transparent
`pixel electrode, a passivation film for the thin film tran-
`sistor, and a lower orientation film for orienting liquid
`crystal molecules; and an upper substrate, which is
`formed over an upper transparent glass substrate se-
`quentially with a black matrix, a color filter, a passiv-
`ation film for the color filter, a common transparent
`pixel electrode and an upper orientation film, such that
`their orientation films are opposed to each other; by
`bonding the two substrates by a sealing material ar-
`ranged around the edges of the substrates; and by seal-
`ing up the liquid crystals between the two substrates.
`Incidentally, a back light is arranged at the side of the
`lower substrate.
`Here, the liquid crystal display device of active ma-
`trix type using the thin film transistors is known in Japa-
`nese Patent Laid-Open No. 309921/1988 or on pp. 193
`to 210 of Nikkei Electronics entitled “Active Matrix
`
`Type Color Liquid Crystal Display of 12.5 Type
`Adopting Redundant Construction” and issued on Dec.
`15, 1986 by NIKKEI McGRAW-HILL, for example.
`SUMMARY OF THE INVENTION
`
`Since a shield casing made of a metal plate or a liquid
`crystal display circuit is fixed by means of rivets, the
`liquid crystal display device of the prior art is troubled
`by a difficulty in repair or replacement of the back
`lights.
`An object of the present invention is to provide a
`liquid crystal display device which can be easily re-
`paired or repaired in its back lights.
`According to one embodiment of the present inven-
`tion, there is provided a liquid crystal display device
`which comprises: a shield casing made of a metal plate
`and having fixing pawls and fixing hooks; an middle
`frame for holding a liquid crystal display; and a lower
`casing for packaging back lights, wherein the fixing
`pawls of said shield casing are bent in corresponding
`recesses formed in the middle frame, and wherein the
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`45
`
`50
`
`55
`
`65
`
`LGD_0O1352
`
`2
`fixing hooks of said shield casing are fitted on corre-
`sponding projections formed on the lower casing.
`The liquid crystal display device can be easily re-
`paired and replaced in its back lights because the fixing
`pawls and hooks of the shield casing can be easily re-
`moved and because the shield casing, the middle frame
`for holding the liquid crystal display and the lower
`casing for packaging the back lights are easily assem-
`bled and disassembled.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a top plan view showing an essential portion
`of one pixel of the liquid crystal display of a color liquid
`crystal display circuit of active matrix type, to which is
`applied the present invention;
`FIG. 2 is a section taken along line 2-2 of FIG. 1 and
`shows one pixel and its peripheral portion;
`FIG. 3 is a section taken along line 3-3 of FIG. 1 and
`shows an additional capacitor Cadd;
`FIG. 4 is a top plan view showing an essential portion
`of a liquid crystal display circuit arranged with a plural-
`ity of pixels shown in FIG. 1;
`FIG. 5 is a top plan view drawing only layers g2 and
`AS of the pixel shown in FIG. 1;
`FIG. 6 is a top plan View drawing only layers d1, d2
`and d3 of the pixel shown in FIG. 1;
`’
`FIG. 7 is a top plan view drawing only a pixel elec-
`trode layer, a light-shielding film and a color filter layer
`of the pixel shown in FIG. 1;
`FIG. 8 is a top plan view showing an essential portion
`of only the pixel electrode layer,
`the light-shielding
`layer and the color filter layer shown in FIG. 6;
`FIGS. 9(A) and 9(B) present a top plan view and a
`section showing the vicinity of a connecting portion
`between a gate terminal GTM and a gate signal line
`GL;
`FIGS. 10(A) and 10(B) present a top plan view and a
`section showing the vicinity of a connecting portion
`between a drain terminal DTM and a video signal line
`DL;
`FIG. 11 is an equivalent circuit diagram showing a
`liquid crystal display circuit of a color liquid crystal
`display device of active matrix type;
`FIG. 12 is an equivalent circuit diagram showing the
`pixel shown in FIG. 1;
`FIG. 13 presents a flow chart of sections of a pixel
`portion and a gate terminal portion and shows the fabri-
`cation steps A to C at the side of a substrate SUB1;
`FIG. 14 presents a flow chart of sections of the pixel
`portion and the gate terminal portion and shows the
`fabrication steps D to F at the side of the substrate
`SUB1;
`FIG. 15 presents a flow chart of sections of the pixel
`portion and the gate terminal portion and shows the
`fabrication steps G , to I at the side of the substrate
`SUB1;
`FIG. 16 is a top plan view for explaining the con-
`struction a matrix peripheral portion of a display panel;
`FIG. 17 is a panel top plan view for exaggerating and
`explaining the peripheral portion of FIG. 16 more spe-
`cifically;
`FIG. 18 is an enlarged top plan view showing a cor-
`ner of a display panel including an electric connection
`portion of upper and lower substrates;
`FIG. 19 is a section showing the pixel portion of a
`matrix at the center and the vicinity of a panel corner
`
`LGD_001352
`
`

`
`3
`and the vicinity of a video signal terminal portion at the
`two sides;
`FIG. 20 is a section showing panel edge portions with
`and without a scanning signal terminal at the lefthand
`and righthand sides;
`FIG. 21 is a section showing a structure of a tape
`carrier package TCP, in which an integrated circuit
`chip CHI constituting a drive circuit is mounted on a
`flexible wiring substrate;
`FIG. 22 is a section showing the state of an essential
`portion, in which the tape carrier package TCP is con-
`nected with a video signal circuit terminal DTP of a
`liquid crystal display panel PNL;
`FIG. 23 is an exploded perspective View showing a
`liquid crystal display module;
`FIG. 24 presents upper side, front side, rear side,
`righthand side and lefthand side views of a shield casing
`of the liquid crystal display module;
`FIG. 25 is a perspective view showing the shield
`casing and taken from the upper side;
`FIG. 26 is a upper side view showing the state, in
`which peripheral drive circuits are packaged in the
`liquid crystal display panel;
`FIG. 27 presents upper side, front side, rear side,
`righthand side and lefthand side views of a middle
`frame;
`FIG. 28 is a lower side view showing the middle
`frame;
`FIG. 29 is a perspective view showing the middle
`frame and taken from the upper side;
`FIG. 30 is a lower side view showing a drive circuit
`substrate to be mounted on the middle frame;
`FIG. 31 is an upper side view showing the connection
`state between the peripheral drive circuit substrate (as
`viewed from the upper side) of the liquid crystal display
`and the drive circuit substrate (as viewed from the
`lower side) to be mounted on the middle frame;
`FIG. 32 presents upper side, rear side, righthand side
`and lefthand side views of a back light support;
`FIG. 33 is a perspective view showing the back light
`support and taken from the upper side;
`FIG. 34 presents upper side (or reflection side), rear
`side, righthand side and lefthand side of a lower casing;
`FIG. 35 is a lower side view of the lower casing;
`FIG. 36 is a perspective view showing the lower
`casing and taken from the upper side;
`FIG. 37 presents upper side, rear side, righthand side
`and lefthand side views showing the state, in which the
`back light support, back lights and‘ an inverter circuit
`substrate are mounted in the lower casing;
`FIG. 38 is a section (as taken along line 38-38 of
`FIG. 34) of the lower casing; and
`FIG. 39 is a section taken along line 39-39 of FIG.
`37.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`The present invention, other objects of the present
`invention, and other features of the present invention
`will become apparent from the following description to 60
`be made with reference to the accompanying drawings.
`
`ACTIVE MATRIX LIQUID CRYSTAL DISPLAY
`DEVICE
`
`Here will be described in the following the construc- 65
`tion of the present invention in connection with em-
`bodiments of a color liquid crystal display device of
`active matrix type, to which is applied the present in-
`
`LGD_0O1353
`
`5,432,626
`
`5
`
`l0
`
`15
`
`20
`
`25
`
`30
`
`35
`
`45
`
`50
`
`55
`
`4
`vention. Incidentally, the parts having identical func-
`tions; are designated at identical reference characters
`throughout all the Figures for describing the embodi-
`ments, and their repeated descriptions will be omitted.
`SUMMARY OF. MATRIX PORTION
`
`FIG. 1 is a top plan View showing one embodiment of
`one pixel and its peripheral portion of the active matrix
`type color liquid crystal display device to which is
`applied the present invention. FIG. 2 is a section taken
`along line 2-2 of FIG. 1. FIG. 3 is a section taken
`along line 3-3 of FIG. 1. On the other hand, FIG. 4 is
`a top plan view showing the case in which a plurality of
`pixels shown in FIG. 1 are arranged.
`As shown in FIG. 1, each pixel is arranged in a cross
`region (defined by four signal lines) between two adja-
`cent scanning signal lines (e.g., gate signal lines or hori-
`zontal signal lines) GL and two video signal lines (e.g.,
`drain signal lines or vertical signal lines) DL. Each pixel
`includes a thin film transistor TFT, a transparent pixel
`electrode ITO1 and a latching capacitor Cadd. The
`scanning signal lines GL are extended in the column
`direction and arranged in plurality in the row direction.
`The video signal lines DL are extended in the row
`direction and arranged in plurality in the column direc-
`tion.
`As shown in FIG. 2, the thin film transistor TFT and
`the transparent pixel electrode ITO1 are formed at the
`side of a lower transparent glass substrate SUB1 across
`a liquid crystal layer LC, and a color film FIL and a
`back matrix pattern BM for light shielding are formed at
`the side of an upper transparent glass substrate SUB2.
`The side of the lower transparent glass substrate SUB1
`is made to have a thickness of about l.l mm, for exam-
`ple. On the both surfaces of the transparent glass sub-
`strates SUB1 and SUB2, there are formed silicon oxide
`layers SIO which are deposited by the dip treatment.
`Accordingly, even if there exist sharp defects at the
`surfaces of the transparent glass substrates SUB1 and
`SUB2, the scanning signal lines GL as well as the color
`filter FIL to be deposited thereon can be protected from
`the sharp defects since the defects are covered with the
`silicon oxide layer SIO.
`On the surface of the upper transparent glass sub-
`strate SUB2 at the inner side (or the side of the liquid
`crystal LC), there are sequentially laminated the light-
`shielding film BM, the color filter FIL, a passivation
`film PSV2, a common transparent pixel electrode ITO2
`(or COM) and an upper orientation film ORI2.
`SUMMARY OF MATRIX PERIPHERY
`
`FIG. 16 is a top plan view showing an essential por-
`tion of the periphery of a matrix (AR) of a display panel
`PNL including the upper and lower glass substrates
`SUB1 and SUB2. FIG. 17 is a top plan view further
`exaggerating the peripheral portion. FIG. 18 is an en-
`larged top plan view showing the vicinity of a seal
`portion SL corresponding to the lefthand upper corner
`of the panel of FIGS. 16 and 17. Moreover, FIG. 19
`presents a section of FIG. 2 at the lefthand side, a sec-
`tion taken from line 19a 19a of FIG. 18 at the righthand
`side, and a section showing the vicinity of an external
`connection terminal DTM, to which is connected a
`video signal drive circuit. Likewise, FIG. 20 presents a
`section showing the vicinity of an external connection
`terminal GTM, to which is connected a scanning cir-
`cuit, at the lefthand side and a section showing the
`
`LGD_001353
`
`

`
`5,432,626
`
`5
`vicinity of a seal portion having no external connection
`terminal at the righthand side.
`In a fabrication of this panel, a plurality of devices are
`simultaneously worked and divided by a single sheet of
`glass substrate so as to improve the throughput, if the
`panel has a small size, but a glass substrate having a
`standardized size for any kind is worked and is reduced
`to the sizes matching the individual kinds so as to share
`the fabrication facilities, if the size is large. In either
`case, the glass is out after a series of steps. In FIGS. 16
`to 18 showing the latter example, FIGS. 16 and 17 show
`the state after the upper and lower substrates SUB1 and
`SUB2 have been cut, and FIG. 18 shows the state be-
`fore the cutting operation. Letters LN designate the
`edges of the two substrates before the cutting operation,
`and characters CT] and CT2 designates the individual
`positions at which the substrates SUB1 and SUB2 are to
`be out. In either case, the size of the upper substrate
`SUB2 is so limited to the inside of the lower substrate
`SUB1 that the portions (as located at the upper and
`lower sides and the lefthand side in the Figures), in
`which external connection terminal groups Tg and Td
`(although suffixes are omitted) are present in the com-
`pleted state, may be exposed to the outside. The termi-
`nal groups Tg and Td are named such that the scanning
`line connecting terminal GTM, the video signal circuit
`connecting terminal DTM and their leading lines are
`collected in plurality at the unit of a tape carrier pack-
`age TCP (as shown in FIGS. 20 and 21) on which is
`packaged an integrated circuit chip CHI. The leading
`line from the matrix portion of each group to the exter-
`nal connection terminal portion is inclined toward the
`two ends. This is because the terminals DTM and GTM
`of the display panel PNL are made to match the array
`pitch of the package TCP and the connection terminal
`pitch at each package TCP.
`Between and along he edges of the transparent glass
`plates SUB1 and SUB2, there is formed the seal pattern
`SL for sealing the liquid crystal LC excepting a liquid
`crystal entrance INJ. The seal material is made of an
`epoxy resin, for example. The common transparent
`pixel electrode ITO2 at the side of the upper transparent
`glass substrate SUB2 is connected at the four corners in
`the present embodiment with a leading line INT, which
`is formed at the side of the lower transparent glass sub-
`strate SUB1, in at least one portion by a silver paste
`material AGP. The leading line INT is formed at the
`same fabrication step as that of the later-described gate
`terminal GTM and drain terminal DTM.
`The orientation films ORI1 and ORI2, the transpar-
`ent pixel electrode ITO1, the common transparent pixel
`electrode ITO2, and the individual layers are formed in
`the seal pattern SL. Polarization plates POL1 and
`POL2 are individually formed on the outer surfaces of
`the lower transparent glass substrate SUB1 and the
`upper transparent glass substrate SUB2. The liquid
`crystal LC is filled in the region which is defined by the
`seal pattern SL between the lower orientation film
`ORI1 and the upper orientation film ORI2 for setting
`the orientations of the liquid crystal molecules. The
`lower orientation film ORI1 is formed over a passiv-
`ation film PSVI at the side of the lower transparent
`glass substrate SUB1.
`This liquid crystal display device is assembled: by
`superposing the individual layers at the sides of the
`lower transparent glass substrate SUB1 and the upper
`transparent glass substrate SUB2; by forming the seal
`pattern SL at the side of the substrate SUB2; by super-
`
`LGD_001354
`
`6
`posing the lower transparent glass substrate SUB1 and
`the upper transparent glass substrate SUB2; by injecting
`the liquid crystal LC from the opening INJ of the seal
`member SL to seal the injection entrance INJ with the
`epoxy resin or the like; and by cutting the upper and
`lower substrates.
`
`5
`
`THIN FILM TRANSISTOR TFT
`
`10
`
`If a positive bias is applied to the gate electrode GT,
`the thin film transistor TFT has its channel resistance
`reduced between its source and drain. If the bias is
`
`15
`
`20
`
`25
`
`30
`
`35
`
`45
`
`50
`
`55
`
`reduced to zero, the thin film transistor TFT operates to
`have its channel resistance increased.
`
`The thin film transistor TFT of each pixel is divided
`into two (or plurality) in the pixel so that it is composed
`of thin film transistors (or divided thin film transistors)
`TFT1 and TFT2. These thin film transistors TFTI and
`TFT2 are individually made to have a substantially
`equal size (in the channel length and width). Each of
`these divided thin film transistors TFTI and TFT2 is
`composed mainly of a gate electrode GT, a gate insulat-
`ing film GI, an i-type (i.e., intrinsic type not doped with
`a conductivity type determining impurity) amorphous
`silicon (Si) semiconductor layer AS, and a pair of
`source electrode SD] and drain electrode SD2. Inci-
`dentally, the source and drain are intrinsically deter-
`mined in dependence upon the bias polarity inbetween,
`and this polarity is inverted during the operation in the
`circuit of the present display device. Thus, it should be
`understood that the source and drain are interchanged
`during the operation. In the following description, how-
`ever, one is fixed as the source whereas the other is fixed
`as the drain, for conveniences only.
`GATE ELECTRODE GT
`
`The gate electrode GT is formed to project perpen-
`dicularly (i.e., upward, as viewed in FIGS. 1 and 5)
`from the scanning signal lines GL (or branched in the
`“T-shape”), as shown in detail in FIG. 5 (presenting a
`top plan view showing the second conductive layer g2
`and i-type semiconductor layer AS of FIG. 1 only). The
`gate electrode GT is extended to the regions to be indi-
`vidually formed with the thin film transistors TFT1 and
`TFT2. These thin film transistors TFT1 and TFT2 have
`
`their individual gate electrodes GT integrated (as their
`common gate electrode) to merge into the scanning
`signal line GL. The gate electrode GT is constituted by
`the single level conductive layer g2. The second con-
`ductive layer g2 is formed, for example, by sputtering
`aluminum (Al) in the thickness of about 1,000 to 5,500
`angstroms. On the gate electrode GT, there is provided
`an anodized oxide film AOF of Al.
`
`This gate electrode GT is made so slightly large as to
`cover the semiconductor layer AS completely (as
`viewed upward), as shown in FIGS. 1 and 2 and FIG.
`5. In case, therefore, back lights BL such as fluorescent
`lamps are attached to the bottom of the substrate SUB1,
`this opaque Al gate electrode GT establishes a shadow
`to shield the semiconductor layer AS from the back
`lights,
`thus substantially eliminating the conducting
`phenomenon due to the optical
`irradiation,
`i.e.,
`the
`deterioration of the OFF characteristics of the TFTs.
`
`65
`
`Here, the intrinsic size of the gate electrode GT is given
`the least necessary width (including the positioning
`allowance of the gate electrode GT, the source elec-
`trode SD1 and the drain electrode SD2) for extending
`between the source and drain electrodes SD1 and SD2.
`The depth for determining that channel width W is
`
`LGD_001354
`
`

`
`7
`determined in dependence upon the factor W/L deter-
`mining the mutual conductance gm, i.e., the ratio to the
`distance (i.e., the channel length) L between the source
`and drain electrodes SD1 and SD2. The size of the gate
`electrode GT in the present liquid crystal display device
`is naturally made larger than the aforementioned intrin-
`sic size.
`
`SCANNING SIGNAL LINE GL
`
`The scanning signal line GL is constituted by the
`second conductive film g2. The second conductive film
`g2 of the scanning signal line GL is formed at the same
`step as and integrally with the second conductive film
`g2 of the gate electrode GT. Moreover, the scanning
`signal line GL is also formed thereon with the anodized
`oxide film AOF of Al.
`
`GATE INSULATING FILM GT
`
`The insulating film GI is used as the individual gate
`insulating films of the thin film transistors TFT1 and
`TFT2. The insulating film GI is formed over the gate
`electrode GT and the scanning signal line GL. The
`insulating film G1 is formed of, for example, a silicon
`nitride film prepared by the plasma CVD, to have a
`thickness of 1,200 to 2,700 angstroms (e.g., about 2,000
`angstroms in the present liquid crystal display device).
`The gate insulating film G1 is formed to enclose the
`entirety of the matrix portion AR, as shown in FIG. 18,
`and to have its peripheral portion removed to expose
`the external connection terminals DTM and GTM to
`the outside.
`
`i-TYPE SEMICONDUCTOR LAYER AS
`
`The i-type semiconductor layer AS is used as the
`individual channel forming regions of the thin film tran-
`sistors TFT1 and TFT2 divided into a plurality of parts,
`as shown in FIG. 5. The i-type semiconductor layer AS
`is formed of an amorphous silicon film or polycrystal-
`line silicon film to have a thickness of about 200 to 2,200
`angstroms (e.g., about 2,000 angstroms in the present
`liquid crystal display device).
`This i-type semiconductor layer AS is formed subse-
`quent to the formation of the Si3N4 gate insulating film
`GI by changing the components of supply gases but by
`using the common plasma CVD system such that it is
`not exposed from the system to the outside. On the
`other hand, an N(+)-type layer d0 (shown in FIG. 2)
`doped with 2.5% of phosphor (P) for the ohmic contact
`is likewise formed subsequently to have a thickness of
`about 200 to 500 angstroms (e.g., about 300 angstroms in
`the present liquid crystal display device). After this, the
`lower substrate SUBI is taken out of the CVD system,
`and the N(+)-type layer d0 and the i-type AS are pat-
`terned into independent islands by the photographic
`technology, as shown FIGS. 1 and 2 and FIG. 5.
`The i-type semiconductor layer As is also formed
`between the intersecting portions (or crossover por-
`tions) of the scanning signal line GL and the video
`signal line DL, as shown in FIGS. 1 and 5. This cross-
`over i-type semiconductor layer As is formed to reduce
`the short-circuiting between the scanning signal line
`GL and the video signal line DL at the intersecting
`portion.
`
`TRANSPARENT PIXEL ELECTRODE ITO1
`
`The transparent pixel electrode ITO1 constitutes one
`of the parts of a pixel electrode of a liquid crystal dis-
`play.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`LGD_001355
`
`5,432,626
`
`8
`The transparent pixel electrode ITO1 is connected
`with both the source electrode SD1 of the thin film
`transistor TFT1 and the source electrode SD1 of the
`thin film transistor TFT2. Even if, therefore, one of the
`thin film transistors TFT1 and TFT2 become defective,
`a suitable portion may be cut by a laser beam in case the
`defect invites an adverse action. Otherwise, the situa-
`tion may be left as it is because the other thin film tran-
`sistor is normally operating. Incidentally, both the two
`thin film transistors TFT1 and TFT2 scarcely become
`defective, and the probability of the point defect or line
`defect can be drastically reduced by that redundant
`system. The transparent pixel electrode ITOI is formed
`of a first conductive film d1, which is made of a trans-
`parent conductive film (of Indium-Tin-Oxide, i.e., ITO
`or NESA film) to have a thickness of 1,000 to 2,000
`angstroms (e.g., about 1,400 angstroms in the present
`liquid crystal display device).
`SOURCE ELECTRODE SDI AND DRAIN
`ELECTRODE SD2
`
`The individual source electrodes SD1 and drain elec-
`trodes SD2 of the divided thin film transistors TFT1
`and TFT2 are formed over the semiconductor layer AS
`and separately from each other, as shown in FIGS. 1
`and 2 and FIG. 6 (presenting a top plan view showing
`the layers d1 to d3 of FIG. 1 only).
`Each of the source electrode SDI and the drain elec-
`trode SD2 is formed by overlaying a second conductive
`film d2 and a third conductive film d3 sequentially from
`the lower side contacting with the N(+)-type semicon-
`ductor layer d0. These second conductive film d2 and
`third conductive film d3 of the source electrode SD1
`are formed at the same fabrication step as those of the
`drain electrode SD2.
`
`The second conductive film d2 is formed of a sput-
`tered chromium (Cr) film to have a thickness of 500 to
`1,000 angstroms (e.g., about 600 angstroms in the pres-
`ent liquid crystal display device). The Cr film is formed
`to have a thickness no more than 2,0()0 angstroms be-
`cause it establishe