(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2003/0058229 A1
`(43) Pub. Date:
`Mar. 27, 2003
`Kawabe et al.
`
`US 20030058229A1
`
`(54) MATRIX-TYPE DISPLAY DEVICE
`
`Publication Classi?cation
`
`(76) Inventors: Kazuyoshi Kawabe, FujisaWa (JP);
`Junichi Hirakata, Chiba (JP)
`
`.... .. G09G 5/00
`(51) Int. Cl.7 .
`(52) US. Cl. ............................................................ .. 345/204
`
`Correspondence Address:
`
`(57)
`
`ABSTRACT
`
`ANTONELLI TERRY STOUT AND KRAUS
`SUITE 1800
`1300 NORTH SEVENTEENTH STREET
`ARLINGTON VA 22209
`’
`
`(21) APPL No.
`
`(22) Filed;
`
`10/200 536
`’
`Ju]_ 23, 2002
`
`(30)
`
`Foreign Application Priority Data
`
`Jul. 23, 2001 (JP) .................................... .. 2001-220832
`Aug. 28, 2001 (JP) .................................... .. 2001-257128
`
`.
`.
`.
`.
`.
`A matrix-type display device includes a data generating
`circuit 102 for multiple scans for inserting blanking data to
`image data for one frame period of an image, and a timing
`controlling circuit 103 for multiple scans for generating
`clocks used by a gate line drive circuit 104 for scanning lines
`of a display element array 107 such that the image data and
`the blanking data can be displayed in one frame period.
`Here, the gate line drive circuit 104 simultaneously scans
`multiple lines adjacent to each other as a bundle. According
`to this con?guration, the larger and more complicated con
`struction can be suppressed, Which can also suppress the
`image deterioration due to blurred moving picture.
`
`101
`
`/
`
`>02
`
`a 4
`
`E'QAIII'EEATING
`DATA GENERATING
`WAGE SIGNAL
`SOURCE
`—’ ACA'SETHJDTLEQSEANS —’ CIRCUIT FOR
`MULTIPLESCANS
`
`/
`
`DRAIN LINE DRIVING CIRCUIT
`
`l
`
`IIIIIIIIIIIIII
`
`112
`i
`
`109
`
`‘:8: _
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`111
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`107
`108
`
`SONY 1007
`Page 1
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 1 0f 50
`
`US 2003/0058229 A1
`
`
`
`)1 IMAGE SIGNAL SOURCE
`
`
`Page 2
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 2 0f 50
`
`US 2003/0058229 A1
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`Page 3
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`

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`Patent Application Publication Mar. 27, 2003 Sheet 3 0f 50
`
`US 2003/0058229 A1
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`FIGB
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`304
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`Page 4
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 4 0f 50
`
`US 2003/0058229 A1
`
`405
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`406
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`409
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`TIME
`
`
`Page 5
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 5 0f 50
`
`US 2003/0058229 A1
`
`FIG.5
`
`ANALOG
`SWITCH
`
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`
`Page 6
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`

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`Patent Application Publication Mar. 27, 2003 Sheet 6 0f 50
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`US 2003/0058229 A1
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`Page 7
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`

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`Patent Application Publication Mar. 27, 2003 Sheet 7 0f 50
`
`US 2003/0058229 A1
`
`FIG.7
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`Page 8
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 8 0f 50
`
`US 2003/0058229 A1
`
`801
`
`DATA GENERATING
`—> CIRCUIT
`MULTIPL
`ANS
`/
`102
`
`60HZ
`
`TIM
`TING
`GEN
`CIRCUIT FOR
`MULTIPLE SCANS
`I)
`103
`
`
`Page 9
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 9 0f 50
`
`US 2003/0058229 A1
`
`FIG.9A
`
`901
`
`60HZ
`
`102
`
`FIG.9B
`
`TIMING
`_____, GENERATING
`CIRCUIT FOR
`MULTIPLE SCANS
`
`FIG.1O
`
`NAME
`VGA
`XGA
`SXGA
`UXGA
`WVGA
`WXGA
`WUXGA
`
`HORIZONTAL
`640
`1024
`1280
`1600
`800
`1280
`1920
`
`VERTICAL
`480
`768
`1024
`1200
`480
`768
`1200
`
`ASPECT RATIO
`4:3
`4:3
`5:4
`4:3
`5:3
`5:3
`8:5
`
`
`Page 10
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 10 0f 50 US 2003/0058229 A1
`
`FIG.1 1
`
`4801
`480p
`1080i
`720p
`1080p
`
`16:9 or 4:3
`16:9
`1619
`16:9
`16:9
`
`FIG.12A FIG.12B FIG.12C FIG.12D
`
`VALID DISPLAY
`AREA
`
`
`/7/////////? 7m VALID DISPLAY ; VALID DISPLAY; VALID DISPLAY
`
`
`AREA
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`,1
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`WWI/[WW W///////A ........................................................................... ..
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`FIG.13A FIG.13B F|G.13C FIG.13D
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`Page 11
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 11 0f 50
`
`US 2003/0058229 A1
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`Page 12
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`
`Page 12
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 12 0f 50 US 2003/0058229 Al
`
`F IG.1 5
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`Page 13
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 13 0f 50 US 2003/0058229 A1
`
`V MM/MMM
`HEADER
`VERTICAL RETRACE PERIOD
`I
`[ff/‘77
`[I
`8 / E i A 6
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`
`IMAGE DATA
`
`25 %
`
`CONTROL PARAMETERS
`
`NUMBER OF SYNCHRONOUS WRITING LINES
`
`NUMBER OF INTERLACE LINES
`
`VALUES
`
`1,2,3,4...
`
`1,2,3,4...
`
`IMPULSED BLANKING
`
`1/2,1/3,2/3,1/4...
`
`COEFFICIENT OF FAST RESPONSE LIQUID CRYSTAL FILTER
`
`1.0,1.5,2.0...
`
`GRAY-SCALE REFERENCE VOLTAGE GROUP
`
`Vh[9:O],Vi[9:0]
`
`ASPECT RATIO/WIDE RATIO
`
`FOCUS
`
`FOCUS POSITION
`
`Enable, Disable
`
`Enable, Disable
`
`(0,0)-(640,480)
`
`
`Page 14
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 14 0f 50 US 2003/0058229 A1
`
`F|G.1 8
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`Page 15
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`

`

`Patent Application Publication Mar. 27, 2003 Sheet 15 0f 50 US 2003/0058229 A1
`
`FIG.19A
`
`FIG.19B
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`VALID DISPLAY AREA
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`FIG .20
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`CONTROL PARAMETERS
`
`VALUES
`
`TUBE CURRENT
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`LIGHTING DUTY
`
`LIGHTING PHASE
`
`SHUTOFF LAMP
`
`x1,x2,x3,x4...
`
`1/2,1/3,2/3...
`
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`
`Page 16
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 16 0f 50 US 2003/0058229 A1
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`Page 17
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 17 0f 50
`
`US 2003/0058229 A1
`
`FIG.22
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`2201
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`TIME
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`Page 18
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`
`Page 18
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`

`

`Patent Application Publication Mar. 27, 2003 Sheet 18 0f 50 US 2003/0058229 A1
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`F|G.23
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`

`

`Patent Application Publication Mar. 27, 2003 Sheet 19 0f 50 US 2003/0058229 A1
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`i
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`VALUES
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`
`DETERMINING THRESHOLD
`
`LOW, MIDDLE, HIGH
`
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`
`EVERY LINE, EVERY FRAME
`
`
`Page 20
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 20 0f 50
`
`US 2003/0058229 A1
`
`FIG.26
`
`2602
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`DRAIN LINE DRIVE CIRCUIT
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`BACKLIGHTINGDRIVECIRCUIT
`
`
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`
`Page 21
`
`
`Page 21
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 21 0f 50
`
`US 2003/0058229 A1
`
`FIG.27
`
`2701
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`Page 22
`
`
`Page 22
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 22 0f 50
`
`US 2003/0058229 A1
`
`FIG.28
`
`
`
`CONTROL PARAMETERS
`VALUES
`
`
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`
`LOWER INVALID AREA
`
`672~768...
`
`FIG.29
`
`2907
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`
`2908
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`_
`DEVICE
`
`Page 23
`
`
`Page 23
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 23 0f 50
`
`US 2003/0058229 A1
`
`FIG.3O
`
`2901
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`FIG.31
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`
`
`Page 24
`
`
`Page 24
`
`
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 24 0f 50
`
`US 2003/0058229 A1
`
`FIG.32A
`
`3201
`
`DATA GENERATING
`—> CIRCUIT FOR
`MULTIPLE SCANS
`
`————>
`
`102
`
`
`
`FIGBZB
`
`103
`
`TIMING
`GENERATING
`CIRCUIT FOR
`MULTIPLE SCANS
`
`Page 25
`
`
`Page 25
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 25 0f 50
`
`US 2003/0058229 A1
`
`FIG.33
`
`3302
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`
`V \
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`Page 26
`
`
`Page 26
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 26 0f 50
`
`US 2003/0058229 A1
`
`FIG.35
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`3501
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`Page 27
`
`
`Page 27
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 27 0f 50
`
`US 2003/0058229 A1
`
`FIG. 36
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`3601
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`Page 28
`
`
`Page 28
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 28 0f 50
`
`US 2003/0058229 A1
`
`FIG.37
`
`
`
`Page 29
`
`
`Page 29
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`

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`Patent Application Publication Mar. 27, 2003 Sheet 29 0f 50
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`US 2003/0058229 A1
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`FIG.4O
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`Page 30
`
`
`Page 30
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 30 0f 50
`
`US 2003/0058229 A1
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`”0
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`Page 31
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`

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`Patent Application Publication Mar. 27, 2003 Sheet 31 0f 50
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`US 2003/0058229 A1
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`FIG.46
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`Page 32
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`Page 32
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`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 32 0f 50
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`US 2003/0058229 A1
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`FIG.48
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`Page 33
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`
`Page 33
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`

`Patent Application Publication Mar. 27, 2003 Sheet 33 0f 50
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`US 2003/0058229 A1
`
`FIG.50
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`Page 34
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`Page 34
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`

`

`Patent Application Publication Mar. 27, 2003 Sheet 34 0f 50
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`US 2003/0058229 A1
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`F:|(Ei.5522
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`Page 35
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`Page 35
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`

`

`Patent Application Publication Mar. 27, 2003 Sheet 35 0f 50
`
`US 2003/0058229 A1
`
`FIG.54
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`BLACK DISPLAY
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`60Hz
`
`Page 36
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`Page 36
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`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 36 0f 50
`
`US 2003/0058229 A1
`
`FIG.56
`
`
`
`DOT INVERSION
`
`EVERY-TWO—LINE INVERSION
`
`
`
`LINE COMMON
`INVERSION
`
`EVERY-TWO-LINE INVERSION
`
`Page 37
`
`
`Page 37
`
`

`

`
`
`
`
` GENERALRESPONSELIQUIDCRYSTAL LIGHTI N G LIGHTING—---.~--»-------.-----~-m-
`
`
`
`FASTRESPONSELIQUIDCRYSTAL
`
`RESPONSE DELAY OF LIQUID CRYSTAL
`7808
`7810
`7806 7807
`
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`WRITING
`..
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`PEAK LIGHTING
`
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`
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`
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`........................................
`
`
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`.......................................
`
`CONTROL
`
`SHUTOFF
`'
`'
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`"
`”
`7809
`ALL
`ALL
`ALL
`ALL
`SIX-LAMPS
`SIX—LAMPS
`SIX-LAMPS
`SIX-LAMPS
`LIGHT ON
`LIGHT ON
`LIGHT ON
`LIGHT ON
`
`Patent Application Publication Mar. 27, 2003 Sheet 37 0f 50
`
`US 2003/0058229 A1
`
`FIG.58
`
`7801
`
`7802
`
`7803
`
`7804
`
`v
`
`
`
`I
`
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`
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`
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`
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`
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`WRITING
`SCANNING
`
`BLACKE""‘i"
`
`
`PEAK LIGHTING
`.
`................................ ,
`FULL-TIME
`
`LIGHTING L|GHT|NG ................................................
`
`CONTROL
`
`7319 ALL
`ALL
`ALL
`ALL
`SIX-LAMPS
`SIX-LAMPS
`SIX-LAMPS
`SIX-LAMPS
`LIGHT ON
`LIGHT ON
`LIGHT ON
`LIGHT ON
`
`SHUTOFF
`
`Page 38
`
`
`Page 38
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 38 0f 50
`
`US 2003/0058229 A1
`
`FIG.59
`
`WRITING
`I: (n O>z E 2 C)
`
`_
`
`...............
`
`_
`
`’_
`
`.
`
`L.............
`
`'0 rn> X l— 5 I j Z G?
`
` GRAY-SCALE
`
`FULL—TIME
`LIGHTING LIGHTING ................................................... .
`
`.........................................................................................................................
`
`CONTROL
`
`/
`
`
`SHUTOFF
`
`7809
`
`g
`THREE-
`LAMPS
`LIGHT ON
`
`A
`THREE—
`LAMPS
`LIGHT ON
`
`
`
`A
`,3
`.4
`
`THREE—
`THREE—
`THREE-
`LAMPS
`LAMPS
`LAMPS
`LIGHT ON
`LIGHT ON
`LIGHT ON
`
`(C; RESPONSE DELAY OF LIQUID CRYSTAL
`7908
`.
`GRAY-SCALE ///
`‘4
`f.............
`
`7912 /
`7907
`Igl§lumfie
`
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`............. " ml.
`A
`
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`
`FULL-TIME
`LIGHTING LIGHTING
`CONTROL
`
`
`., .............................................................................................................................................................
`
`..................................
`.
`........................................................................
`I ...............................
`
`
`SHUTOFF;
`I:
`A
`A
`,3
`A
`7810 THREE-
`THREE-
`THREE-
`THREE-
`THREE-
`LAMPS
`LAMPS
`LAMPS
`LAMPS
`LAMPS
`LIGHT ON
`LIGHT ON
`LIGHT ON
`LIGHT ON
`LIGHT ON
`
`Page 39
`
`UPPERHAL
`
`F O
`
`WERHAL4
`
`
`Page 39
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 39 0f 50
`
`US 2003/0058229 A1
`
`
`
`FIG.6OD
`
`RESPONSE DELAY
`OF LIQUID CRYSTAL
`(i,
`3? y ,
`
`8005
`8006
`
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`
`y I ........................4/
`
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`
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`LIGHT %8010........
`I
`// '7,
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`ESQ :::::;j;.;..._
`iii/Higi:11::;;;;;;;.;;;;;;;j;;;1j;;;;..ii;j;;:;:
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`/
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`SIX-LAMPS
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`ALL
`SIX-LAMPS
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`ALL
`EIX-LAMPS
`IGHT ON
`
`ALL
`SIX-LAMPS
`LIGHT ON
`
`Page 40
`
`
`Page 40
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 40 0f 50
`
`US 2003/0058229 A1
`
`FIG.61
`
`
`
`
`—_
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`240 X 60:14400 LINES/SEC.
`
`348 X 120:46080 LINES/SEC.
`
`FIG.63
`
`HEADER SETTINGS
`
`SETTING VALUES
`
`
`
`
`
`
`
`
`
`BLACK DISPLAY PATTERN
`
`FULL-SCREEN. VERTICAL.
`HORIZONTAL, CHECKER, etc.
`
`
`
`
`
`
`
`
`
`Page 41
`
`
`Page 41
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 41 0f 50
`
`US 2003/0058229 A1
`
`FIG.64
`
`HEADER SETTINGS
`
`SETTING VALUES
`
`NUMBER OS SCANS
`
`1,2,3,4,...,n etc
`
`1,2,3.4,...,n etc
`
`SYNCHRONOUS WRITING LINES
`
`
`
`
`
`
`
`INTERLACE LINES
`
`1.2,3,4,...,n etc
`
`NUMBER OF TIMES OF BLACK DISPLAY
`
`1,2,3,4,...,n BIC
`
`FULL—SCREEN, VERTICAL, HORIZONTAL,
`
`CHECKER, etc.
`BLACK DISPLAY PATTERN
`
`
`
`
`
`
`
`POLARITY INVERSION PERIOD
`1, 2, 3, 4 LINES, etc.
`
`
`
`EDGE EMPHASIS, ANTI-ALIASING, etc.
`
`
`
`
`
` HIGH, LOW, etc.
`
`
`
`
`
`
`
`DOT INVERSION, COMMON INVERSION, etc.
`
`Page 42
`
`
`Page 42
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 42 0f 50
`
`US 2003/0058229 A1
`
`
`
`oonEoé40$me5L$5128:28me
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`Page 43
`
`
`Page 43
`
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 43 0f 50
`
`US 2003/0058229 A1
`
`
`
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`Page 44
`
`
`Page 44
`
`

`

`
`
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`Patent Application Publication Mar. 27, 2003 Sheet 44 0f 50
`
`US 2003/0058229 A1
`
`
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`Page 45
`
`
`Page 45
`
`
`
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 45 0f 50
`
`US 2003/0058229 A1
`
`
`3:10:5539698:99
`EEG:Bmamwmwmm20.58%
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`Page 46
`
`
`
`
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 46 0f 50
`
`US 2003/0058229 A1
`
`FIG.69
`
`8502
`
`7301
`
`7304
`
`7305
`
`7302
`
`/\/
`
`
`DATA
`HEADER CREATING
`
`TRANSMITTER
`
`
`
`
`CIRCUIT
`
`
`
`VIDEOSIGNALDETERMININGCIRCUIT
`
` DATA GENERATING
`
`FORMATTER
`
`
`CIRCUIT FOR
`SCANNING
`
`........................................................................................................................................................................................................................................
`
`Page 47
`
`
`Page 47
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 47 0f 50
`
`US 2003/0058229 A1
`
`F:|(Ei.77()
`
`8503
`
`HEADER
`
`ANALYZING
`
`
` RECEIVER
`CIRCUIT
`
`
`7317
`
`7416
`
`7405 I
`;
`
`DRAIN LINE DRIVE CIRCUIT
`
`
`
`
`CIRCUIT
`
`
`
`CIRCUIT
`
`GATELINEDRIVE
`
`LIQUID CRYSTAL DISPLAY ELEMENT ARRAY
`
`g 7404
`
`8504
`
`Page 48
`
`
`Page 48
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 48 0f 50
`
`US 2003/0058229 A1
`
`FIG.71
`
`ONE FRAME PERIOD
`
`FIRST SCANNING (IMAGES)
`SECOND SCANNING (BLACK BLANKING)
`fi—kfif—A—fi
`ONEHOREONTALPEHOD
`
`
`
`7104
`
`LINE
`
`1,2
`
`3,4
`
`5,6. -- n,n+1 n+2,n+3 - - -
`
`RESPONSE DELAY
`
`LIGHTING PERIOD
`
`"um
`
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`
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`x..........................................................
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`PEAK
`BRmHTNESS
`
`V
`
`RESPONSE DELAY LIGHTING PERIOD
`(—>(————->
`
`Page 49
`
`
`Page 49
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 49 0f 50
`
`US 2003/0058229 A1
`
`FIG.72
`
`ONE FRAME PERIOD
`
`FIRST SCANNING (IMAGES)
`
`SECOND SCANNING (BLACK BLANKING)
`
`ONE HORIZONTAL PERIOD
`
`
`
`
`
`GENERAL
`RESPONSE
`
`LINE
`
`1,2.
`
`3,4
`
`5,67-
`
`-n,n+1 n+2,r.1.+3 - - -
`
`PEAK
`BRIGHTNESS
`
`RESPONSE DELAY
`
`LIGHTING PERIOD
`
`Page 50
`
`
`Page 50
`
`
`
`

`

`Patent Application Publication Mar. 27, 2003 Sheet 50 0f 50
`
`US 2003/0058229 A1
`
`FIG.73A
`
`FIG.73B
`
`FIG.73C
`
`% % w)
`240 % \_7:8[
`768[
`1 $2;
`
`‘
`
`60Hz
`
`’
`
`‘
`
`60Hz
`
`’
`
`‘
`
`60Hz
`
`’
`
`240 m i 768
`LINES §
`LINES
`% a
`
`60Hz
`
`
`
`240 x 60:14400 LINES/SEC.
`
`348 x 120246080 LINES/SEC.
`
`Page 51
`
`
`Page 51
`
`

`

`US 2003/0058229 A1
`
`Mar. 27, 2003
`
`MATRIX-TYPE DISPLAY DEVICE
`
`BACKGROUND OF THE INVENTION
`
`[0001]
`
`1. Field of the Invention
`
`[0002] The present invention relates to a matrix-type dis-
`play device having display elements such as amorphous
`silicon liquid crystal, polysilicon liquid crystal, light emit-
`ting diode or organic EL, and particularly to a display device
`for performing blanking processing.
`
`[0003]
`
`2. Description of the Related Art
`
`Japanese Unexamined Patent Application Publica-
`[0004]
`tion No. 11-109921 is a technology of the related art.
`According to the technology of the related art, one liquid
`crystal display panel is divided into tow upper and lower
`pixel arrays. Data line drive circuits are provided to the
`divided pixel arrays, respectively. One gate line for each of
`the upper and lower pixel arrays, that is, a total of two gate
`lines for the upper and the lower gate lines are selected. Two
`of the upper and lower divided display areas are dual-
`scanned by the respective drive circuits. During the dual
`scanning, a blanking image (black image) is inserted by
`changing the upper and lower phases within one frame
`period. In other words, the one frame period includes a video
`display period and the blanking period, which can reduce an
`image-holding period. Therefore, a liquid crystal display can
`obtain a moving image display performance similar to that
`of a cathode ray tube.
`
`[0005] However, according to the technology of the
`related art, the liquid crystal display panel is divided into the
`upper and the lower portions, each of which has a data line
`drive circuit. Therefore, the costs for parts and manufactur-
`ing are increased. Furthermore, the construction becomes
`larger and more complicated. As a result, the costs on the
`larger screen and higher definition are more increased than
`those for the general panel. The liquid crystal display panel
`according to the technology of the related art has a dramati-
`cally improved moving picture display characteristic. How-
`ever, the still picture display characteristic is the same for a
`still picture typified by a desktop movie by a personal
`computer, for example. In other words, the liquid crystal
`display panel according to the technology of the related art
`is overdesigned for a liquid crystal panel, which has been
`widely spread for the application for a monitor for a note-
`book personal computer,
`for example. Thus,
`the liquid
`crystal display panel is limited as a high-end type for the
`multimedia applications. Thus, the efficiency of the mass
`production is reduced when a variety of the products are
`produced in large quantities.
`
`SUMMARY OF THE INVENTION
`
`[0006] Accordingly, it is an object of the present invention
`to provide a display device, which can suppress the larger
`and more complicated construction and which can suppress
`the deterioration in image quality due to blurred moving
`images.
`
`In order to achieve the object, according to an
`[0007]
`aspect of the present invention, blanking data is inserted to
`video data for one frame period and line scanning of a
`display panel is controlled such that the video data and the
`blanking data are displayed by an arbitrary display element
`in one frame period. Preferably, adjacent n lines are selected
`
`the same time, and gradation voltage in
`as a bundle at
`accordance with the data is applied thereto. Next, those n
`lines are skipped and the next adjacent n lines are selected
`at the same time, and gradation voltage in accordance with
`the data is applied thereto. Here, n is 2, 3, 4, 5, .
`.
`. (a natural
`number larger than 1). Here, according to the present inven-
`tion, a number of adjacent multiple lines and a number of
`interlaced lines do not have to be the same. Also, adjacent n
`lines can be selected at the same time. However, it is also
`possible to change the select timing (in other words, the start
`timing for scanning) such that the scanning period of each
`line constituting n lines partially overlaps each other.
`
`there is an
`invention,
`[0008] According to the present
`advantage that the deterioration in image quality due to
`blurred moving image can be suppressed by inserting blank-
`ing data to image data. Furthermore, according to the present
`invention, the increase in the number of drain drivers can be
`suppressed by selecting a line in which image data and
`blanking data are displayed in one frame period, which
`produces an advantage that the larger and more complicated
`construction can be suppressed.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0009] FIG. 1 is a diagram showing the configuration of
`a display device according to a first embodiment of the
`present invention;
`
`[0010] FIG. 2 is a diagram showing the configuration of
`a display element array according to the first embodiment of
`the present invention;
`
`[0011] FIG. 3 is a waveform diagram of a gate line drive
`signal for two-line synchronous writing and two-line inter-
`lace scanning according to the first embodiment of the
`present invention;
`
`[0012] FIG. 4 is an optical response waveform diagram of
`each signal line drive waveform and a display element for
`two-line synchronous writing and two-line interlace scan-
`ning according to the first embodiment of the present
`invention;
`
`[0013] FIG. 5 is a diagram showing the configuration of
`a gradation voltage generating circuit according to the first
`embodiment of the present invention;
`
`[0014] FIG. 6 is a waveform diagram of a gate line drive
`signal for scanning by four-line synchronous writing and
`four-line interlace scanning according to the first embodi-
`ment of the present invention;
`
`[0015] FIG. 7 is an optical response waveform diagram of
`each signal line drive waveform and a display element for
`scanning by four-line synchronous writing and four-line
`interlace scanning according to the first embodiment of the
`present invention;
`
`[0016] FIG. 8A is a conceptual diagram showing a video
`data generating process in a data generating circuit for
`multiple scans by two-line synchronous writing and two-line
`interlace scanning according to the first embodiment of the
`present invention;
`
`[0017] FIG. 8B is a conceptual diagram showing a video
`data generating process in a data generating circuit for
`multiple scans by two-line synchronous writing and two-line
`interlace scanning according to the first embodiment of the
`present invention;
`
`Page 52
`
`
`Page 52
`
`

`

`US 2003/0058229 A1
`
`Mar. 27, 2003
`
`[0018] FIG. 9A is a conceptual diagram showing a video
`data generating process in a data generating circuit for
`multiple scans by four-line synchronous writing and four-
`line interlace scanning according to the first embodiment of
`the present invention;
`
`[0019] FIG. 9B is a conceptual diagram showing a video
`data generating process in a data generating circuit for
`multiple scans by four-line synchronous writing and four-
`line interlace scanning according to the first embodiment of
`the present invention;
`
`a diagram showing relationships
`[0020] FIG. 10 is
`between resolutions and aspect ratios of a display element
`array;
`
`[0021] FIG. 11 is a relational diagram of video formats in
`digital broadcasting;
`
`[0022] FIG. 12A is a schematic diagram for a case when
`a wide image is displayed in a non-wide type of display
`element array, wherein an aspect ratio of wide image is
`modified and displayed therein;
`
`[0023] FIG. 12B is a schematic diagram when a wide
`image is displayed in a non-wide type of display element
`array, wherein the horizontal resolution of display element
`array is fully used to keep the aspect ratio of the wide image;
`
`[0024] FIG. 12C is a schematic diagram when a wide
`image is displayed in a non-wide type of display element
`array, wherein the resolution of display element array and
`the resolution of a wide image are the same;
`
`[0025] FIG. 12D is a schematic diagram when a wide
`image is displayed in a non-wide type of display element
`array, wherein the vertical resolution of display element
`array is fully used to keep the aspect ratio of the wide image;
`
`[0026] FIG. 13A is a schematic diagram for a case when
`awide image is displayed in a wide type of display element
`array, or a case when a non-wide image is stretched in the
`horizontal direction and displayed;
`
`[0027] FIG. 13B is a schematic diagram for a case when
`a non-wide image is displayed in a wide type of display
`element array, wherein the vertical resolution of the display
`element array is fully used;
`
`[0028] FIG. 13C is a schematic diagram for a case when
`a non-wide image is displayed in a wide type of display
`element array, wherein the resolution of the display element
`array and the resolution of non-wide image is the same;
`
`[0029] FIG. 13D is a schematic diagram for a case when
`a non-wide image is displayed in a wide type of display
`element array, wherein the horizontal resolution of the
`display element array is fully used;
`
`[0030] FIG. 14 is a relational diagram for combinations
`between display element arrays and digital broadcasting
`video formats;
`
`[0031] FIG. 15 is a waveform diagram of a gate line drive
`signal, which simplifies invalid area scanning according to
`the first embodiment of the present invention;
`
`[0032] FIG. 16 is a schematic diagram of a video format
`having control information according to the first embodi-
`ment of the present invention;
`
`[0033] FIG. 17 is an explanatory diagram showing a
`specific example of control parameters and the values
`according to the first embodiment of the present invention;
`
`[0034] FIG. 18 is a timing chart for gate select pulses
`(gate line drive signals) and backlighting blinking for two-
`line synchronous writing and two-line interlace scanning
`according to the second embodiment of the present inven-
`tion;
`
`[0035] FIG. 19A is a schematic diagram showing an
`invalid display area according to the second embodiment of
`the present invention;
`
`[0036] FIG. 19B is a schematic diagram showing an
`arrangement of a lighting lamp according to the second
`embodiment of the present invention;
`
`[0037] FIG. 20 is an explanatory diagram showing spe-
`cific examples of control parameter and the values according
`to the second embodiment of the present invention;
`
`[0038] FIG. 21 is a waveform diagram for a gate line drive
`signal when scanning is performed line by line according to
`a third embodiment of the present invention;
`
`[0039] FIG. 22 is a diagram showing a signal line drive
`waveform and a liquid crystal optical response waveform
`when scanning is performed line by line according to the
`third embodiment of the present invention;
`
`[0040] FIG. 23 is a waveform diagram of a gate line drive
`signal for two-line synchronous writing and two-line inter-
`lace scanning according to the third embodiment of the
`present invention;
`
`[0041] FIG. 24 is a diagram showing a signal line drive
`waveform and a liquid crystal optical response waveform for
`two-line synchronous writing and two-line interlace scan-
`ning according to the third embodiment of the present
`invention;
`
`[0042] FIG. 25 is an explanatory diagram showing spe-
`cific examples of control parameter and the values according
`to the third embodiment of the present invention;
`
`[0043] FIG. 26 is a diagram showing the configuration of
`a display device according to the fourth embodiment of the
`present invention;
`
`[0044] FIG. 27 is a waveform diagram of a gate line drive
`signal according to the fourth embodiment of the present
`invention;
`
`[0045] FIG. 28 is an explanatory diagram showing spe-
`cific examples of control parameter and the values according
`to the fourth embodiment of the present invention;
`
`[0046] FIG. 29 is a diagram showing the configuration of
`a drain line drive circuit (drain driver IC) according to the
`fifth embodiment of the present invention;
`
`[0047] FIG. 30 is a diagram showing the configuration of
`a drain line drive circuit (drain driver IC) according to the
`fifth embodiment of the present invention;
`
`[0048] FIG. 31 is a diagram showing the configuration of
`another drain line drive circuit (drain driver IC) according to
`the fifth embodiment of the present invention;
`
`[0049] FIG. 32A is a conceptual diagram showing a video
`data generating process in a data generating circuit for
`
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`US 2003/0058229 A1
`
`Mar. 27, 2003
`
`multiple scans for rapid data transfer according to the fifth
`embodiment of the present invention;
`
`[0050] FIG. 32B is conceptual diagrams each showing a
`video data generating process in a timing generating circuit
`for multiple scans for rapid data transfer according to the
`fifth embodiment of the present invention;
`
`[0051] FIG. 33 is a configuration diagram of a main
`portion of a display device according to the fifth embodi-
`ment of the present invention;
`
`[0052] FIG. 34 is an explanatory diagram showing spe-
`cific examples of control parameter and the values according
`to the fifth embodiment of the present invention;
`
`[0053] FIG. 35 is a waveform diagram of a gate line drive
`signal according to the sixth embodiment of the present
`invention;
`
`[0054] FIG. 36 is a diagram of a waveform of each drive
`signal line and a waveform of an optical response of a pixel
`included in serial lines according to the sixth embodiment of
`the present invention;
`
`[0055] FIG. 37 is an explanatory diagram showing the
`configuration of scanning screens, into which a black dis-
`play is inserted alternately in screen scanning at frame rate
`120 Hz for
`two-line synchronous writing and two-line
`interlace scanning according to a first example of the present
`invention;
`
`[0056] FIG. 38 is an explanatory diagram showing the
`configuration of scanning screens, into which a black dis-
`play is inserted once in screen scanning at frame rate 180 Hz
`for scanning by three-line synchronous writing and three-
`line interlace scanning according to the second example of
`the present invention;
`
`[0057] FIG. 39 is an explanatory diagram showing the
`configuration of scanning screens, into which a black dis-
`play is inserted twice in screen scanning at frame rate 180
`Hz for scanning by three-line synchronous writing and
`three-line interlace scanning according to the second
`example of the present invention;
`
`[0058] FIG. 40 is an explanatory diagram showing the
`configuration of scanning screens, into which a black dis-