EXHIBIT
`2008
`
`Samsung Exhibit 1059
`Samsung v. Affinity
`IPR2014-01181
`Page 00001
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`

`
`Universal Serial Bus
`Specification
`
`Compaq
`
`Hewlett-Packard
`
`Intel
`
`Lucent
`
`Microsoft
`
`NEC
`
`Philips
`
`Revision 2.0
`
`April 27, 2000
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`Page 00002
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`

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`Universal Serial Bus Specification Revision 2.0
`
`Scope of this Revision
`The 2.0 revision of the specification is intended for product design. Every attempt has been made to ensure a
`consistent and implementable specification. Implementations should ensure compliance with this revision.
`
`Revision History
`
`Revision
`
`Issue Date
`
`Comments
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`0.7
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`0.8
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`0.9
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`0.99
`
`November 11, 1994
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`Supersedes 0.6e.
`
`December 30, 1994
`
`Revisions to Chapters 3-8, 10, and 11. Added
`appendixes.
`
`April 13, 1995
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`Revisions to all the chapters.
`
`August 25, 1995
`
`Revisions to all the chapters.
`
`1.0 FDR
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`November 13, 1995
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`Revisions to Chapters 1, 2, 5-11.
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`1.0
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`1.1
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`January 15, 1996
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`Edits to Chapters 5, 6, 7, 8, 9, 10, and 11 for
`consistency.
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`September 23, 1998
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`Updates to all chapters to fix problems identified.
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`2.0 (draft 0.79) October 5, 1999
`
`Revisions to chapters 5, 7, 8, 9, 11 to add high
`speed.
`
`2.0 (draft 0.9)
`
`December 21, 1999
`
`Revisions to all chapters to add high speed.
`
`2.0
`
`April 27, 2000
`
`Revisions for high-speed mode.
`
`Universal Serial Bus Specification
`Copyright C 2000, Compaq Computer Corporation,
`Hewlett-Packard Company, Intel Corporation, Lucent Technologies Inc,
`Microsoft Corporation, NEC Corporation, Koninklijke Philips Electronics N.V.
`All rights reserved.
`
`INTELLECTUAL PROPERTY DISCLAIMER
`THIS SPECIFICATION IS PROVIDED TO YOU "AS IS" WITH NO WARRANTIES WHATSOEVER,
`INCLUDING ANY WARRANTY OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR
`ANY PARTICULAR PURPOSE. THE AUTHORS OF THIS SPECIFICATION DISCLAIM ALL LIABILITY,
`INCLUDING LIABILITY FOR INFRINGEMENT OF ANY PROPRIETARY RIGHTS, RELATING TO USE
`OR IMPLEMENTATION OF INFORMATION IN THIS SPECIFICATION. THE PROVISION OF THIS
`SPECIFICATION TO YOU DOES NOT PROVIDE YOU WITH ANY LICENSE, EXPRESS OR IMPLIED,
`BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS.
`
`All product names are trademarks, registered trademarks, or servicemarks of their respective owners.
`
`Please send comments via electronic mail to techsup@usb.org
`For industry information, refer to the USB Implementers Forum web page at http://www.usb.org
`
`fi
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`Universal Serial Bus Specification Revision 2.0
`
`Acknowledgement of USB 2.0 Technical Contribution
`
`The authors of this specification would like to recognize the following people who participated in the USB
`2.0 Promoter Group technical working groups. We would also like to thank others in the USB 2.0
`Promoter companies and throughout the industry who contributed to the development of this specification.
`
`Hub Working Group
`John Garney (cid:9)
`Ken Stufflebeam (cid:9)
`David Wooten (cid:9)
`Matt Nieberger (cid:9)
`John Howard (cid:9)
`Venkat lyer (cid:9)
`Steve McGowan (cid:9)
`Geert Knapen (cid:9)
`Zong Liang Wu (cid:9)
`Jim Clee (cid:9)
`Jim Guziak (cid:9)
`Dave Thompson (cid:9)
`John Fuller (cid:9)
`Nathan Sherman (cid:9)
`Mark Williams (cid:9)
`Nobuo Furuya (cid:9)
`Toshimi Sakurai (cid:9)
`Moto Sato (cid:9)
`Katsuya Suzuki (cid:9)
`
`Intel Corporation (Chair/Editor)
`Compaq Computer Corporation
`Compaq Computer Corporation
`Hewlett-Packard Company
`Intel Corporation
`Intel Corporation
`Intel Corporation
`Royal Philips Electronics
`Royal Philips Electronics
`Lucent Technologies Inc
`Lucent Technologies Inc
`Lucent Technologies Inc
`Microsoft Corporation
`Microsoft Corporation
`Microsoft Corporation
`NEC Corporation
`NEC Corporation
`NEC Corporation
`NEC Corporation
`
`Electrical Working Group
`Jon Lueker
`Intel Corporation (Chair/Editor)
`David Wooten
`Compaq Computer Corporation
`Matt Nieberger
`Hewlett-Packard Company
`Larry Taugher
`Hewlett-Packard Company
`Venkat lyer
`Intel Corporation
`Steve McGowan
`Intel Corporation
`Mike Pennell
`Intel Corporation
`Todd West
`Intel Corporation
`Gerrit den Besten
`Royal Philips Electronics
`Marq Kole
`Royal Philips Electronics
`Zong Liang Wu
`Royal Philips Electronics
`Jim Clee
`Lucent Technologies Inc
`Jim Guziak
`Lucent Technologies Inc
`Par Parikh
`Lucent Technologies Inc
`Dave Thompson
`Lucent Technologies Inc
`Ed Giaimo
`Microsoft Corporation
`Mark Williams
`Microsoft Corporation
`Toshihiko Ohtani
`NEC Corporation
`Kugao Ouchi
`NEC Corporation
`Katsuya Suzuki
`NEC Corporation
`Toshio Tasaki
`NEC Corporation
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`

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`Universal Serial Bus Specification Revision 2.0
`
`iv
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`Page 00005
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`Universal Serial Bus Specification Revision 2.0
`
`Contents
`
`CHAPTER 1 INTRODUCTION
`
`1.1 Motivation (cid:9)
`
`1.2 Objective of the Specification (cid:9)
`
`1.3 Scope of the Document (cid:9)
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`1.4 USB Product Compliance (cid:9)
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`1.5 Document Organization (cid:9)
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`CHAPTER 2 TERMS AND ABBREVIATIONS
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`CHAPTER 3 BACKGROUND
`
`3.1 Goals for the Universal Serial Bus (cid:9)
`
`3.2 Taxonomy of Application Space (cid:9)
`
`3.3 Feature List (cid:9)
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`CHAPTER 4 ARCHITECTURAL OVERVIEW
`
`4.1 USB System Description (cid:9)
`4.1.1 Bus Topology (cid:9)
`
`4.2 Physical Interface (cid:9)
`4.2.1 (cid:9)
`Electrical (cid:9)
`4.2.2 Mechanical (cid:9)
`
`4.3 Power (cid:9)
`4.3.1 (cid:9)
`Power Distribution (cid:9)
`4.3.2 Power Management (cid:9)
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`4.4 Bus Protocol (cid:9)
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`4.5 Robustness (cid:9)
`4.5.1 (cid:9)
`Error Detection (cid:9)
`4.5.2 Error Handling (cid:9)
`
`4.6 System Configuration (cid:9)
`4.6.1 Attachment of USB Devices (cid:9)
`4.6.2 Removal of USB Devices (cid:9)
`4.6.3 Bus Enumeration (cid:9)
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`4.7 Data Flow Types (cid:9)
`4.7.1 (cid:9)
`Control Transfers (cid:9)
`4.7.2 Bulk Transfers (cid:9)
`4.7.3 (cid:9)
`Interrupt Transfers (cid:9)
`4.7.4 Isochronous Transfers (cid:9)
`4.7.5 Allocating USB Bandwidth (cid:9)
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`4.8 USB Devices (cid:9)
`4.8.1 Device Characterizations (cid:9)
`4.8.2 Device Descriptions (cid:9)
`
`4.9 USB Host: Hardware and Software (cid:9)
`
`4.10 Architectural Extensions (cid:9)
`
`CHAPTER 5 USB DATA FLOW MODEL
`
`5.1 Implementer Viewpoints (cid:9)
`
`5.2 Bus Topology (cid:9)
`5.2.1 USB Host (cid:9)
`5.2.2 USB Devices (cid:9)
`5.2.3 Physical Bus Topology (cid:9)
`5.2.4 Logical Bus Topology (cid:9)
`5.2.5 (cid:9)
`Client Software-to-function Relationship (cid:9)
`
`5.3 USB Communication Flow (cid:9)
`5.3.1 (cid:9)
`Device Endpoints (cid:9)
`5.3.2 (cid:9)
`Pipes (cid:9)
`5.3.3 Frames and Microframes (cid:9)
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`5.4 Transfer Types (cid:9)
`5.4.1 (cid:9)
`Table Calculation Examples (cid:9)
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`5.5 Control Transfers (cid:9)
`5.5.1 Control Transfer Data Format (cid:9)
`5.5.2 Control Transfer Direction (cid:9)
`5.5.3 (cid:9)
`Control Transfer Packet Size Constraints (cid:9)
`5.5.4 Control Transfer Bus Access Constraints (cid:9)
`5.5.5 Control Transfer Data Sequences (cid:9)
`
`5.6 Isochronous Transfers (cid:9)
`5.6.1 Isochronous Transfer Data Format (cid:9)
`5.6.2 Isochronous Transfer Direction (cid:9)
`5.6.3 Isochronous Transfer Packet Size Constraints (cid:9)
`5.6.4 Isochronous Transfer Bus Access Constraints (cid:9)
`5.6.5 Isochronous Transfer Data Sequences (cid:9)
`
`5.7 Interrupt Transfers (cid:9)
`5.7.1 (cid:9)
`Interrupt Transfer Data Format (cid:9)
`5.7.2 Interrupt Transfer Direction (cid:9)
`5.7.3 Interrupt Transfer Packet Size Constraints (cid:9)
`5.7.4 Interrupt Transfer Bus Access Constraints (cid:9)
`5.7.5 Interrupt Transfer Data Sequences (cid:9)
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`Universal Serial Bus Specification Revision 2.0
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`5.8 Bulk Transfers (cid:9)
`5.8.1 Bulk Transfer Data Format (cid:9)
`5.8.2 Bulk Transfer Direction (cid:9)
`5.8.3 Bulk Transfer Packet Size Constraints (cid:9)
`5.8.4 Bulk Transfer Bus Access Constraints (cid:9)
`5.8.5 Bulk Transfer Data Sequences (cid:9)
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`5.9 High-Speed, High Bandwidth Endpoints (cid:9)
`5.9.1 High Bandwidth Interrupt Endpoints (cid:9)
`5.9.2 High Bandwidth Isochronous Endpoints (cid:9)
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`5.10 Split Transactions (cid:9)
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`5.11 Bus Access for Transfers (cid:9)
`5.11.1 Transfer Management (cid:9)
`5.11.2 Transaction Tracking (cid:9)
`5.11.3 Calculating Bus Transaction Times (cid:9)
`5.11.4 Calculating Buffer Sizes in Functions and Software (cid:9)
`5.11.5 Bus Bandwidth Reclamation (cid:9)
`
`5.12 Special Considerations for Isochronous Transfers (cid:9)
`5.12.1 Example Non-USB Isochronous Application (cid:9)
`5.12.2 USB Clock Model (cid:9)
`5.12.3 Clock Synchronization (cid:9)
`5.12.4 Isochronous Devices (cid:9)
`5.12.5 Data Prebuffering (cid:9)
`5.12.6 SOF Tracking (cid:9)
`5.12.7 Error Handling (cid:9)
`5.12.8 Buffering for Rate Matching (cid:9)
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`CHAPTER 6 MECHANICAL
`
`6.1 Architectural Overview (cid:9)
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`6.2 Keyed Connector Protocol (cid:9)
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`6.3 Cable (cid:9)
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`6.4 Cable Assembly (cid:9)
`6.4.1 Standard Detachable Cable Assemblies (cid:9)
`6.4.2 High-/full-speed Captive Cable Assemblies (cid:9)
`6.4.3 Low-speed Captive Cable Assemblies (cid:9)
`6.4.4 Prohibited Cable Assemblies (cid:9)
`
`6.5 Connector Mechanical Configuration and Material Requirements (cid:9)
`6.5.1 USB Icon Location (cid:9)
`6.5.2 USB Connector Termination Data (cid:9)
`6.5.3 Series "A" and Series "B" Receptacles (cid:9)
`6.5.4 Series "A" and Series "B" Plugs (cid:9)
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`6.6 Cable Mechanical Configuration and Material Requirements (cid:9)
`Description (cid:9)
`6.6.1 (cid:9)
`6.6.2 Construction (cid:9)
`Electrical Characteristics (cid:9)
`6.6.3 (cid:9)
`6.1.4 Cable Environmental Characteristics (cid:9)
`Listing (cid:9)
`6.1.5 (cid:9)
`
`6.7 Electrical, Mechanical, and Environmental Compliance Standards (cid:9)
`6.7.1 Applicable Documents (cid:9)
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`6.8 USB Grounding (cid:9)
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`6.9 PCB Reference Drawings (cid:9)
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`CHAPTER 7 ELECTRICAL
`
`7.1 Signaling (cid:9)
`7.1.1 (cid:9)
`USB Driver Characteristics (cid:9)
`7.1.2 Data Signal Rise and Fall, Eye Patterns (cid:9)
`7.1.3 Cable Skew (cid:9)
`7.1.4 Receiver Characteristics (cid:9)
`7.1.5 (cid:9)
`Device Speed Identification (cid:9)
`7.1.6 (cid:9)
`Input Characteristics (cid:9)
`7.1.7 (cid:9)
`Signaling Levels (cid:9)
`7.1.8 Data Encoding/Decoding (cid:9)
`7.1.9 (cid:9)
`Bit Stuffing (cid:9)
`7.1.10 Sync Pattern (cid:9)
`7.1.11 Data Signaling Rate (cid:9)
`7.1.12 Frame Interval (cid:9)
`7.1.13 Data Source Signaling (cid:9)
`7.1.14 Hub Signaling Timings (cid:9)
`7.1.15 Receiver Data Jitter (cid:9)
`7.1.16 Cable Delay (cid:9)
`7.1.17 Cable Attenuation (cid:9)
`7.1.18 Bus Turn-around Time and Inter-packet Delay (cid:9)
`7.1.19 Maximum End-to-end Signal Delay (cid:9)
`7.1.20 Test Mode Support (cid:9)
`
`7.2 Power Distribution (cid:9)
`7.2.1 (cid:9)
`Classes of Devices (cid:9)
`7.2.2 Voltage Drop Budget (cid:9)
`7.2.3 Power Control During Suspend/Resume (cid:9)
`7.2.4 Dynamic Attach and Detach (cid:9)
`
`7.3 Physical Layer (cid:9)
`7.3.1 Regulatory Requirements (cid:9)
`7.3.2 Bus Timing/Electrical Characteristics (cid:9)
`7.3.3 Timing Waveforms (cid:9)
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`Universal Serial Bus Specification Revision 2.0
`
`CHAPTER 8 PROTOCOL LAYER
`
`8.1 Byte/Bit Ordering (cid:9)
`
`8.2 SYNC Field (cid:9)
`
`8.3 Packet Field Formats (cid:9)
`Packet Identifier Field (cid:9)
`8.3.1 (cid:9)
`8.3.2 Address Fields (cid:9)
`8.3.3 Frame Number Field (cid:9)
`8.3.4 Data Field (cid:9)
`8.3.5 Cyclic Redundancy Checks (cid:9)
`
`8.4 Packet Formats (cid:9)
`8.4.1 (cid:9)
`Token Packets (cid:9)
`8.4.2 Split Transaction Special Token Packets (cid:9)
`Start-of-Frame Packets (cid:9)
`8.4.3 (cid:9)
`8.4.4 Data Packets (cid:9)
`8.4.5 Handshake Packets (cid:9)
`8.4.6 Handshake Responses (cid:9)
`
`8.5 Transaction Packet Sequences (cid:9)
`8.5.1 NAK Limiting via Ping Flow Control (cid:9)
`8.5.2 Bulk Transactions (cid:9)
`8.5.3 Control Transfers (cid:9)
`8.5.4 Interrupt Transactions (cid:9)
`8.5.5 Isochronous Transactions (cid:9)
`
`8.6 Data Toggle Synchronization and Retry (cid:9)
`8.6.1 (cid:9)
`Initialization via SETUP Token (cid:9)
`8.6.2 Successful Data Transactions (cid:9)
`8.6.3 Data Corrupted or Not Accepted (cid:9)
`8.6.4 Corrupted ACK Handshake (cid:9)
`8.6.5 Low-speed Transactions (cid:9)
`
`8.7 Error Detection and Recovery (cid:9)
`8.7.1 (cid:9)
`Packet Error Categories (cid:9)
`8.7.2 Bus Turn-around Timing (cid:9)
`8.7.3 False EOPs (cid:9)
`8.7.4 Babble and Loss of Activity Recovery (cid:9)
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`Universal Serial Bus Specification Revision 2.0
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`CHAPTER 9 USB DEVICE FRAMEWORK
`
`9.1 USB Device States (cid:9)
`9.1.1 (cid:9)
`Visible Device States (cid:9)
`9.1.2 Bus Enumeration (cid:9)
`
`9.2 Generic USB Device Operations (cid:9)
`9.2.1 Dynamic Attachment and Removal (cid:9)
`9.2.2 Address Assignment (cid:9)
`9.2.3 Configuration (cid:9)
`9.2.4 Data Transfer (cid:9)
`9.2.5 Power Management (cid:9)
`9.2.6 Request Processing (cid:9)
`9.2.7 Request Error (cid:9)
`
`9.3 USE Device Requests (cid:9)
`9.3.1 bmRequestType (cid:9)
`9.3.2 bRequest (cid:9)
`9.3.3 wValue (cid:9)
`9.3.4 wIndex (cid:9)
`9.3.5 wLength (cid:9)
`
`9.4 Standard Device Requests (cid:9)
`Clear Feature (cid:9)
`9.4.1 (cid:9)
`9.4.2 Get Configuration (cid:9)
`9.4.3 Get Descriptor (cid:9)
`9.4.4 Get Interface (cid:9)
`9.4.5 Get Status (cid:9)
`9.4.6 Set Address (cid:9)
`9.4.7 Set Configuration (cid:9)
`9.4.8 (cid:9)
`Set Descriptor (cid:9)
`9.4.9 (cid:9)
`Set Feature (cid:9)
`9.4.10 Set Interface (cid:9)
`9.4.11 Synch Frame (cid:9)
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`9.5 Descriptors (cid:9)
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`9.6 Standard USB Descriptor Definitions (cid:9)
`9.6.1 (cid:9)
`Device (cid:9)
`9.6.2 Device_Qualifier (cid:9)
`9.6.3 Configuration (cid:9)
`9.6.4 Other_Speed_Configuration (cid:9)
`9.6.5 (cid:9)
`Interface (cid:9)
`9.6.6 Endpoint (cid:9)
`String (cid:9)
`9.6.7 (cid:9)
`
`9.7 Device Class Definitions (cid:9)
`9.7.1 (cid:9)
`Descriptors (cid:9)
`9.7.2 Interface(s) and Endpoint Usage (cid:9)
`9.7.3 Requests (cid:9)
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`Universal Serial Bus Specification Revision 2.0
`
`CHAPTER 10 USB HOST: HARDWARE AND SOFTWARE
`
`10.1 Overview of the USB Host (cid:9)
`10.1.1 Overview (cid:9)
`10.1.2 Control Mechanisms (cid:9)
`10.1.3 Data Flow (cid:9)
`10.1.4 Collecting Status and Activity Statistics (cid:9)
`10.1.5 Electrical Interface Considerations (cid:9)
`
`10.2 Host Controller Requirements (cid:9)
`10.2.1 State Handling (cid:9)
`10.2.2 Serializer/Deserializer (cid:9)
`10.2.3 Frame and Microframe Generation (cid:9)
`10.2.4 Data Processing (cid:9)
`10.2.5 Protocol Engine (cid:9)
`10.2.6 Transmission Error Handling (cid:9)
`10.2.7 Remote Wakeup (cid:9)
`10.2.8 Root Hub (cid:9)
`10.2.9 Host System Interface (cid:9)
`
`10.3 Overview of Software Mechanisms (cid:9)
`10.3.1 Device Configuration (cid:9)
`10.3.2 Resource Management (cid:9)
`10.3.3 Data Transfers (cid:9)
`10.3.4 Common Data Definitions (cid:9)
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`10.4 Host Controller Driver (cid:9)
`
`10.5 Universal Serial Bus Driver (cid:9)
`10.5.1 USBD Overview (cid:9)
`10.5.2 USBD Command Mechanism Requirements (cid:9)
`10.5.3 USBD Pipe Mechanisms (cid:9)
`10.5.4 Managing the USB via the USBD Mechanisms (cid:9)
`10.5.5 Passing USB Preboot Control to the Operating System (cid:9)
`
`10.6 Operating System Environment Guides (cid:9)
`
`CHAPTER 11 HUB SPECIFICATION
`
`11.1 Overview (cid:9)
`11.1.1 Hub Architecture (cid:9)
`11.1.2 Hub Connectivity (cid:9)
`
`11.2 Hub Frame/Microframe Timer (cid:9)
`11.2.1 High-speed Microframe Timer Range (cid:9)
`11.2.2 Full-speed Frame Timer Range (cid:9)
`11.2.3 Frame/Microframe Timer Synchronization (cid:9)
`11.2.4 Microframe Jitter Related to Frame Jitter (cid:9)
`11.2.5 E0F1 and E0F2 Timing Points (cid:9)
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`11.3 (cid:9)
`
`Host Behavior at End-of-Frame (cid:9)
`11.3.1 Full-/low-speed Latest Host Packet (cid:9)
`11.3.2 Full-/low-speed Packet Nullification (cid:9)
`11.3.3 Full-/low-speed Transaction Completion Prediction (cid:9)
`
`11.4 Internal Port (cid:9)
`11.4.1 Inactive (cid:9)
`11.4.2 Suspend Delay (cid:9)
`11.4.3 Full Suspend (Fsus) (cid:9)
`11.4.4 Generate Resume (GResume) (cid:9)
`
`11.5 Downstream Facing Ports (cid:9)
`11.5.1 Downstream Facing Port State Descriptions (cid:9)
`11.5.2 Disconnect Detect Timer (cid:9)
`11.5.3 Port Indicator (cid:9)
`
`11.6 Upstream Facing Port (cid:9)
`11.6.1 Full-speed (cid:9)
`11.6.2 High-speed (cid:9)
`11.6.3 Receiver (cid:9)
`11.6.4 Transmitter (cid:9)
`
`11.7 Hub Repeater (cid:9)
`11.7.1 High-speed Packet Connectivity (cid:9)
`11.7.2 Hub Repeater State Machine (cid:9)
`11.7.3 Wait for Start of Packet from Upstream Port (WFSOPFU) (cid:9)
`11.7.4 Wait for End of Packet from Upstream Port (WFEOPFU) (cid:9)
`11.7.5 Wait for Start of Packet (WFSOP) (cid:9)
`11.7.6 Wait for End of Packet (WFEOP) (cid:9)
`
`11.8 Bus State Evaluation (cid:9)
`11.8.1 Port Error (cid:9)
`11.8.2 Speed Detection (cid:9)
`11.8.3 Collision (cid:9)
`11.8.4 Low-speed Port Behavior (cid:9)
`
`11.9 Suspend and Resume (cid:9)
`
`11.10 Hub Reset Behavior (cid:9)
`
`11.11 Hub Port Power Control (cid:9)
`11.11.1 Multiple Gangs (cid:9)
`
`11.12 Hub Controller (cid:9)
`11.12.1 Endpoint Organization (cid:9)
`11.12.2 Hub Information Architecture and Operation (cid:9)
`11.12.3 Port Change Information Processing (cid:9)
`11.12.4 Hub and Port Status Change Bitmap (cid:9)
`11.12.5 Over-current Reporting and Recovery (cid:9)
`11.12.6 Enumeration Handling (cid:9)
`
`11.13 Hub Configuration (cid:9)
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`xii
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`11.14 Transaction Translator (cid:9)
`11.14.1 Overview (cid:9)
`11.14.2 Transaction Translator Scheduling (cid:9)
`
`11.15 Split Transaction Notation Information (cid:9)
`
`11.16 Common Split Transaction State Machines (cid:9)
`11.16.1 Host Controller State Machine (cid:9)
`11.16.2 Transaction Translator State Machine (cid:9)
`
`11.17 Bulk/Control Transaction Translation Overview (cid:9)
`11.17.1 Bulk/Control Split Transaction Sequences (cid:9)
`11.17.2 Bulk/Control Split Transaction State Machines (cid:9)
`11.17.3 Bulk/Control Sequencing (cid:9)
`11.17.4 Bulk/Control Buffering Requirements (cid:9)
`11.17.5 Other Bulk/Control Details (cid:9)
`
`11.18 Periodic Split Transaction Pipelining and Buffer Management (cid:9)
`11.18.1 Best Case Full-Speed Budget (cid:9)
`11.18.2 TT Microframe Pipeline (cid:9)
`11.18.3 Generation of Full-speed Frames (cid:9)
`11.18.4 Host Split Transaction Scheduling Requirements (cid:9)
`11.18.5 TT Response Generation (cid:9)
`11.18.6 IT Periodic Transaction Handling Requirements (cid:9)
`11.18.7 IT Transaction Tracking (cid:9)
`11.18:8 TT Complete-split Transaction State Searching (cid:9)
`
`11.19 Approximate TT Buffer Space Required (cid:9)
`
`11.20 Interrupt Transaction Translation Overview (cid:9)
`11.20.1 Interrupt Split Transaction Sequences (cid:9)
`11.20.2 Interrupt Split Transaction State Machines (cid:9)
`11.20.3 Interrupt OUT Sequencing (cid:9)
`11.20.4 Interrupt IN Sequencing (cid:9)
`
`11.21 Isochronous Transaction Translation Overview (cid:9)
`11.21.1 Isochronous Split Transaction Sequences (cid:9)
`11.21.2 Isochronous Split Transaction State Machines (cid:9)
`11.21.3 Isochronous OUT Sequencing (cid:9)
`11.21.4 Isochronous IN Sequencing (cid:9)
`
`11.22 TT Error Handling (cid:9)
`11.22.1 Loss of IT Synchronization With HS SOFs (cid:9)
`11.22.2 IT Frame and Microfiame Timer Synchronization Requirements (cid:9)
`
`11.23 Descriptors (cid:9)
`11.23.1 Standard Descriptors for Hub Class (cid:9)
`11.23.2 Class-specific Descriptors (cid:9)
`
`11.24 Requests (cid:9)
`11.24.1 Standard Requests (cid:9)
`11.24.2 Class-specific Requests (cid:9)
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`366
`371
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`Page 00014
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`Universal Serial Bus Specification Revision 2.0
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`APPENDIX A TRANSACTION EXAMPLES
`
`A.1 Bulk/Control OUT and SETUP Transaction Examples (cid:9)
`
`A.2 Bulk/Control IN Transaction Examples (cid:9)
`
`A.3 Interrupt OUT Transaction Examples (cid:9)
`
`A.4 Interrupt IN Transaction Examples (cid:9)
`
`A.5 Isochronous OUT SpAppendix A Transaction Examples
`
`APPENDIX B EXAMPLE DECLARATIONS FOR STATE MACHINES
`
`B.1 Global Declarations (cid:9)
`
`B.2 Host Controller Declarations (cid:9)
`
`B.3 Transaction Translator Declarations (cid:9)
`
`APPENDIX C RESET PROTOCOL STATE DIAGRAMS
`
`C.1 Downstream Facing Port State Diagram (cid:9)
`
`C.2 Upstream Facing Port State Diagram (cid:9)
`C.2.1 Reset From Suspended State (cid:9)
`C.2.2 Reset From Full-speed Non-suspended State (cid:9)
`C.2.3 Reset From High-speed Non-suspended State (cid:9)
`C.2.4 Reset Handshake (cid:9)
`
`INDEX
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`464
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`489
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`509
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`555
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`558
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`560
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`570
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`Page 00015
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`Figures
`
`Figure 3-1. Application Space Taxonomy (cid:9)
`Figure 4-1. Bus Topology (cid:9)
`Figure 4-2. USB Cable (cid:9)
`Figure 4-3. A Typical Hub (cid:9)
`Figure 4-4. Hubs in a Desktop Computer Environment (cid:9)
`Figure 5-1. Simple USB Host/Device View (cid:9)
`Figure 5-2. USB Implementation Areas (cid:9)
`Figure 5-3. Host Composition (cid:9)
`Figure 5-4. Physical Device Composition (cid:9)
`Figure 5-5. USB Physical Bus Topology (cid:9)
`Figure 5-6. Multiple Full-speed Buses in a High-speed System (cid:9)
`Figure 5-7. USB Logical Bus Topology (cid:9)
`Figure 5-8. Client Software-to-function Relationships (cid:9)
`Figure 5-9. USB Host/Device Detailed View (cid:9)
`Figure 5-10. USB Communication Flow (cid:9)
`Figure 5-11. Data Phase PID Sequence for Isochronous IN High Bandwidth Endpoints (cid:9)
`Figure 5-12. Data Phase PID Sequence for Isochronous OUT High Bandwidth Endpoints (cid:9)
`Figure 5-13. USB Information Conversion From Client Software to Bus (cid:9)
`Figure 5-14. Transfers for Communication Flows (cid:9)
`Figure 5-15. Arrangement of IRPs to Transactions/(Micro)frames (cid:9)
`Figure 5-16. Non-USB Isochronous Example (cid:9)
`Figure 5-17. USB Full-speed Isochronous Application (cid:9)
`Figure 5-18. Example Source/Sink Connectivity (cid:9)
`Figure 5-19. Data Prebuffering (cid:9)
`Figure 5-20. Packet and Buffer Size Formulas for Rate-matched Isochronous Transfers (cid:9)
`Figure 6-1. Keyed Connector Protocol (cid:9)
`Figure 6-2. USB Standard Detachable Cable Assembly (cid:9)
`Figure 6-3. USB High-/full-speed Hardwired Cable Assembly (cid:9)
`Figure 6-4. USB Low-speed Hardwired Cable Assembly (cid:9)
`Figure 6-5. USB Icon (cid:9)
`Figure 6-6. Typical USB Plug Orientation (cid:9)
`Figure 6-7. USB Series "A" Receptacle Interface and Mating Drawing (cid:9)
`Figure 6-8. USB Series "B" Receptacle Interface and Mating Drawing (cid:9)
`
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`Figure 6-9. USB Series "A" Plug Interface Drawing (cid:9)
`Figure 6-10. USB Series "B" Plug Interface Drawing (cid:9)
`Figure 6-11. Typical High-/full-speed Cable Construction (cid:9)
`Figure 6-12. Single Pin-type Series "A" Receptacle (cid:9)
`Figure 6-13. Dual Pin-type Series "A" Receptacle (cid:9)
`Figure 6-14. Single Pin-type Series "B" Receptacle (cid:9)
`Figure 7-1. Example High-speed Capable Transceiver Circuit (cid:9)
`Figure 7-2. Maximum Input Waveforms for USB Signaling (cid:9)
`Figure 7-3. Example Full-speed CMOS Driver Circuit (non High-speed capable) (cid:9)
`Figure 7-4. Full-speed Buffer V/I Characteristics (cid:9)
`Figure 7-5. Full-speed Buffer V/I Characteristics for High-speed Capable Transceiver (cid:9)
`Figure 7-6. Full-speed Signal Waveforms (cid:9)
`Figure 7-7. Low-speed Driver Signal Waveforms (cid:9)
`Figure 7-8. Data Signal Rise and Fall Time (cid:9)
`Figure 7-9. Full-speed Load (cid:9)
`Figure 7-10. Low-speed Port Loads (cid:9)
`Figure 7-11. Measurement Planes (cid:9)
`Figure 7-12. Transmitter/Receiver Test Fixture (cid:9)
`Figure 7-13. Template 1 (cid:9)
`Figure 7-14. Template 2 (cid:9)
`Figure 7-15. Template 3 (cid:9)
`Figure 7-16. Template 4 (cid:9)
`Figure 7-17. Template 5 (cid:9)
`Figure 7-18. Template 6 (cid:9)
`Figure 7-19. Differential Input Sensitivity Range for Low-/full-speed (cid:9)
`Figure 7-20. Full-speed Device Cable and Resistor Connections (cid:9)
`Figure 7-21. Low-speed Device Cable and Resistor Connections (cid:9)
`Figure 7-22. Placement of Optional Edge Rate Control Capacitors for Low-/full-speed (cid:9)
`Figure 7-23. Diagram for High-speed Loading Ecluivalent Circuit (cid:9)
`Figure 7-24. Upstream Facing Full-speed Port Transceiver (cid:9)
`Figure 7-25. Downstream Facing Low-/full-speed Port Transceiver (cid:9)
`Figure 7-26. Low-/full-speed Disconnect Detection (cid:9)
`Figure 7-27. Full-/high-speed Device Connect Detection (cid:9)
`Figure 7-28. Low-speed Device Connect Detection (cid:9)
`Figure 7-29. Power-on and Connection Events Timing (cid:9)
`Figure 7-30. Low-/full-speed Packet Voltage Levels (cid:9)
`Figure 7-31. NRZI Data Encoding (cid:9)
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`Page 00017
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`Figure 7-32, Bit Stuffing (cid:9)
`Figure 7-33. Illustration of Extra Bit Preceding EOP (Full-/low-speed) (cid:9)
`Figure 7-34. Flow Diagram for Bit Stuffing (cid:9)
`Figure 7-35. Sync Pattern (Low-/full-speed) (cid:9)
`Figure 7-36. Data Jitter Taxonomy (cid:9)
`Figure 7-37. SEO for EOP Width Timing (cid:9)
`Figure 7-38. Hub Propagation Delay of Full-speed Differential Signals (cid:9)
`Figure 7-39. Full-speed Cable Delay (cid:9)
`Figure 7-40. Low-speed Cable Delay (cid:9)
`Figure 7-41. Worst-case End-to-end Signal Delay Model for Low-/full-speed (cid:9)
`Figure 7-42. Compound Bus-powered Hub (cid:9)
`Figure 7-43. Compound Self-powered Hub (cid:9)
`Figure 7-44. Low-power Bus-powered Function (cid:9)
`Figure 7-45. High-power Bus-powered Function (cid:9)
`Figure 7-46. Self-powered Function (cid:9)
`Figure 7-47. Worst-case Voltage Drop Topology (Steady State) (cid:9)
`Figure 7-48. Typical Suspend Current Averaging Profile (cid:9)
`Figure 7-49. Differential Data Jitter for Low-/full-speed (cid:9)
`Figure 7-50. Differential-to-EOP Transition Skew and EOP Width for Low-/full-speed (cid:9)
`Figure 7-51. Receiver Jitter Tolerance for Low-/full-speed (cid:9)
`Figure 7-52. Hub Differential Delay, Differential Jitter, and SOP Distortion for Low-/full-speed (cid:9)
`Figure 7-53. Hub EOP Delay and EOP Skew for Low-/full-speed (cid:9)
`Figure 8-1. PID Format (cid:9)
`Figure 8-2. ADDR Field (cid:9)
`Figure 8-3. Endpoint Field (cid:9)
`Figure 8-4. Data Field Format (cid:9)
`Figure 8-5. Token Format (cid:9)
`Figure 8-6. Packets in a Start-split Transaction (cid:9)
`Figure 8-7. Packets in a Complete-split Transaction (cid:9)
`Figure 8-8. Relationship of Interrupt IN Transaction to High-speed Split Transaction (cid:9)
`Figure 8-9. Relationship of Interrupt OUT Transaction to High-speed Split OUT Transaction (cid:9)
`Figure 8-10. Start-split (SSPLIT) Token (cid:9)
`Figure 8-11. Port Field (cid:9)
`Figure 8-12. Complete-split (CSPLIT) Transaction Token (cid:9)
`Figure 8-13. SOF Packet (cid:9)
`Figure 8-14. Relationship between Frames and Microframes (cid:9)
`Figure 8-15. Data Packet Format (cid:9)
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`Figure 8-16. Handshake Packet (cid:9)
`Figure 8-17. Legend for State Machines (cid:9)
`Figure 8-18. State Machine Context Overview (cid:9)
`Figure 8-19. Host Controller Top Level Transaction State Machine Hierarchy Overview
`Figure 8-20. Host Controller Non-split Transaction State Machine Hierarchy Overview (cid:9)
`Figure 8-21. Device Transaction State Machine Hierarchy Overview (cid:9)
`Figure 8-22. Device Top Level State Machine (cid:9)
`Figure 8-23. Device_process_Trans State Machine (cid:9)
`Figure 8-24. Dev_do_OUT State Machine (cid:9)
`Figure 8-25. Dev_do_IN State Machine (cid:9)
`Figure 8-26. HC_Do_nonsplit State Machine (cid:9)
`Figure 8-27. Host High-speed Bulk OUT/Control Ping State Machine (cid:9)
`Figure 8-28. Dev_HS_ping State Machine (cid:9)
`Figure 8-29. Device High-speed Bulk OUT /Control State Machine (cid:9)
`Figure 8-30. Bulk Transaction Format (cid:9)
`Figure 8-31. Bulk/Control/Interrupt OUT Transaction Host State Machine (cid:9)
`Figure 8-32. Bulk/Control/Interrupt OUT Transaction Device State Machine (cid:9)
`Figure 8-33. Bulk/Control/Interrupt IN Transaction Host State Machine (cid:9)
`Figure 8-34. Bulk/Control/Interrupt IN Transaction Device State Machine (cid:9)
`Figure 8-35. Bulk Reads and Writes (cid:9)
`Figure 8-36. Control SETUP Transaction (cid:9)
`Figure 8-37. Control Read and Write Sequences (cid:9)
`Figure 8-38. Interrupt Transaction Format (cid:9)
`Figure 8-39. Isochronous Transaction Format (cid:9)
`Figure 8-40. Isochronous OUT Transaction Host State Machine (cid:9)
`Figure 8-41. Isochronous OUT Transaction Device State Machine (cid:9)
`Figure 8-42. Isochronous IN Transaction Host State Machine (cid:9)
`Figure 8-43. Isochronous IN Transaction Device State Machine (cid:9)
`Figure 8-44. SETUP Initialization (cid:9)
`Figure 8-45. Consecutive Transactions (cid:9)
`Figure 8-46. NAKed Transaction with Retry (cid:9)
`Figure 8-47. Corrupted ACK Handshake with Retry (cid:9)
`Figure 8-48. Low-speed Transaction (cid:9)
`Figure 8-49. Bus Turn-around Timer Usage (cid:9)
`Figure 9-1. Device State Diagram (cid:9)
`Figure 9-2. wIndex Format when Specifying an Endpoint (cid:9)
`Figure 9-3. wIndex Format when Specifying an Interface (cid:9)
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`Page 00019
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`Universal Serial Bus Specification Revision 2.0
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`Figure 9-4. Information Returned by a GetStatus() Request to a Device
`Figure 9-5. Information Returned by a GetStatus() Request to an Interface (cid:9)
`Figure 9-6. Information Returned by a GetStatus() Request to an Endpoint (cid:9)
`Figure 9-7. Example of Feedback Endpoint Numbers (cid:9)
`Figure 9-8. Example of Feedback Endpoint Relationships (cid:9)
`Figure 10-1. Interlayer Communications Model (cid:9)
`Figure 10-2. Host Communications (cid:9)
`Figure 10-3. Frame and Microframe Creation (cid:9)
`Figure 10-4. Configuration Interactions (cid:9)
`Figure 10-5. Universal Serial Bus Driver Structure (cid:9)
`Figure 11-1. Hub Architecture (cid:9)
`Figure 11-2. Hub Signaling Connectivity (cid:9)
`Figure 11-3. Resume Connectivity (cid:9)
`Figure 11-4. Example High-speed EOF Offsets Due to Propagation Delay Without EOF Advancement (cid:9)
`Figure 11-5. Example High-speed EOF Offsets Due to Propagation Delay With EOF Advancement (cid:9)
`Figure 11-6. High-speed E0F2 Timing Point (cid:9)
`Figure 11-7. High-speed E0F1 Timing Point (cid:9)
`Figure 11-8. Full-speed EOF Timing Points (cid:9)
`Figure 11-9. Internal Port State Machine (cid:9)
`Figure 11-10. Downstream Facing Hub Port State Machine (cid:9)
`Figure 11-11. Port Indicator State Diagram (cid:9)
`Figure 11-12. Upstream Facing Port Receiver State Machine (cid:9)
`Figure 11-13. Upstream Facing Port Transmitter State Machine (cid:9)
`Figure 11-14. Example Hub Repeater Organization (cid:9)
`Figure 11-15. High-speed Port Selector State Machine (cid:9)
`Figure 11-16. Hub Repeater State Machine (cid:9)
`Figure 11-17. Example Remote-wakeup Resume Signaling With Full-/low-speed Device (cid:9)
`Figure 11-18. Example Remote-wakeup Resume Signaling With High-s