UNITED STATES PATENT AND TRADEMARK OFFICE
`__________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________
`
`ATopTech, Inc.
`Petitioner
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`v.
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`Synopsys, Inc.
`Patent Owner
`___________
`
`Case IPR2014-01145
`Patent 6,237,127
`___________
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`
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`
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 6,237,127
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`__________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________
`
`ATopTech, Inc.
`Petitioner
`
`v.
`
`Synopsys, Inc.
`Patent Owner
`___________
`
`Case IPR2014-01145
`Patent 6,237,127
`___________
`
`
`
`
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 6,237,127
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`Petition for Inter Partes Review of U.S. Patent No. 6,237,127
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`I.
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`TABLE OF CONTENTS
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`IDENTIFICATION OF CLAIMS BEING CHALLENGED (§
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`COMPLIANCE WITH PETITION REQUIREMENTS .......................... 1
`A. Certification the `127 Patent May Be Contested By Petitioner ...... 1
`B.
`Fee For Inter Partes Review (37 C.F.R. § 42.15(a) and § 42.103) .. 1
`C. Mandatory Notices (37 C.F.R. § 42.8) ............................................... 1
`1.
`Real Party-In-Interest (§ 42.8(b)(1)) ........................................... 1
`2.
`Related Matters (§ 42.8 (b)(2)) ................................................... 1
`3.
`Lead And Backup Counsel (§ 42.8 (b)(3)) ................................. 1
`4.
`Service Information (§ 42.8 (b)(4)) ............................................ 2
`D.
`Proof Of Service (§ 42.6(e) and § 42.105(a)) ..................................... 2
`II.
`42.104(B)) ........................................................................................................ 2
`III. RELEVANT INFORMATION CONCERNING THE `127 PATENT .... 2
`A.
`Subject Matter of the `127 Patent ...................................................... 2
`1.
`Calculating Delay Values with Timing Table Propagation ........ 4
`2.
`Tracking “Exceptions” with Timing Table Propagation ............ 4
`3.
`“Exceptions” – Non-Default Timing Constraints ....................... 6
`4.
` ..................................................................................................... 8
`5.
`Circuit Constraints and Applying the Relevant Exceptions. ...... 9
` ............................................................................................................. 10
`1.
`Prosecution ................................................................................ 11
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`B.
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`“Pin-Labelling” – Associating the “Exceptions” with the Circuit
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`Comparing the Delay Values in the Timing Tables to the
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`Effective Filing Date And Prosecution History Of The `127 Patent
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`Belkhale’s Significance was not Recognized During
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`Belkhale Teaches Marking the Circuit Description with
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`Petition for Inter Partes Review of U.S. Patent No. 6,237,127
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`C. How the Challenged Claims Are To Be Construed ....................... 12
`IV. PRECISE REASONS FOR RELIEF REQUESTED ............................... 12
`A.
`Belkhale Anticipates or Renders Obvious Claims 1-11 and 13 ... 12
`1.
`Overview Of Belkhale .............................................................. 12
`B.
`Belkhale Invalidates Claims 1-11 and 13 of the `127 Patent ......... 18
`1.
`Belkhale Teaches The Preamble Of Claim 1 ............................ 18
`2.
`Belkhale Teaches The First Element Of Claim 1 ..................... 19
`a.
`Correct Construction of the First Element of Claim 1 ... 19
`b.
`Exceptions ....................................................................... 20
`Belkhale Teaches The Second Element Of Claim 1 ................. 22
`3.
`a.
`Correct Construction “Timing Tables” .......................... 23
`Belkhale Teaches The Final Element Of Claim 1 .................... 25
`4.
`a.
`The Correct Construction of “Tag” ................................ 27
`Belkhale Anticipates or Renders Obvious Claim 2 .................. 29
`5.
`Belkhale Anticipates or Renders Obvious Claim 3 .................. 30
`6.
`Belkhale Anticipates or Renders Obvious Claim 4 .................. 30
`7.
`Belkhale Anticipates or Renders Obvious Claim 5 .................. 31
`8.
`Belkhale Anticipates or Renders Obvious Claim 6 .................. 33
`9.
`10. Belkhale Anticipates or Renders Obvious Claims 7 & 8 ......... 34
`11. Belkhale Anticipates or Renders Obvious Claim 9 .................. 35
`12. Belkhale Anticipates or Renders Obvious Claims 10 and 11 ... 36
`13. Belkhale Anticipates or Renders Obvious Claim 13 ................ 37
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`Petition for Inter Partes Review of U.S. Patent No. 6,237,127
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`Belkhale Renders Claim 12 Obvious in view of the Knowledge of
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`C.
`One of Ordinary Skill in the Art. ..................................................... 39
`D. Claims 1-13 are Obvious over Belkhale in view of Tom. ............... 40
`1.
`Overview Of Tom ..................................................................... 40
`2. Motivation to combine Tom with Belkhale .............................. 42
`3.
`Belkhale in View of Tom Renders Obvious Claims 1-13 ........ 45
`V. CONCLUSION ............................................................................................ 60
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`Petition for Inter Partes Review of U.S. Patent No. 6,237,127
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`TABLE OF AUTHORITIES
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`Cases
`Statutes
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`KSR Intern. Co. v. Teleflex Inc., 550 U.S. 398 (2007) ............................................ 47
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`Merrill v. Yeomans, 94 U.S. 568 (1876) .................................................................. 28
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`35 U.S.C. § 102 ............................................................................................. 2, 13, 40
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`35 U.S.C. § 103 ................................................................................................... 2, 10
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`35 U.S.C. § 315(b) ..................................................................................................... 1
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`Rules
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`37 C.F.R. § 42.8 (b)(2) ............................................................................................... 1
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`37 C.F.R. § 42.8 (b)(3) ............................................................................................... 1
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`37 C.F.R. § 42.8 (b)(4) ............................................................................................... 2
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`37 CFR § 42.100(b) ................................................................................................. 12
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`Attachment A: Proof of Service of the Petition
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`Attachment B: List of Evidence and Exhibits Relied Upon in Petition
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`Petition for Inter Partes Review of U.S. Patent No. 6,237,127
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`I.
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`COMPLIANCE WITH PETITION REQUIREMENTS
`A.
`Certification the `127 Patent May Be Contested By Petitioner
`Petitioner certifies that (i) Patent No. 6,237,127 (“the `127 patent”) Ex. 1001
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`is available for inter partes review; (ii) it is not barred or estopped from requesting
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`inter partes review of the claims of the `127 patent on the grounds identified
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`herein; and (iii) neither Petitioner nor any privy has filed a civil action or an inter
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`partes review challenging the validity of any claim of the `127 patent.
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`Petitioner certifies this Petition is filed within one year of service of a
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`complaint alleging infringement, thus complying with 35 U.S.C. § 315(b). A
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`complaint was filed on 6/26/2013 (Ex. 1003) and served on 7/12/2013. Ex. 1004.
`B.
`Fee For Inter Partes Review (37 C.F.R. § 42.15(a) and § 42.103)
`Petitioner paid the required fees upon filing. Should any further fees be
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`required, the PTAB is hereby authorized to charge Deposit Account No. 04-1073.
`C. Mandatory Notices (37 C.F.R. § 42.8)
`1. Real Party-In-Interest (§ 42.8(b)(1))
`The real party-in-interest is ATopTech, Inc. (“Petitioner”).
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`2. Related Matters (§ 42.8 (b)(2))
`The `127 patent is a subject of an action styled as Synopsys, Inc. v.
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`ATopTech, Inc., No. 3:13-cv-02965-MMC (N.D. Cal. 2013). Ex. 1003.
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`3. Lead And Backup Counsel (§ 42.8 (b)(3))
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`Lead Counsel
`Jeffrey A. Miller, Reg. No. 35, 287
`millerj@dicksteinshapiro.com
`Tel 650.690.9554; Fax 650.690.9501
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`Backup Counsel
`Paul G. Novak, Reg. No. 55,504
`novakp@dicksteinshapiro.com
`Tel. 310.772.8353; Fax 310.772.8301
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`Petition for Inter Partes Review of U.S. Patent No. 6,237,127
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`4. Service Information (§ 42.8 (b)(4))
`Service may be made to Jeffrey Miller, Dickstein Shapiro LLP, 1841 Page
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`Mill Rd., Palo Alto, CA 94304. Please also email correspondence to
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`millerj@dicksteinshapiro.com and novakp@dicksteinshapiro.com.
`D.
`Proof Of Service (§ 42.6(e) and § 42.105(a))
`Proof of service of this petition is provided in Attachment A.
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`II.
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`IDENTIFICATION OF CLAIMS BEING CHALLENGED (§
`42.104(B))
`Petitioner requests inter partes review of claims 1-13 because: (1) claims 1-
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`11 and 13 are anticipated under 35 U.S.C. § 102 or rendered obvious under 35
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`U.S.C. § 103 by “Timing Analysis with known False Sub Graphs” by Belkhale et
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`al. (“Belkhale”), Ex. 1005; (2) claim 12 is rendered obvious under 35 U.S.C. § 103
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`in view of Belkhale; and (3) claims 1-13 are rendered obvious under 35 U.S.C. §
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`103 by Belkhale in view of US Patent 5,210,700 (“Tom”) Ex. 1006.
`III. RELEVANT INFORMATION CONCERNING THE `127 PATENT
`A.
`Subject Matter of the `127 Patent
`The `127 Patent teaches methods for performing a static timing analysis on a
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`circuit design. Ex. 1001, Title. When an electronic circuit is designed, it often
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`begins with a designer expressing the design of the circuit in a high-level hardware
`description language (HDL)1. Ex. 1001, 1:17-20. Once the circuit description is
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`1 The two most widely used HDL’s are Verilog, introduced by Gateway Design
`Automation in 1985, and VHDL, which resulted from a request from the
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`Department of Defense in 1987. Ghiasi Declaration (Ex. 1007), ¶32.
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`expressed or coded by the designer using a HDL, the description for the circuit is
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`converted/compiled into a circuit that is expressed as a netlist description of gates
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`and transistors. Ex. 1001, 1:23-27. The process of converting/compiling the HDL
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`description of a circuit into a netlist description is well known to those of ordinary
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`skill in the art as “synthesis.” Id. Synthesizing the HDL description of the circuit is
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`more productive compared to a traditional schematic layout because the
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`functionality of the circuit is abstracted. Ex. 1001, 1:21-23.
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`The process of synthesizing a circuit design may be analogized to writing
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`software in C or some other programming language, and compiling the source code
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`into an executable. However, unlike compiling software, a circuit design that is
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`output from the “synthesis” process must be compatible with hardware clocks and
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`the delays associated with signal propagation. Thus, a timing analysis should be
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`done to verify that the actual circuit design produced will perform correctly at the
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`target clock speeds. Ex. 1001, 1:36-40; See also Ex. 1007, ¶34. This timing
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`analysis of the circuit design is the subject of the `127 Patent. Ex. 1001, Title.
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`In particular, the `127 Patent deals with the use of non-default timing
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`constraints, which the `127 Patent calls “exceptions.” Id; Ex. 1007, ¶37. An
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`exception, which may be identified by a user, instructs the timing analyzer that
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`specific paths through the circuit design are not subject to the default timing
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`constraints that the rest of the circuit must adhere to. Ex. 1001, 1:61-64. In the
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`context of the `127 Patent, the timing analysis is performed within the “Design
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`Compiler” shown as block 103 in Fig. 1. Ex. 1001, Fig. 1. As may be seen in Fig.
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`1, the “exceptions” 108 are input into the “Design Compiler.” Id; Ex. 1007, ¶39.
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`1. Calculating Delay Values with Timing Table Propagation
`The timing analysis of the `127 Patent is performed in two steps: (1)
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`calculating the delays through the circuit by propagating timing tables; and (2)
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`comparing the calculated delays to the required timing constraints of the circuit. Ex.
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`1001, 8:37-41. The first step of the timing analysis in the `127 Patent involves
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`propagating the signal availability times through the various paths of the circuit
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`and summing the delays along the way to calculate the minimum and maximum
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`signal availability times at each point in the circuit. Ex. 1001, 8:41-13:2. These
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`minimum and maximum delays are stored in “timing tables.” Ex. 1001, 9:53-58.
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`As the timing tables are propagated through the circuit, the delays at each node are
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`added to the minimum and maximum values of the timing table from the previous
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`node. Ex. 1001, 10:61-11:15, Fig. 5. Delays associated with wire objects between
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`nodes are taken into account by adding a fixed delay to each of the delay values of
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`the timing tables propagated across the wire. Ex. 1001, 12:50-55. To this end, the
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`worst case delays at each point within the circuit are calculated. Ex. 1007, ¶40-41.
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`The `127 Patent teaches the use of a particular kind of “timing table,”
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`referred to as an “RF timing table.” Ex. 1001, 3:7-11. The “RF timing table”
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`includes the minimum and maximum delays associated with the rise and fall (RF)
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`times of the signal. Id. Accordingly, the `127 Patent discloses that an “RF timing
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`table” includes values for the minimum rise time (minRT), maximum rise time
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`(maxRT), maximum fall time (maxFT), and minimum fall time (minFT). Id.
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`2. Tracking “Exceptions” with Timing Table Propagation
`In addition to the delay values stored in each timing table, the `127 Patent
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`teaches that the timing table includes a “tag.” Ex. 1001, 3:11-14. The specification
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`of the `127 Patent teaches that a “tag” is a data structure that comprises “labels.”
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`Ex. 1001, 10:21-25, See also 3:11-15. The `127 Patent teaches that the “labels”
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`within a “tag” may identify a clock. Ex. 1001, 10:21-25. (“In general, a “tag” is a
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`data structure, pointed to by an RF timing table, which contains an identifier
`(which we shall refer to as a “label”)2 that uniquely determines the clock…”). The
``127 Patent also teaches that the labels of a “tag” may identify points in the circuit
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`referenced by an exception. Ex. 1001, 3:29-32. (“For each output pin with an
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`exception flag, a label, representing that pin…is added to the second part of the
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`tag….”) See also 3:11-16, 3:35-39. Thus, the specification of the `127 Patent
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`teaches that tags may comprise any number of labels and labels may identify
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`clocks or points in the circuit referenced by an exception. Ex. 1007, ¶43-45.
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`A “tag” is described by the `127 Patent as being comprised of different types
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`of labels in different locations within the `127 Patent:
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`RF timing tables each have their own “tag” which, in accordance with
`the present invention, has two parts: i) a first part which is loaded
`with a unique identifier for the clock of a launch flip flop; and ii) a
`second part which can contain a variety of “labels.”
`Id. In yet another portion of the `127 Patent, a “tag” is described as:
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`In general, a “tag” is a data structure, pointed to by an RF timing table,
`which contains an identifier (which we shall also refer to as a “label”)
`that uniquely determines the clock driving the flip flop for which the
`RF timing table was created.
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`2 Unless indicated, any bolding, underlining, etc. of text is added by Petitioner.
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`Ex. 1001, 10:21-25.
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`Fig. 12, shown below,
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`illustrates one example of a circuit
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`which has been processed using
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`timing tables and tags. As seen in
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`Fig. 12, at each point along the
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`circuit, a timing table is produced –
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`for example timing tables 1203,
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`1207, 1211, 1217, 1218, etc. Each timing table points to a tag – 1204, 1208, 1212,
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`1219 and 1220, respectively. Those tags include labels to either identify a clock or
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`to identify points within the circuit. Ex. 1007, ¶48-49.
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`To incorporate the use of exceptions within the timing table propagation,
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`each time a timing table is created at a new location in the circuit, a check is made
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`to determine whether the pin at that location is associated with an exception. Ex.
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`1001, 18:31-35. If the pin is part of an exception statement, a label, which
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`represents how the pin is referred to by the exception statement, may be added to
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`the tag. Ex. 1001, 18:42-50. See also Ex. 1007, ¶50.
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`3. “Exceptions” – Non-Default Timing Constraints
`The `127 Patent teaches that exceptions are specified by the circuit designer
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`as individual syntactic units called “exceptions statements.” Ex. 1001, 1:57-61. An
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`“exception statement” is a user-specified command, which for a particular path or
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`set of paths through a circuit section, alters the default timing constraints. Ex. 1001,
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`14:30-54. An exception statement comprises two main components: (i) a “path
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`specification” which specifies the path or paths for which the exception statement
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`applies; and (ii) a “timing alteration” which alters the default timing constraints of
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`the specified paths. Id. The `127 Patent, at Ex. 1001, 14:43-46, gives an example
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`of the syntax for an exception statement:
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`<timing alteration>[value]<path_specification><delimiter>
`The `127 Patent explicitly states that what it calls a “false path” is an
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`example of an exception statement. Ex. 1001, 14:44-54. When using the
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`“set_false_path” exception statement, no additional timing information is needed
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`because a false path always sets the Maximum Allowable Path Delay MAPD to
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`infinity and sets the Shortest Allowable Path Delay SAPD to zero. Id.
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`Accordingly, only a <path_specification> is required when defining a false path
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`exception. Ex. 1001, 16:37-42. The `127 Patent provides the following
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`“exemplary exception” statement: set_false_path –from input1 –to output1;
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`explaining, “[t]his exception alters the default timing constraints, according to the
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`“set_false_path” timing alteration discussed above, for the path beginning at a pin
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`“input1” and ending at a pin “output1.” Id. See also Ex. 1007, ¶51-53.
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`In the numerous examples throughout the `127 Patent, the “set_false_path”
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`command is used as the example illustrating an exception statement. See e.g. Ex.
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`1001, 16:33-17:39, 22:40-24:28, 24:29-25:61. One example is in Fig. 12,
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`illustrated above, where the circuit is subject to the command: set_false_path –
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`through {X1 X2}. See Ex. 1001, 24:47-54. This exception statement indicates that
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`all paths through pin X1 or pin X2 should be subject to the “set_false_path” timing
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`constraint. Ex. 1001, 22:49-55. Accordingly, pins X1 and X2 show up as
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`arguments in the labels within the tags of the timing tables that have passed
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`through pin X1 or pin X2. Ex. 1007, ¶54.
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`4. “Pin-Labelling” – Associating the “Exceptions” with the Circuit
`Referred to as “pin-labelling” in the `127 Patent, the path specified by the
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`exception statements are referenced to the circuit description in two different ways.
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`Ex. 1001, 2:44-46; See also 18:10-22; 21:3-35. The `127 Patent teaches a first way
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`of “pin labelling” where pins in the circuit design that are part of any exception are
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`associated with an “exception flag.” Ex. 1001, 18:10-22; See also 2:44-46. This is
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`illustrated as the “E.F.” (exception flag) elements 1110 and 1111 in Fig. 11. Ex.
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`1007, ¶56.
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`The second way the `127 patent teaches for “pin-labelling” is that an
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`“argument container” is associated with the pin and the argument container may
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`contain a collection of “labels” which may be matched to one or more exception
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`statements. Ex. 1001, 2:48-63; 21:3-35. The `127 Patent explains: “Any form of
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`label, which allows this matching to be accomplished, is suitable.” Ex. 1001, 2:56-
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`57. If the exception deals with a single pin, the label may refer to a single pin. Ex.
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`1001, 2:57-60. If the exception refers to several pins, a label which can represent
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`the entire expression may be used. Ex. 1001, 2:60-62. Figure 12 illustrates the
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`second-way of “pin-labelling” showing the two argument containers 1200 and
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`1201 associated with pins x1 and x2 respectively both containing the label {x1 x2}.
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`The label {x1 x2} is a single label establishing that the exception statement applies
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`to pin x1 OR x2. Ex. 1001, 24:67-25:3. Ex. 1007, ¶57.
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`As the timing tables propagate through the circuit description and pass
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`through points that have been identified during pin labeling, the timing tables may
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`be amended with a label representing the circuit point. Id. The second way of pin
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`labeling may reduce the number of timing tables that need to be propagated. Ex.
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`1001, 25:37-40. A good way to understand the different effects of the two
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`methods of pin labeling is by comparing the difference between Figs. 11 and 12.
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`In Fig. 11, at point X3 and X6, the first-way process results in four separate timing
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`tables each with a different tag. In contrast, in Fig. 12, the second-way process
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`results in only two separate timing tables at points X3 and X6. Ex. 1007, ¶58-59.
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`5. Comparing the Delay Values in the Timing Tables to the Circuit
`Constraints and Applying the Relevant Exceptions.
`Once all the timing tables have been propagated through the circuit
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`description and tagged with the relevant information, the delay values contained in
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`the timing tables are compared to the relevant constraint values. Ex. 1001, 13:66-
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`14:27. In the context of the `127 Patent, the constraint value is the required arrival
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`time at the circuit point. The `127 Patent discloses: “[the] [Maximum Allowable
`Path Delay] MAPDxy and [Shortest Allowable Path Delay] SAPDxy are the default
`timing constraints…alterable by exceptions.” Ex. 1001, 13:60-63. Thus, the `127
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`Patent applies any exceptions identified as being relevant by the tag in the timing
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`table to the MAPD and/or SAPD, and then compares the MAPD and SAPD against
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`the delay values stored in the timing table. Ex. 1001, 13:56-14:26. As already
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`explained above in the section on exceptions, for set_false_path exceptions, the
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`relevant MAPD’s are set to infinity and the relevant SAPD’s are set to zero. Ex.
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`1001, 14:51-53. If the MAPD and SAPD timing constrains are satisfied, the circuit
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`section has successfully passed the static timing analysis. Id. If they are not, some
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`modification may be required. Ex. 1007, ¶60-61.
`B.
`Effective Filing Date And Prosecution History Of The `127 Patent
`The `127 patent issued from Appl. 09/093,817 filed 6/8/1998. No priority or
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`benefit claims were made, making the effective filing date 6/8/1998.
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`The `127 Patent was filed with 13 original claims. Claim 1 was the only
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`independent claim and claims 2-13 depended directly or indirectly from claim 1.
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`On 4/12/2000, an Office Action was mailed in which claims 1-11 were rejected
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`under 35 U.S.C. § 103(a) as being unpatentable over Osler and Tom (Ex. 1006).
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`Ex. 1002, pgs. 131-136. The Examiner stated that Tom taught all the limitations of
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`claim 1 but “exceptions.” Id. Specifically, the Examiner stated that the Tom
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`taught: 1) “marking certain points (clock tags) in a circuit description”; 2)
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`“propagating a plurality of timing tables (clock description & path delay tables…)
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`through the circuit”; and 3) “a first timing table referring to a tag.” Id. The
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`Examiner then stated that Osler taught (i) exceptions, and (ii) referencing
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`exceptions to a circuit description, and thus finding that it would have been
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`obvious for one skilled in the art to combine Tom and Osler. Id. Dependent claims
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`2-11 were also rejected under the combination of Tom and Osler et al. Id.
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`On 8/14/2000, Patent Owner submitted a response to the Office Action. Ex.
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`1002, pgs. 143-147. Patent Owner did not amend the claims, arguing instead that
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`they were patentable over the cited combination, specifically arguing that Osler did
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`not teach the concept of exceptions. Id. Patent Owner argued that the “timing
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`rules” of Osler were not the same as the “exceptions“ of the `127 Patent and
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`therefore, claim 1 and all its dependent claims were patentable. Id. Importantly,
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`Patent Owner did not argue that any of the Examiner’s assertions relating to the
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`teachings of Tom and its application to the claims were incorrect.
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`On 11/20/2000, the Examiner mailed a notice of allowability, accepting the
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`Patent Owner’s arguments that independent claim 1, and thus its dependent claims
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`2-13, was patentable over Tom in view of Osler. Ex. 1002, pgs. 148-153.
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`The Examiner’s stated reasons for allowability were as follows:
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`From the prior arts of record, Tom does not teach the use of
`exceptions or some equivalent. Furthermore, Osler taught timing rules
`that are descriptions of circuit characteristics. These used timing rules
`are described as characterizing either a low level or a synthesized
`design by containing propagation paths and setup and hold tests.
`However, Osler failed to teach exceptions or some other equivalent.
`It is therefore clear that the Examiner allowed claims 1-13 of the `127 Patent
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`because the Examiner thought the “exceptions” limitation was not in the prior art.
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`1. Belkhale’s Significance was not Recognized During Prosecution
`The Examiner was mistaken that exceptions, i.e., non-default timing
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`constraints, were not in the prior art. Belkhale, which was before the Examiner,
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`although not relied on, demonstrates that use of exceptions was well known in the
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`art. Patent Owner cited Belkhale in an information disclosure statement dated
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`December 16, 1998, although no comments were made regarding Belkhale’s
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`teachings. Ex. 1002, pgs. 119-121.
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`Belkhale teaches use of the same “exception” the `127 patent uses as its
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`exemplary exception throughout the patent, although it does not use the term
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`“exception.” That is not surprising since the term “exception” was used mainly by
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`Synopsys (Ex. 1007, ¶38), whereas Belkhale’s work was performed at IBM. Ex.
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`1005, p. 736, note 1. In particular, the `127 patent uses the “set_false_path”
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`command as an exemplary exception. Yet, the set_false_path command was well
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`known in the art, and Belkhale talks extensively about how to incorporate false
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`paths in the context of a static timing analysis of a circuit design. To this end, the
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`Examiner’s reasoning for allowance was clearly in error and the patentability of
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`the claims of the `127 Patent must be reevaluated.
`C. How the Challenged Claims Are To Be Construed
`In this proceeding, claims must be given their broadest reasonable
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`interpretation in light of the specification. 37 CFR § 42.100(b). Petitioner
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`addresses the meaning of claim terms while comparing the claims to the prior art.
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`In particular, Petitioner has addressed the construction of “marking certain points
`
`in a circuit description according to their being referenced by at least a first
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`exception” in Section IV.B.2.a. Petitioner address the construction of the claim
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`term “timing tables” in Section IV.B.3.a. Petitioner addresses the construction of
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`the claim term “tag” in Section IV.B.4.a. Petitioner respectfully submits that the
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`discussion of the meaning of these claim terms is best understood when discussed
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`in the context of the claims, which is found below.
`IV. PRECISE REASONS FOR RELIEF REQUESTED
`A.
`Belkhale Anticipates or Renders Obvious Claims 1-11 and 13
`1. Overview Of Belkhale
`Belkhale was published in a digest of technical papers from the 1995
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`IEEE/ACM International Conference of Computer Aided Design held November
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`5-9, 1995. The digest was available on the shelf of the Arizona State University
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`library at least as early as February 19, 1996. Ex. 1005. Thus, the Belkhale
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`reference is prior art under 35 U.S.C. § 102(b).
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`Belkhale demonstrates that removing false paths, which are paths that are
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`not logically realized by the circuit, prior to timing analysis, was well understood
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`at the time of the `127 Patent. Belkhale states:
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`Thus some of the paths that are considered by the algorithm may not
`be logically realizable. These paths are often referred to as false paths.
`Such paths must be detected and eliminated from consideration from
`the timing analysis. This problem has been studied extensively by
`many researchers, and various interesting algorithms for false path
`detection and elimination have been discovered [2,3,4,5,6,7].
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`…In many cases, users do have an idea that certain paths reported by
`the timing system are really false. This formulation allows the user to
`convey this information to the timing system resulting in a more
`meaningful analysis. As will be shown in Section 2, the ability to
`remove entire sub graphs from consideration from timing is a
`powerful feature.
`Ex. 1005, p. 736. As is seen from this quote, Belkhale teaches Patent Owner’s
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`“exceptions,” the very feature Patent Owner argued during prosecution
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`distinguished its alleged invention from the prior art. Ex. 1007, ¶76-77.
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`Belkhale discloses methods of removing “false sub graphs” from the timing
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`analysis. Belkhale explains that that a “false sub graph” is a representation of one
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`or more false paths. Ex. 1005, p. 736, (“The notion of false sub graphs is more
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`general than the notion of false paths as we can simultaneously remove the
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`consideration of multiple paths.”). Ex. 1007, ¶78.
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`Throughout, Belkhale represents the timing model of the circuit as a graph G.
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`Belkhale gives two example figures of false
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`sub graphs, identified as F1 and F2, for the
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`Timing graph G. Ex. 1005, Fig. 1,
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`reprinted to the right. As seen in Fig. 1,
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`false graph F1 represents all the paths from
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`v1 to v7 and False graph F2 represents all
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`the paths from v1 to v8 within the Timing
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`graph G. Ex. 1007, ¶79-80.
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`Belkhale explains how the false sub graphs may be specified by the user in
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`the form of a set of ordered pair of vertices. Ex. 1005, p. 737. For the false sub
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`graph F1 shown in Fig. 1, Belkhale states the false sub graph could be described by
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`specifying the seven ordered pairs representing the seven non-diagonal false paths
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`of the false sub graph. Id. This would be {(v1, v2), (v1, v3), (v2,v5), (v3, v5), (v2,
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`v4), (v4, v7), (v5, v7)}. Ex. 1007, ¶81.
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`Belkhale then provides a more specific example
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`of a false path specified by the user. Referring to its
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`Figure 2, reprinted here, Belkhale explains that if the
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`control path delays are small, all paths l eading from the
`I1 pin of the first multiplexer MUX1, to the I1 pin of the
`second multiplexer MUX2 are false. Id. Belkhale
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`teaches that this false sub graph may be specified by the user by using the single
`ordered pair {(MUX1)/I1, MUX2/I1)}. Ex. 1005, p. 737. See also Ex. 1007, ¶82-83.
`The next section of Belkhale, Section 3 titled “Algorithm for the problem,”
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`explains how the false sub graphs are tracked and removed during the timing
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`analysis. Belkhale uses the Timing graph G and the false sub graphs F1 and F2 of
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`Figure 1 to go through a
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`working example of its
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`algorithm. The results are
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`represented in Fig. 3:
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`Belkhale explains that its disclosed algorithm computes multiple arrival
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`times (AT) at each node. Ex. 1005, p. 737. The arrival times are the summation of
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`the delay values through the circuit. For the purposes of the example in Figure 1,
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`each edge (the line between two nodes) is equivalent to a delay time of T=1. Ex.
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`1005, Fig. 1. Thus, propagating from V1 to V3 adds a delay of 1. Propagating
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`from V3 to V6 adds another delay of 1 such that propagating from V1 to V6 incurs
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`a delay of 2. If there are multiple paths to the same node that are of different
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`lengths, the timing table may consist of multiple delay values as shown for node v5
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`in the timing table of Fig. 3. Ex. 1005, Fig. 3. See also Ex. 1007, ¶84-85.
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`Belkhale teaches that as the delay values are propagated through the circuit,
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`the different arrival and required times are distinguished by w
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