UNITED STATES PATENT AND TRADEMARK OFFICE
`__________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________
`
`ATopTech, Inc.
`Petitioner
`
`v.
`
`Synopsys, Inc.
`Patent Owner
`___________
`
`Case IPR2014-00xxx
`Patent 6,237,127
`___________
`
`
`
`
`
`DECLARATION OF SOHEIL GHIASI, Ph.D.
`
`IN SUPPORT OF
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 6,237,127
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`
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`Exhibit 1007 - Page 1 of 74
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`TABLE OF CONTENTS
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`“Pin-Labelling” – Associating the “Exceptions” with the Circuit
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`Comparing the Delay Values in the Timing Tables to the
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`INTRODUCTION ......................................................................................... 1
`I.
`EXPERT QUALIFICATIONS AND CREDENTIALS ............................. 1
`II.
`III. BASIS FOR OPINIONS AND MATERIALS REVIEWED ..................... 3
`IV. SUMMARY OF MY OPINIONS ................................................................. 4
`V.
`LEGAL PRINCIPLES .................................................................................. 4
`A. Anticipation .......................................................................................... 5
`B. Obviousness .......................................................................................... 5
`C. Claim Interpretation in Inter Partes Review ................................... 7
`VI. THE TECHNOLOGY DESCRIBED IN THE `127 PATENT .................. 7
`A.
`Background .......................................................................................... 7
`B.
`Subject Matter of the `127 Patent .................................................... 13
`1.
`Calculating Delay Values with Timing Table Propagation ...... 14
`2.
`Tracking “Exceptions” with Timing Table Propagation .......... 15
`3.
`“Exceptions” – Non-Default Timing Constraints ..................... 17
`4.
` ................................................................................................... 18
`5.
`Circuit Constraints and Applying the Relevant Exceptions. .... 20
`VII. EFFECTIVE FILING DATE OF THE `127 PATENT ........................... 20
`VIII. PROSECUTION HISTORY OF THE `127 PATENT ............................. 21
`IX. BELKHALE ANTICIPATES OR RENDERS OBVIOUS CLAIMS 1-11
`AND 13 .......................................................................................................... 23
`A.
`Which is One Type of Exception According to the `127 Patent ... 23
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`Belkhale Teaches Marking of False Paths for Timing Analysis,
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`i
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`Exhibit 1007 - Page 2 of 74
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`B.
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`Belkhale Anticipates or Renders Obvious Claims 1-11 and 13 of
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`Belkhale Teaches Marking the Circuit Description with
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`the `127 Patent ................................................................................... 30
`1.
`Belkhale Teaches The Preamble Of Claim 1 ............................ 30
`2.
`Belkhale Teaches The First Element Of Claim 1 ..................... 31
`a.
`Correct Construction of the First Element of Claim 1 ... 31
`b.
`Exceptions ....................................................................... 32
`Belkhale Teaches The Second Element Of Claim 1 ................. 35
`3.
`a.
`Correct Construction “Timing Tables” .......................... 36
`Belkhale Teaches the Final Element Of Claim 1 ...................... 37
`4.
`a.
`The Correct Construction of “Tag” ................................ 40
`Claim 2 ...................................................................................... 42
`5.
`Claim 3 ...................................................................................... 44
`6.
`Claim 4 ...................................................................................... 44
`7.
`Claim 5 ...................................................................................... 45
`8.
`Claim 6 ...................................................................................... 48
`9.
`10. Claims 7 & 8 ............................................................................. 49
`11. Claim 9 ...................................................................................... 51
`12. Claims 10 and 11....................................................................... 52
`13. Claim 13 .................................................................................... 52
`C.
`One of Ordinary Skill in the Art. ..................................................... 54
`D. Claims 1-13 are Obvious over Belkhale in view of Tom. ............... 56
`1.
`Tom ........................................................................................... 56
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`Belkhale Renders Claim 12 Obvious in view of the Knowledge of
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`ii
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`Exhibit 1007 - Page 3 of 74
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`2. Motivation to Combine ............................................................. 58
`3.
`Belkhale in View of Tom Renders Obvious Claims 1-13 ........ 62
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`iii
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`Exhibit 1007 - Page 4 of 74
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`I, Soheil Ghiasi, declare:
`
`I.
`
`INTRODUCTION
`1.
`I have been retained by ATopTech, Inc. (“Petitioners”) to provide my
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`expert opinions regarding U.S. Patent No. 6,237,127 (“the `127 Patent”). More
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`specifically, I have been asked to give my opinion about the meanings of certain
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`terms of the `127 Patent claims, and to compare the `127 Patent claims to prior art
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`patents and publications. I submit this declaration in support of Petitioner’s
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`petition for inter partes review of the `127 Patent.
`2.
`
`This declaration sets forth my opinions based on my review of the
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``127 Patent, its prosecution history, the prior art discussed herein, and my
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`education and experience. Based on my education, research, training and
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`experience, as summarized herein, I believe I am qualified to render expert
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`opinions on the technical issues regarding the `127 Patent.
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`3.
`
`I am being compensated for my work in this matter. My
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`compensation in no way depends upon the outcome of this proceeding.
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`II. EXPERT QUALIFICATIONS AND CREDENTIALS
`4. My qualifications are set forth in my curriculum vitae, a copy of
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`which is attached as an Appendix A to this declaration, including lists of my
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`journal publications, books I have authored or edited, and my patents
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`5.
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`I am currently an Associate Professor in the Department of Electrical
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`and Computer Engineering at the University of California, Davis (UCD). At UCD,
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`I lead our Laboratory for Embedded and Programmable Systems. I have been a
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`faculty member at UCD since October 2004.
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`
`
`1
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`Exhibit 1007 - Page 5 of 74
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`6.
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`One of the major concentrations of my research to date has been
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`system-level Electronic Design Automation (“EDA”), along with digital system
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`modeling and optimization. In my research, I have also studied high-level
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`synthesis, logic synthesis & optimization, and the placement and routing of digital
`
`circuits. Much of my research is directed to these technical areas, and I am a co-
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`author on 4 papers particularly relevant to techniques described in the `127 Patent.
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`7.
`
`I hold two degrees from the University of California, Los Angeles: (1)
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`a Doctor of Philosophy (Ph.D.) degree in Computer Science (Dissertation Title:
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`Reconfigurable Computing in Heterogeneous Collaborative Systems) earned in
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`2004; (2) a Master of Science degree in Computer Science (with specialization in
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`Computer-aided Design of Digital Circuits; and EDA Tools and Algorithms)
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`earned in 2002. I also hold a Bachelor of Science degree in Computer Engineering
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`from Sharif University of Technology in Tehran, Iran, earned in June 1998.
`
`8.
`
`In 2004, I received the Harry M. Showman Prize, awarded by the
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`University of California, Los Angeles, College of Engineering for excellence in
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`research communication to a broader audience. In 2007, I was nominated for the
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`Best Paper Award at the International Conference on Computer-Aided Design
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`(ICCAD), one of the most respected and leading conferences in EDA/Computer-
`
`Aided Design (CAD).
`
`9.
`
`Since 2011, I have been a Senior Member of the Institute of Electrical
`
`and Electronics Engineers. I am a Member of the Association of Computing
`
`Machinery and its Special Interest Group in Design Automation. I have been a
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`member of technical program committees for many conferences in the general area
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`
`
`2
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`Exhibit 1007 - Page 6 of 74
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`of EDA/CAD over the past 10 years. I have also served as an Associate Editor for
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`several journals and newsletters in the broad area of digital circuits and systems.
`10.
`
`I am the author or co-author on 22 peer-reviewed journal articles and
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`39 conference papers in the fields of electronic design, embedded computing, and
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`EDA technology.
`11.
`
`I have also published articles relevant to the problems addressed by
`
`the patents I reviewed as part of this assignment. I was a co-author on “Optimal
`
`Integer Delay- Budget Assignment on Directed Acyclic Graphs,” published in
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`IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
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`Vol. 23, No. 7 (July 2004), exploring using EDA techniques for the optimal
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`distribution of timing budgets among nodes within a given component while
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`meeting the timing constraint for that component, i.e. slack distribution. Further, I
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`was a co-author of “A Unified Theory of Timing Budget Management,” published
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`in IEEE Transactions on Computer-Aided Design of Integrated Circuits and
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`Systems, Vol. 25, No. 11 (Nov. 2006), that disclosed an EDA framework that
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`improves the area requirements of a netlist while meeting the timing constraints for
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`that netlist.
`12. A full list of my publications is included in my curriculum vitae,
`
`attached as Exhibit A.
`
`III. BASIS FOR OPINIONS AND MATERIALS REVIEWED
`13. The opinions set forth in my declaration are based on my personal
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`knowledge gained from my education, professional experience, and from the
`
`review of the documents and information described in this declaration.
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`
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`3
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`Exhibit 1007 - Page 7 of 74
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`14.
`
`In preparation of this declaration, I have studied
`
`a. U.S. Patent No. 6,237,127 (Ex. 1001);
`b. The file history of U.S. Patent No. 6,237,127 (Ex. 1002);
`
`c. The reference entitled “Timing Analysis with known False Sub
`
`Graphs,” Krishna P. Belkhale and Alexander J. Suess, 1995
`
`IEEE/ACM International Conference of Computer-Aided Design –
`
`Digest of Technical Papers, November 5-9, 1995, San Jose,
`
`California, pgs. 736-740. (“Belkhale”) (Ex. 1005); and
`d. U.S. Patent No. 5,210,700 (“Tom”) (Ex. 1006).
`
`IV. SUMMARY OF MY OPINIONS
`15.
`It is my opinion that claims 1-13 of the `127 Patent are invalid as
`
`anticipated under 35 U.S.C. § 102 or rendered obvious under 35 U.S.C. § 103 by
`
`Belkhale.
`
`16.
`
`It is also my further opinion that claims 1-13 are rendered obvious
`
`under 35 U.S.C. § 103 by Belkhale in view of Tom.
`
`V. LEGAL PRINCIPLES
`17.
`I understand that a claim is invalid, among other things, if it is
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`anticipated under 35 U.S.C. § 102 or obvious under 35 U.S.C. § 103. I understand
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`that the burden of proof in this proceeding is the “preponderance of the evidence”
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`standard, and not the “clear and convincing evidence” standard that is used in
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`court. I understand that the “preponderance of the evidence” standard is lower
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`than the “clear and convincing evidence” standard.
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`
`
`4
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`Exhibit 1007 - Page 8 of 74
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`A.
`18.
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`Anticipation
`I understand that for a claim to be anticipated, every limitation of the
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`claimed invention must be found in a single prior art reference, either expressly or
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`inherently.
`19.
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`I understand that anticipation is determined on a claim-by-claim basis
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`by comparing the claim, as construed, to the prior art.
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`20.
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`I understand that when a claim covers several alternative structures or
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`elements, either generically or as alternatives, the claim is anticipated if any one of
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`the structures or elements within the scope of the claim is disclosed or practiced by
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`a single prior art reference.
`21.
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`I have been informed that if a single prior art reference discloses each
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`and every element of an asserted claim, either expressly or inherently, it anticipates
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`and therefore invalidates that claim under 35 U.S.C. § 102. For a claim element to
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`be inherently present in a prior art reference, I understand that the element must be
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`“necessarily present” in the disclosed apparatus, system, product, or method, and
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`not probably or possibly present.
`B. Obviousness
`22.
`I understand that a claim is invalid for obviousness if the differences
`
`between the claimed subject matter and the prior art are such that the claimed
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`subject matter, taken as a whole, would have been obvious at the time the
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`invention was made (or, in some cases, at the statutory “critical date” of the patent
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`claim) to a person having ordinary skill in the art to which the subject matter
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`pertained.
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`5
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`Exhibit 1007 - Page 9 of 74
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`23.
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`In determining whether a claimed invention is obvious, I understand
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`that one should consider (i) the scope and content of the prior art, (ii) the level of
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`ordinary skill in the relevant art, (iii) the differences between the claimed invention
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`and the prior art, and (iv) whether the claimed invention would have been obvious
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`to one of ordinary skill in the art in light of those differences.
`24.
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`I understand that, historically, the applicable framework for assessing
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`obviousness was whether there was a teaching, suggestion, or motivation, either
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`explicitly or implicitly, in the prior art to combine the teachings of different
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`references. I have been informed that although the claimed subject matter can still
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`be found obvious when that test is satisfied, the obviousness inquiry is actually
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`broader and more flexible than that. One need not identify an explicit teachings,
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`suggestion, or motivation in the prior art. Instead, one can take into account the
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`inferences, creative steps, common knowledge and common sense that a person of
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`ordinary skill in the art would have employed.
`25.
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`I understand that if one of ordinary skill in the art can implement a
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`predictable variation of an apparatus or method prompted by market forces or
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`design incentives, such a variation is obvious. I understand that if a technique has
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`been used to improve one device, and one of ordinary skill in the art would
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`recognize that it would improve similar devices in the same way, using the
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`technique is obvious unless its actual application is beyond ordinary skill. Stated
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`differently, I understand that the proper question is whether one of ordinary skill,
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`facing the wide range of needs created by developments in the field of endeavor,
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`would have seen a benefit to combining the teachings of the prior art.
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`6
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`Exhibit 1007 - Page 10 of 74
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`26.
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`I understand that the person of ordinary skill is a hypothetical person
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`who is presumed to be aware of all of the pertinent art. A person of ordinary skill
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`also has an ordinary level of creativity. I understand that the person of ordinary
`
`skill is not an automaton, and may be able to fit together the teachings of multiple
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`prior art references employing ordinary creativity and the common sense that
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`familiar items may have obvious uses beyond their primary purposes. In many
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`cases, a person of ordinary skill will be able to fit the teachings of multiple prior art
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`together like the pieces of a puzzle. I understand that a patent which claims
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`predictable uses of old elements according to their established functions to achieve
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`predicable results may be found invalid as obvious. I understand that the
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`perspective of one of ordinary skill in the art is used to determine obviousness, as
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`well as anticipation, as discussed above.
`C.
`27.
`
`Claim Interpretation in Inter Partes Review
`I understand that claims in inter partes review are given their broadest
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`reasonable interpretation that is consistent with the patent specification. I provide
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`my opinions regarding the construction of certain terms in the claims of the `127
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`Patent when discussing those claim elements in comparison to the prior art, below.
`
`VI. THE TECHNOLOGY DESCRIBED IN THE `127 PATENT
`A.
`Background
`28. At a high level, electronic design is the process by which engineers
`design electronic devices such as integrated circuits, also known as ICs or chips.1
`
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`1 An IC is a combination of electronic circuits on a single semiconductor, e.g.
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`
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`7
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`Exhibit 1007 - Page 11 of 74
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`EDA software of the kind available from Synopsys, Cadence, Mentor Graphics,
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`and other companies is used by engineers to design and develop the ICs required
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`by a product. The EDA design process is an iterative pipeline of distinct stages in
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`which each stage uses the output of previous stages to further the design. These
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`stages, illustrated below, can be thought of conceptually as corresponding to
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`defining the behavioral design (illustrated with a white background), the structural
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`design (illustrated with a light grey background), and physical design of the chip
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`(illustrated with a dark grey background). As each separate stage progresses, the
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`design is evaluated and often a previous stage is repeated due to an unforeseen
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`impact of a later stage.
`
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`silicon. ICs can be made much smaller than combining independent components to
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`generate the same circuitry. See, e.g., Wikipedia, Integrated Circuit,
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`http://en.wikipedia.org/wiki/Integrated_circuit.
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`
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`8
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`Exhibit 1007 - Page 12 of 74
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`29. The behavioral design defines the operation of a design, the structural
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`design generates logical representations of the operation, and the physical design
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`translates the logical representation into specific circuit elements on the silicon that
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`achieve the function of the behavioral design.
`30. The behavioral design steps create a high level model of an electronic
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`circuit that is capable of performing the required functions and include developing
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`a high level specification, designing an architecture for the IC, and defining the
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`
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`9
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`Exhibit 1007 - Page 13 of 74
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`functional behavior of the components. The specification development is where
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`engineers consider the purpose of the design; design requirements such as cost,
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`fabrication techniques, power, and speed; market requirements and business needs.
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`The architecture design uses the specification to develop the system’s architecture,
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`such as determining the size or the type of instructions the IC will process, the type
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`of data it will compute, its internal memory design, and structure. The functional
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`design considers the specification and architecture to develop the main functional
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`blocks of the IC and the interconnections of those blocks to develop an IC or chip
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`capable of processing the expected input data and creating the desired output.
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`31. The functional design often begins with a designer expressing the
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`design of the circuit in a high-level hardware description language (HDL). The
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``127 patent recognizes this. Ex. 1001, 1:17-20. The two most widely used HDL’s
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`are Verilog, introduced by Gateway Design Automation in 1985, and VHDL,
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`which resulted from a request from the Department of Defense in 1987.
`32.
`
`It is often inefficient and unnecessary for circuit designers to work
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`with the individual circuit elements, such as individual transistors. Instead,
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`designers usually work with pre-defined groups of circuit elements that perform a
`discrete low-level function, such as an OR gate.2 These groups of circuit elements
`
`
`2 An OR gate is a digital logic gate that implements logical disjunction - it behaves
`according to a truth table. A HIGH output (1) results if one or both the inputs to the
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`gate are HIGH (1). If neither input is high, a LOW output (0) results. In another
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`sense, the function of OR effectively finds the maximum between two binary digits,
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`
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`10
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`Exhibit 1007 - Page 14 of 74
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`are referred to as a “cell,3
`based on their functions. Working with cells allows engineers, and the software
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` and these pre-defined cells are organized into libraries
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`tools used by engineers, to more easily handle complex designs.
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`33. Once the circuit description is expressed or coded by the designer
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`using a HDL, the description for the circuit is converted/compiled into a circuit
`
`that is expressed as a netlist description of gates and transistors. Ex. 1001, 1:23-
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`27. The process of converting/compiling the HDL description of a circuit into a
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`netlist description is well known to those of ordinary skill in the art as “synthesis.”
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`Id. Synthesizing the HDL description of the circuit is more productive compared
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`to a traditional schematic layout because the functionality of the circuit is
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`abstracted. Ex. 1001, 1:21-23.
`34. The process of synthesizing a circuit design may be analogized to
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`writing software in C or some other programming language, and compiling the
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`source code into an executable. However, unlike compiling software, a circuit
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`design that is output from the “synthesis” process must be compatible with
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`hardware clocks and the delays associated with signal propagation. As I will
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`discuss below, a timing analysis should be done to verify that the actual circuit
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`design produced will perform correctly at the target clock speeds. Ex. 1001, 1:36-
`
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`just as the complementary AND function finds the minimum.” See e.g., Wikipedia,
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`OR gate, http://en.wikipedia.org/wiki/OR_gate
`3 See, e.g., Wikipedia, Cell (EDA), http://en.wikipedia.org/wiki/Cell_(EDA)
`(describing the abstraction of cells in EDA).
`
`
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`11
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`Exhibit 1007 - Page 15 of 74
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`40. For example, if data is generated at the output pin of the clocked element (the
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`“source” element) but arrives later than it is expected to be clocked into the input
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`pin of the next downstream clocked element (the “sink” element), the data will
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`appear to be too late from the standpoint of the sink element.
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`35. The physical design steps then convert the circuit model into its
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`physical counterpart that can be manufactured into an IC. The steps for creating a
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`physical design include partitioning the design into designated physical areas for
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`particular functions, placing the components in partitions, routing of
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`interconnections between components, and compaction. Partitioning is the process
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`of separating an IC, which may contain millions of transistors, into sub-blocks.
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`Each sub-block is often dedicated to a specific operation or function within the IC,
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`such as memory, instruction decoders, and processing units, and interconnected
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`with other subblocks. Once the chip is partitioned, a placement tool will organize
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`the cells of each sub-block within the physical partition designated for that sub-
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`block. Routing then determines the path for the wires that interconnect those cells.
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`As further described below, routing is often performed at two levels. The first,
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`coarse level is called global routing, which determines a rough path for the wires;
`
`and the second, detailed level is called detailed routing, which determines the
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`precise location for the wires. Compaction is a process where the physical area of
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`the overall design is reduced given the designs constraints.
`36. Timing analysis of the circuit design is the subject of the `127 Patent.
`
`Ex. 1001, Title. Timing analysis of the type described in the `127 patent is
`
`
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`12
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`Exhibit 1007 - Page 16 of 74
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`performed after the “optimization” stage in the flowchart above, but prior to the
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`partitioning, placement and routing stages.
`B.
`Subject Matter of the `127 Patent
`37. The `127 Patent teaches methods for performing a static timing
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`analysis on a circuit design. Ex. 1001, Title. In particular, the `127 Patent deals
`
`with the use of non-default timing constraints, which the `127 Patent calls
`
`“exceptions.” Id. An exception, which may be identified by a user, instructs the
`
`timing analyzer that specific paths through the circuit design are not subject to the
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`default timing constraints that the rest of the circuit must adhere to. Ex. 1001, 1:61-
`
`64.
`
`38. The concept of a non-default timing constraint was well known at the
`
`time of the `127 Patent. However, the term “exception” was used mainly by
`
`Synopsys. Accordingly, very few prior art references used the term, even when
`
`discussing the same concept. As an example, handling false paths, which are paths
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`through the circuit that will never be logically realized, was well known in the art.
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`As another example, setting multi-cycle paths, which are paths through the circuit
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`that are subject to more than one clock cycle instead of the standard single clock
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`cycle, was also well known in the art.
`
`39.
`
`In the context of the `127 Patent, the timing analysis is performed
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`within the “Design Compiler” shown as block 103 in Fig. 1. Ex. 1001, Fig. 1. As
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`may be seen in Fig. 1, the “exceptions” 108 are input into the “Design Compiler.”
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`Id.
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`
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`13
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`Exhibit 1007 - Page 17 of 74
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`1. Calculating Delay Values with Timing Table Propagation
`40. The `127 Patent teaches that its timing analysis is performed in two
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`steps: (1) calculating the delays through the circuit by propagating timing tables;
`
`and (2) comparing the calculated delays to the required timing constraints of the
`
`circuit. Ex. 1001, 8:37-41.
`
`41. The first step of the timing analysis in the `127 Patent involves
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`propagating the signal availability times through the various paths of the circuit
`
`and summing the delays along the way to calculate the minimum and maximum
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`signal availability times at each point in the circuit. Ex. 1001, 8:41-13:2. These
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`minimum and maximum delays are referred to as “timing tables.” Ex. 1001, 9:53-
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`58. As the timing tables are propagated through the circuit, the delays at each node
`
`are added to the minimum and maximum values of the timing table from the
`
`previous node. Ex. 1001, 10:61-11:15, Fig. 5. Delays associated with wire objects
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`between nodes are taken into account by adding a fixed delay to each of the delay
`
`values of the timing tables propagated across the wire. Ex. 1001, 12:50-55. To this
`
`end, the worst-case delays at each point within the circuit are calculated.
`42. The `127 Patent teaches the use of a particular kind of “timing table,”
`
`referred to by the `127 Patent as an “RF timing table.” Ex. 1001, 3:7-11. The “RF
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`timing table” includes the minimum and maximum delays associated with the rise
`
`and fall (RF) times of the signal. Id. Accordingly, the `127 Patent discloses that
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`an “RF timing table” includes values for the minimum rise time (minRT),
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`maximum rise time (maxRT), maximum fall time (maxFT), and minimum fall time
`
`(minFT). Id.
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`
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`14
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`Exhibit 1007 - Page 18 of 74
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`2. Tracking “Exceptions” with Timing Table Propagation
`In addition to the delay values stored in each timing table, the `127
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`43.
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`Patent teaches that the timing table includes a “tag.” Ex. 1001, 3:11-14. The
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`specification of the `127 Patent teaches that a “tag” is a data structure that
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`comprises “labels.” Ex. 1001, 10:21-25 and 3:11-15.
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`44. The `127 Patent teaches that the “labels” within a “tag” may identify a
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`clock. Ex. 1001, 10:21-25. (“In general, a “tag” is a data structure, pointed to by an
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`RF timing table, which contains an identifier (which we shall refer to as a “label”)
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`that uniquely determines the clock…”).
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`45. The `127 Patent also teaches that the labels of a “tag” may identify
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`points in the circuit referenced by an exception. Ex. 1001, 3:29-32. (“For each
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`output pin with an exception flag, a label, representing that pin…is added to the
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`second part of the tag….”). See also 3:11-16, 3:35-39. Thus, the specification of
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`the `127 Patent teaches that tags may comprise any number of labels, and labels
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`may identify clocks or points in the circuit referenced by an exception.
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`46. A “tag” is described by the `127 Patent as being comprised of
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`different types of labels in different locations within the `127 Patent:
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`RF timing tables each have their own “tag” which, in accordance with
`the present invention, has two parts: i) a first part which is loaded
`with a unique identifier for the clock of a launch flip flop; and ii) a
`second part which can contain a variety of “labels.”
`Ex. 1001, 3:11-16
`47.
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`In another portion of the `127 Patent, a “tag” is described as:
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`In general, a “tag” is a data structure, pointed to by an RF timing table,
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`
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`15
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`Exhibit 1007 - Page 19 of 74
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`
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`which contains an identifier (which we shall also refer to as a “label”)
`that uniquely determines the clock driving the flip flop for which the
`RF timing table was created.
`Ex. 1001, 10:21-25.
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`48. Fig. 12, shown below, illustrates one example of a circuit which has
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`been processed using timing tables and tags.
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`
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`49. As seen in Fig. 12, at each point along the circuit, a timing table is
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`produced – for example timing tables 1203, 1207, 1211, 1217, 1218, etc. Each
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`timing table points to a tag – 1204, 1208, 1212, 1219 and 1220, respectively.
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`Those tags include labels to either identify a clock or to identify points within the
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`circuit.
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`
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`16
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`Exhibit 1007 - Page 20 of 74
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`50. To incorporate the use of exceptions within the timing table
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`propagation, each time a timing table is created at a new location in the circuit, a
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`check is made to determine whether the pin at that location is associated with an
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`exception. Ex. 1001, 18:31-35. If the pin is part of an exception statement, a label,
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`which represents how the pin is referred to by the exception statement, may be
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`added to the tag. Ex. 1001, 18:42-50.
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`3. “Exceptions” – Non-Default Timing Constraints
`51. The `127 Patent teaches that exceptions are specified by the circuit
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`designer as individual syntactic units called “exceptions statements.” Ex. 1001,
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`1:57-61. As I mentioned, the term “exceptions” was somewhat unique to tools
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`offered by Synopsys. Regardless, according the `127 Patent, an “exception
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`statement” is a user-specified command, which for a particular path or set of paths
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`through a circuit section, alters the default timing constraints. Ex. 1001, 14:30-54.
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`An exception statement comprises two main components: (i) a “path specification”
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`which specifies the path or paths for which the exception statement applies; and (ii)
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`a “timing alteration” which alters the default timing constraints of the specified
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`paths. Id.
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`52. The `127 Patent, at Ex. 1001, 14:43-46, gives an example of the
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`syntax for an exception statement:
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`<timing alteration>[value]<path_specification><delimiter>
`53. The `127 Patent states that what it calls a “false path” is an example of
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`an exception statement. Ex. 1001, 14:44-54. When using the “set_false_path”
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`exception statement, no additional timing information is needed because a false
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`
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`17
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`Exhibit 1007 - Page 21 of 74
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`path always sets the Maximum Allowable Path Delay MAPD to infinity and sets
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`the Shortest Allowable Path Delay SAPD to zero. Id. Accordingly, only a
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`<path_specification> is required when defining a false path exception. Ex. 1001,
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`16:37-42. The `127 Patent provides the following “exemplary exception”
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`statement: set_false_path –from input1 –to output1; explaining, “[t]his exception
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`alters the default timing constraints, according to the “set_false_path” timing
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`alteration discussed above, for the path beginning at a pin “input1” and ending at a
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`pin “output1.” Id.
`54.
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`In the numerous examples throughout the `127 Patent, the
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`“set_false_path” command is used as the example illustrating an exception
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`statement. See e.g. Ex. 1001, 16:33-17:39, 22:40-24:28, 24:29-25:61. One
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`example is in Fig. 12, illustrated above, where the circuit is subject to the
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`command: set_false_path –through {X1 X2}. See Ex. 1001, 24:47-54. This
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`exception statement indicates that all paths through pin X1 or pin X2 should be
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`subject to the “set_false_path” timing constraint. Ex. 1001, 22:49-55. Accordingly,
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`pins X1 and X2 show up as arguments in the labels within the tags of the timing
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`tables that have passed through pin X1 or pin X2.
`55. The other exception statement example that is used in the `127 Patent
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`is the “set