`Patent No. 6,237,127
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`_________________________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`_________________________
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`ATOPTECH, INC.
`Petitioner
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`v.
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`SYNOPSYS, INC.
`Patent Owner
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`_________________________
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`
`
`Case IPR2014-01145
`Patent No. 6,237,127
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`_________________________
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`
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`PATENT OWNER’S RESPONSE
`PURSUANT TO 37 C.F.R. § 42.120
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`
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`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`TABLE OF CONTENTS
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`Page
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`I.
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`II.
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`B.
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`V.
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`PRELIMINARY STATEMENT .................................................................... 1
`THE ALLEGED GROUNDS FOR UNPATENTABILITY ......................... 4
`III. THE ’127 PATENT AND CLAIM CONSTRUCTION ................................ 5
`A. Overview of the ’127 Patent ................................................................. 5
`B.
`Claim Construction of “Timing Table” ................................................ 8
`IV. OVERVIEW OF THE CITED REFERENCES ........................................... 11
`A.
`Belkhale .............................................................................................. 11
`Tom ..................................................................................................... 15
`THE PETITION FAILS TO PRESENT A PRIMA FACIE CASE OF
`UNPATENTABILITY OF CLAIMS 1-4 AND 7-11 .................................. 16
`A.
`The Petition fails to prove that independent claim 1 is obvious
`over Belkhale. ..................................................................................... 16
`1.
`The Petition fails to provide evidence that Belkhale
`discloses “propagating a plurality of timing tables.” ............... 17
`The Petition’s allegations that Belkhale’s “set attribute”
`is propagated through a circuit description do not provide
`evidence that Belkhale discloses propagating a reference
`to a tag. ..................................................................................... 20
`Belkhale does not disclose propagating a reference to a
`tag through a circuit description. ............................................. 22
`The Petition fails to provide evidence that Belkhale
`discloses “a tag comprising at least a first label indicating
`a marked point in the circuit description, through which
`the table has been propagated.” ............................................... 24
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`2.
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`3.
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`4.
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`-i-
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`TABLE OF CONTENTS
`(continued)
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`Page
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`5.
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`2.
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`2.
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`3.
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`4.
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`B.
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`C.
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`The Petition does not address multiple Graham factors
`and thus fails to present a prima facie case of
`obviousness over Belkhale. ...................................................... 31
`The Petition fails to prove that independent claim 1 is obvious
`over the combination of Belkhale and Tom. ...................................... 40
`1.
`Tom does not cure the deficiencies of Belkhale. ..................... 40
`A person of ordinary skill in the art would not have been
`motivated to combine Belkhale and Tom. ............................... 42
`The Petition fails to prove that dependent claims 2-4 and 7-11
`are obvious over Belkhale or the combination of Belkhale and
`Tom. .................................................................................................... 45
`1.
`Neither Belkhale nor the combination of Belkhale and
`Tom discloses or renders obvious the limitations of
`dependent claim 2. ................................................................... 45
`Neither Belkhale nor the combination of Belkhale and
`Tom discloses or renders obvious the limitations of
`dependent claim 3. ................................................................... 48
`Neither Belkhale nor the combination of Belkhale and
`Tom discloses or renders obvious the limitations of
`dependent claim 10. ................................................................. 49
`Neither Belkhale nor the combination of Belkhale and
`Tom discloses or renders obvious the limitations of
`dependent claim 11. ................................................................. 49
`VI. CONCLUSION ............................................................................................. 50
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`-ii-
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`CASES
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`TABLE OF AUTHORITIES
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`Page
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`Apple, Inc. v. Int’l Trade Comm’n
`725 F.3d 1356 (Fed. Cir. 2013) .......................................................................... 32
`
`Ariosa Diagnostics v. Verinata Health, Inc.,
`IPR2013-00276, Paper 43 (P.T.A.B. October 23, 2014) .............................. 33, 34
`
`Graham v. John Deere Co.,
`383 U.S. 1 (1966) .............................................................................. 31, 32, 34, 38
`
`In re Kahn,
`441 F.3d 977 (Fed. Cir. 2006) ............................................................................ 34
`
`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007) ...................................................................................... 31, 32
`
`Litton Indus. Prods., Inc. v. Solid State Sys. Corp.,
`755 F.2d 158 (Fed. Cir. 1985) .......................................................... 35, 36, 38, 39
`
`Okajima v. Bourdeau,
`261 F.3d 1350 (Fed. Cir. 2001) ........................................................ 35, 36, 37, 38
`
`Travelocity.com L.P. v. Cronos Techs., LLC,
`CBM2014-00082, Paper 10 (P.T.A.B. September 15, 2014) ............................. 32
`
`Valeo N. Am., Inc. v. Magna Elecs., Inc.,
`IPR2014-01206, Paper 13 (P.T.A.B. December 23, 2014) .......................... 32, 33
`
`Zetec, Inc. v. Westinghouse Elec. Co., LLC,
`IPR2014-00384, Paper 10 (P.T.A.B. July 23, 2014). ......................................... 35
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`-iii-
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`STATUTES
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`TABLE OF AUTHORITIES
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`(continued)
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`Page
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`35 U.S.C. § 103 ............................................................................4, 31, 35, 36, 38, 40
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`35 U.S.C. § 312(a)(3) ................................................................................... 24, 30, 50
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`35 U.S.C. § 316(e) ............................................................................................... 1, 19
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`
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`OTHER AUTHORITIES
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`37 C.F.R. § 42.100(b) ................................................................................................ 8
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`37 C.F.R. § 42.104(b) ........................................................... 1, 19, 24, 30, 31, 33, 50
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`37 C.F.R. § 42.120 ..................................................................................................... 1
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`-iv-
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`Pursuant to the Board’s Decision – Institution of Inter Partes Review (Paper
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`No. 7) (“Decision”), entered January 21, 2015, and 37 C.F.R. § 42.120, Patent
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`Owner Synopsys, Inc. (“Synopsys” or “Patent Owner”) submits this Response in
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`opposition to the Petition for Inter Partes Review of United States Patent No.
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`6,237,127 (the “’127 patent”) filed by ATopTech, Inc. (“ATopTech” or
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`“Petitioner”).
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`I.
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`PRELIMINARY STATEMENT
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`Under 35 U.S.C. § 316(e), Petitioner ATopTech has “the burden of proving
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`a proposition of unpatentability by a preponderance of the evidence.” And to
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`prove a proposition of unpatentability, the Petition must specify where each
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`element of a challenged claim is found in the prior art. 37 C.F.R. § 42.104(b)(4).
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`The burden is thus placed squarely on ATopTech to provide evidence establishing
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`that all limitations of the challenged claims are met in the prior art. But the
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`Petition suffers from substantial deficiencies, and ATopTech falls short of meeting
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`its burden.
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`The ’127 Patent discloses a method for performing static timing analysis on
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`a digital electronic circuit. Ex. 1001, Abstract. In the static timing analysis, timing
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`tables are propagated through a circuit description. Id. at 9:58-13:2. Such timing
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`tables include delay values, e.g., minimum rise time (minRT), maximum rise time
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`(maxRT), minimum fall time (minFT), and maximum fall time (maxFT) values, as
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`
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`disclosed at 9:54-57 of the ’127 Patent, and illustrated in Figure 4A:
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`
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`The minRT, maxRT, minFT, and maxFT delay values are propagated through the
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`circuit description as part of the static timing analysis. Id. at 9:58-13:2.
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`But the propagation of timing tables in the ’127 Patent does not involve the
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`propagation of only delay values. Rather, delay values and other additional
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`information are propagated through a circuit description. The additional
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`information that is propagated through the circuit description includes at least a
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`reference to a “tag.” A tag is a data structure that includes a “label,” and the label
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`identifies a point in the circuit description through which the timing table has been
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`propagated. Id., 3:29-32, 10:21-25, 18:23-50.
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`Propagating a reference to a tag through a circuit description is illustrated,
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`for example, in Figure 11 of the ’127 Patent:
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`-2-
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`This annotated portion of Figure 11 shows a timing table 1118 and a tag 1119. As
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`shown in the annotation above, the timing table refers to the tag, and the tag
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`includes a label 1121 indicating a marked point (“x1”) in a circuit description.
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`Ex. 1001, 23:53-60. When the timing table is propagated through the circuit
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`description, the reference to the tag is also propagated through the circuit
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`description. Id., 23:66-24:28, Fig. 11.
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`This feature—propagating a reference
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`to a
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`tag
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`through a circuit
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`description—is required by the claims of the ’127 Patent. Specifically,
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`independent claim 1 recites propagating a plurality of timing tables through a
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`circuit description, where at least one of the propagated timing tables “refers to a
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`tag comprising at least a first label indicating a marked point in the circuit
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`description.”
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`Petitioner fails to recognize this requirement of the claims. This is
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`evidenced, for example, in Petitioner’s proposed claim construction for “timing
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`table.” Petition at 23-24. Petitioner alleges that propagating delay values only
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`satisfies the “propagating a plurality of timing tables” limitation. Id. at 24. This is
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`-3-
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`incorrect: as explained above, the propagating step of claim 1 requires propagating
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`a “refer[ence] to a tag” through a circuit description.
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`Petitioner’s misunderstanding of the claim is fatal to its unpatentability
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`arguments. Having failed to recognize that claim 1 requires propagating a
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`“refer[ence] to a tag,” Petitioner provides no evidence that the prior art discloses
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`this feature. In particular, Petitioner relies on Belkhale as allegedly disclosing the
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`“propagating” limitation but provides no evidence that this reference discloses
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`propagating a reference to a tag. The Petition thus fails to provide evidence
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`establishing that all claim limitations are disclosed in the prior art.
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`The Petition is deficient in other respects, as explained below. For at least
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`these reasons, the Board should enter judgment that claims 1-4 and 7-11 of the ’127
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`patent are patentable over Belkhale and the combination of Belkhale and Tom.
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`II. THE ALLEGED GROUNDS FOR UNPATENTABILITY
`The Institution Decision sets forth the following alleged grounds for
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`unpatentability in this trial:
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` Claims 1-4 and 7-11 are unpatentable under 35 U.S.C. § 103 over
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`Belkhale; and
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` Claims 1-4 and 7-11 are unpatentable under 35 U.S.C. § 103 over
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`Belkhale and Tom.
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`-4-
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`Decision at 25. The Board denied all other grounds that ATopTech presented in its
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`Petition. Id.
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`III. THE ’127 PATENT AND CLAIM CONSTRUCTION
`A. Overview of the ’127 Patent
`The ’127 Patent discloses a method for performing static timing analysis on a
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`digital electronic circuit. Ex. 1001, Abstract; see also Ex. 2004, ¶¶ 39-52. The
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`static timing analysis may be used, for example, to verify that the circuit will
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`perform correctly at target clock speeds. Ex. 1001, 1:36-40. The ’127 Patent
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`describes the use of “exceptions,” which allow a circuit designer to specify certain
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`paths through a circuit as being subject to non-default timing rules. Id., 7:57-59.
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`Using exceptions, certain paths through the circuit can be subject to less
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`demanding timing requirements. Id., 8:1-8.
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`To incorporate exceptions in the static timing analysis, a “pin-labelling” step
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`is performed. Pin-labelling involves marking points in a circuit description
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`according to their being referenced by an exception. Id., 2:40-43, 23:1-7. Figure 11
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`of
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`the ’127 Patent shows pin-labelling of circuit points with exception
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`flags 1110, 1111:
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`-5-
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`After the marking of the circuit description with the exception flags, timing
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`tables are propagated through the marked circuit description. Ex. 1001, 9:58-13:2,
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`23:8-17. The propagation of timing tables is used to determine, for example, an
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`amount of time required to propagate a signal from an output of a “launch” flip-flop
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`to an input of a “capture” flip-flop of the circuit description. Id., 12:50-13:2. The
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`timing tables described in the ’127 Patent include multiple delay values. Id., 9:54-
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`57. As the timing tables are propagated through the circuit description, the delay
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`values at each circuit node are added to corresponding delay values of the timing
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`table from the previous node. Id., 9:58-13:2.
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`When a timing table propagates through a point in the circuit description
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`marked by an exception flag, a tag to which the timing table refers is updated to
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`-6-
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`indicate the marked point through which the table propagated. See, e.g., id., 23:39-
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`60. For example, in Figure 11, in propagating a timing table through the marked
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`point “x1,” timing table 1118 is generated. Id. Because the point x1 was
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`previously marked with the exception flag 1110, the tag 1119 to which the table
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`1118 refers is updated to indicate the marked point x1 through which the table
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`1118 propagated:
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`
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`After the propagation of the timing tables through the circuit description, a
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`second phase of the timing analysis, relative constraint analysis, is performed. Ex.
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`1001, 13:3-4. Relative constraint analysis involves the comparison of the delay
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`values included in the timing tables with the timing constraints of the circuit. Id.,
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`13:66-14:27. For example, the ’127 Patent describes maximum allowable path
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`delays (MAPDs) and shortest allowable path delays (SAPDs), which are timing
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`constraints for a path of the circuit that may be altered based on exceptions. Id.,
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`-7-
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`13:34-63, 14:30-38. The delay values stored in the timing tables are compared to
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`the MAPD and SAPD values, and if the MAPD and SAPD timing constraints are
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`satisfied, the circuit has passed the static timing analysis. Id., 13:56-14:26.
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`B. Claim Construction of “Timing Table”
`Pursuant to 37 C.F.R. § 42.100(b), and solely for the purposes of this review,
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`Petitioner construes the claim language such that the claims are given their broadest
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`reasonable interpretation, as understood by a person of ordinary skill in the art
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`(POSITA) at the earliest claimed priority date and consistent with the disclosure of
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`the ’127 patent. The earliest claimed priority date of the ’127 patent is June 8, 1998.
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`The ’127 patent is directed to systems and methods for performing static timing
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`analysis on a digital electronic circuit. See Ex. 1001, Abstract. The POSITA,
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`working on static timing analysis systems and methods in June 1998, would have a
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`minimum of a Bachelor of Science degree in Electrical Engineering, Computer
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`Engineering, or a closely-related field. See Ex. 2004, Declaration of Dr. Martin
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`Walker, ¶ 22. The POSITA also would have a minimum of one to two years of
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`professional experience in digital electronic circuit design and analysis. Id.
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`Independent claim 1 recites the step of “propagating a plurality of timing
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`tables through the circuit description.” In the Institution Decision, the Board
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`construed “timing table” to be a “table having a timing value.” Decision at 7. The
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`Board’s construction effectively adopts Petitioner’s proposed construction of this
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`-8-
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`term. Specifically, Petitioner argues that “the broadest reasonable interpretation of
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`‘timing table’ is not limited to the four values disclosed as an ‘RF timing table’ in
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`the ’127 Patent but refers to the propagation of any delay value.” Petition at 24.
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`Under the Petitioner’s construction, the propagation of a single delay value would
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`be a propagation of a “timing table.” And under the Petitioner’s construction, the
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`propagation of multiple delay values, without any additional information, would
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`meet the “propagating a plurality of timing tables” limitation.
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`Patent Owner submits that the Petitioner’s construction contradicts the
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`language of independent claim 1 and is thus improper. Contrary to the Petitioner’s
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`assertion, the “propagating a plurality of timing tables” limitation cannot be met by
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`propagating only delay values through a circuit description. Rather, to meet the
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`“propagating” limitation, at least one of the propagated timing tables must include
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`certain additional information. The language of claim 1 makes this evident:
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`wherein at least a first timing table, of the plurality of timing
`tables, refers to a tag comprising at least a first label indicating a
`marked point in the circuit description . . . .
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`As shown above, at least one of the timing tables that is propagated through the
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`circuit description must “refer[] to a tag.” A timing table that “refers to a tag”
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`cannot consist of only delay values. Rather, such a timing table must include at
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`least some additional information, i.e., a reference to a tag. See Ex. 2004, ¶¶ 62-63.
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`-9-
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`Based on the plain language of the claims, Patent Owner submits that the
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`broadest reasonable interpretation of “propagating a plurality of timing tables
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`through the circuit description” requires propagating a reference to a tag through a
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`circuit description. Petitioner’s proposed claim construction, which omits this
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`requirement, contradicts the language of claim 1 and is thus improper.
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`Patent Owner further submits that the Petitioner’s construction contradicts
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`the plain meaning of the term “table” and is thus improper for this additional
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`reason. As noted above, under Petitioner’s proposed construction, the propagation
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`of a single delay value would be a propagation of a “timing table.” But under its
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`plain and ordinary meaning, a table must include a set of data, i.e., more than a
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`single data item. This is consistent with the term’s use in the ’127 Patent and is
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`also consistent with the term’s ordinary usage. See Ex. 2004, ¶¶ 64-65. For
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`example, the ’127 Patent discloses tables having multiple data items:
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`The RF timing tables propagated are comprised of the following
`four values: minimum rise time (minRT), maximum rise time
`(maxRT), minimum fall time (minFT) and maximum fall time
`(maxFT).
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`Ex. 1001, 9:54-57. The ’127 Patent includes no disclosure of a table having only a
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`single data item.
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`Consistent with the term’s use in the ’127 Patent, the Microsoft Press
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`Computer Dictionary (Third Edition 1997) defines “table” as “a data structure
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`-10-
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`usually consisting of a list of entries.” Ex. 2006 at 459. Similarly, The Oxford
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`Desk Dictionary (American Edition 1995) defines “table” as a “set of facts or
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`figures in columns, etc.” Ex. 2001 at 585. Merriam Webster’s Collegiate
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`Dictionary (10th ed. 1995) defines “table” as “a systematic arrangement of data
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`usu. in rows and columns for ready reference.” Ex. 2002 at 1198.
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`In summary, Petitioner’s construction for “timing table” is inconsistent with
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`the language of the claims and contradicts the plain meaning of the term “table.”
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`Under the broadest reasonable interpretation, the “propagating a plurality of timing
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`tables” limitation should be construed as requiring the propagation of a reference
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`to a tag. And under the broadest reasonable interpretation, a “timing table” should
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`be construed as requiring multiple timing values.
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`IV. OVERVIEW OF THE CITED REFERENCES
`A. Belkhale
`Belkhale is related to static timing analysis of circuits. Ex. 1005 at 6; see
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`
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`also Ex. 2004, ¶¶ 66-71. Belkhale discloses that a problem with conventional static
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`timing analysis procedures is that they “do[] not take logic into account.” Ex. 1005
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`at 6. Specifically, conventional static timing analysis procedures may consider
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`paths of a circuit description that are not “logically realizable.” Id. Belkhale uses
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`the term “false path” to refer to a path that is not logically realizable. Id. Belkhale
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`-11-
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`discloses that false paths “must be detected and eliminated from consideration
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`from the timing analysis.” Id.
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`To eliminate multiple false paths from a timing analysis, Belkhale discloses
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`the use of “false sub graphs.” Ex. 1005 at 6. Belkhale explains that a false sub
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`graph “is, in general, equivalent to many individual [false] paths.” Id. at 9; see
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`also id., disclosing example in which 29 false sub graphs include 30,000 false
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`paths. Example false sub graphs F1 and F2 for a timing graph G are illustrated in
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`Figure 1 of Belkhale:
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`Ex. 1005 at 10. False sub graph F1 represents seven (7) false paths, which may be
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`specified as ordered pairs (v1, v2), (v1, v3), (v2, v4), (v2, v5), (v3, v5), (v4, v7),
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`and (v5, v7).1 Id. at 7. False sub graph F2 also represents seven false paths, which
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`may be specified as ordered pairs (v1, v2), (v1, v3), (v2, v5), (v3, v5), (v3, v6),
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`(v5, v8), and (v6, v8). Id.
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`
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`To determine an amount of time required to propagate a signal from an input
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`node of a timing graph (e.g., node v1 of Belkhale’s timing graph G) to an output
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`node of the timing graph (e.g., node v9), Belkhale discloses “Algorithm 1.”
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`Ex. 1005 at 7. The algorithm is used to calculate one or more arrival times at each
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`node of the timing graph. Id. An example output of the algorithm is depicted in
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`Figure 3 of Belkhale:
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`Id. at 10. In Figure 3, a first row includes arrival times (AT) for each of the nodes
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`v1-v9 of the timing graph G, as computed by the algorithm, and a second row
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`1 Belkhale indicates that false sub graphs F1 and F2 do not include diagonal edges.
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`Ex. 1005 at 7. Thus, false sub graph F1 does not include paths specified by
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`ordered pairs (v1, v5) and (v2, v7). Likewise, false sub graph F2 does not include
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`paths specified by ordered pairs (v1, v5) and (v3, v8).
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`-13-
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`includes required times (RAT) for each of the nodes. Id. An AT value of a node is
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`compared to an RAT value of the node to determine a “local measure of the
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`magnitude of the timing violation.” Id. at 6.
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`Each AT value in Figure 3 is associated with a “set attribute,” where the set
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`attribute “gives the set of false sub graphs the signal has come through.” Ex. 1005 at
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`7. In the example presented in Figure 1 of Belkhale, including false sub graphs F1
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`and F2, Belkhale’s set attribute is used to indicate false sub graphs as follows:
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`Set Attribute False Sub Graph
`{}
`Neither F1 nor F2
`{1}
`F1
`{2}
`F2
`{1,2}
`F1 and F2
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`
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`To illustrate an application of Belkhale’s set attribute, reference is made to Figure 3
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`of Belkhale. In the first row of Figure 3, node v4 has an entry (2, {1}). The value
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`“2” is an arrival time, and the value {1} is a set attribute indicating the false sub
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`graph F1. The notation (2, {1}) thus means that in propagating a signal from node
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`v1 to v4 through the false sub graph F1, there is a delay of 2 timing units.
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`In instances where the algorithm computes multiple arrival times for a given
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`node, the different arrival times “are distinguished based on a set attribute.” Id. at 7.
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`For example, in the first row of Figure 3, node v5 has multiple arrival times “1” and
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`-14-
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`“2.” The arrival time “1” is associated with a null ({}) set attribute, and the arrival
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`time “2” is associated with a {1,2} set attribute.
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`Tom
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`B.
`Tom discloses methods for performing automatic delay adjustment in static
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`
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`timing analysis procedures. Ex. 1006, Title; see also Ex. 2004, ¶¶ 72-76. Tom
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`discloses that static timing analysis includes “propagating maximum delays from
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`the inputs to the outputs of a design in a single pass through the design.” Ex. 1006,
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`1:29-31. A problem in the static timing analysis may occur if “data is generated at
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`the output pin of [a] clocked element (the “source” element) later than it is
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`expected to be clocked into the input pin of [a] next downstream clocked element
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`(the “sink” element), [because] the data will appear to be too late from the
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`standpoint of the sink latch.” Id., 1:34-39. This problem may be resolved “by
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`making a timing adjustment to the delay value which is propagated out of the
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`output pin of the source latch. The timing adjustment is made by subtracting a
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`clock cycle from the delay value so that the data will appear to have been clocked
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`out of the output pin during the clock cycle preceding that during which it is
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`clocked into the downstream input pin.” Id., 1:39-46.
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`Tom discloses that logic designs may employ “multiple-phase system
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`clocking in which the operations of clocked elements are controlled by a plurality
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`of clock signals.” Ex. 1006, 2:15-17. Making a timing adjustment, as described
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`above, may be “a difficult task” in systems with multiple-phase system clocking.
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`Id., 3:34-37. Tom discloses that this task can be made less difficult by
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`“(1) associating clock information with the delay values which are propagated
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`through the logic design, (2) propagating multiple delay values downstream in the
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`logic design . . . , and (3) using the clock information associated with a delay to
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`automatically adjust [the delay value] as needed.” Id., 4:65-5:6.
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`Tom further discloses that a “clock tag” is associated with each delay value
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`in a logic network. Id., 5:9-10. The clock tag “provides information about how a
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`signal represented by the delay value was generated by a clocked circuit element.
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`In FIG. 3, a clock tag is simply the name of the clock signal which operates the
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`clocked element generating the signal with which the clock tag is associated.”
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`Id., 5:10-15.
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`V. THE PETITION FAILS TO PRESENT A PRIMA FACIE CASE OF
`UNPATENTABILITY OF CLAIMS 1-4 AND 7-11
`A. The Petition fails to prove that independent claim 1 is obvious
`over Belkhale.
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`The Petition alleges that independent claim 1 is obvious over Belkhale.
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`Petition at 18-28. As explained below, the Petition fails to (i) provide evidence
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`that Belkhale discloses all limitations of the claim, and (ii) articulate the differences
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`between Belkhale and the claimed invention, among other deficiencies. For at least
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`-16-
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`these reasons, the Petition fails to set forth a prima facie case that claim 1 is obvious
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`over Belkhale.
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`1.
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`The Petition fails to provide evidence that Belkhale discloses
`“propagating a plurality of timing tables.”
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`Independent claim 1 requires “propagating a plurality of timing tables
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`through the circuit description.” As noted (see Section III.B, supra), this limitation
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`cannot be met by propagating only delay values through a circuit description.
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`Rather, to meet the “propagating” limitation, at least one of the propagated timing
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`tables must include a reference to a tag. The language of claim 1 makes this
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`evident:
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`wherein at least a first timing table, of the plurality of timing
`tables, refers to a tag comprising at least a first label indicating a
`marked point in the circuit description . . . .
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`The “propagating” limitation thus requires propagating a “refer[ence] to a tag”
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`through a circuit description. See Ex. 2004, ¶¶ 79-80.
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`
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`As evidenced by Petitioner’s proposed claim construction for “timing table”
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`(Petition at 23-24), Petitioner fails to recognize this requirement of the claims.
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`See Section III.B, supra. Statements made by Petitioner’s expert, Dr. Soheil
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`Ghiasi, also make evident Petitioner’s incorrect understanding of the “propagating”
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`limitation:
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`Q. [D]oes [propagating a timing table through a circuit
`description within the context of the ’127 Patent] require
`propagating anything more than a single delay value?
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`A. So if I understand your question, you’re asking whether
`propagating timing tables requires propagating more than one
`delay value. . . . I don’t think necessarily you need more than one
`delay value for that objective.
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`Q. Do you need anything other than a delay value?
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`A. Not for that objective. I don’t think so.
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`Ex. 2003, Deposition of Soheil Ghiasi, at 25.
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`Petitioner’s incorrect understanding of the claim is further evidenced in its
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`discussion of how Belkhale allegedly meets the “propagating” step. See Petition at
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`22-24. In particular, Petitioner makes evident that it is attempting to equate
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`Belkhale’s delay values (i.e., arrival times (AT)) with the recited “timing tables” of
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`claim 1:
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`Belkhale . . . discloses [the step of “propagating a plurality of
`timing tables through the circuit description.”] Belkhale
`calculates multiple delay values – arrival times (AT) – at each
`point of the circuit and propagates those delay values through
`the circuit.
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`Petition at 22 (emphasis added).
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`The timing tables for each vertex are illustrated in Fig. 3 where for
`each vertex v1-v9, at least one delay value is calculated . . . . For
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`some nodes with multiple paths such as v5, multiple delay values
`– AT – and required arrival times (RAT) are calculated. . . .
`Thus, Belkhale teaches “propagating a plurality of timing tables
`through the circuit description” as required by claim 1.
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`Id. at 23 (emphasis added).
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`Petitioner thus argues that Belkhale’s alleged disclosure of propagating
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`delay values meets the “propagating a plurality of timing tables” limitation. But
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`as explained above, Petitioner’s argument is incorrect: the propagating limitation
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`cannot be met by propagating only delay values through a circuit description. For
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`the propagating limitation to be met, there must be a propagation of a “refer[ence]
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`to a tag.”
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`Petitioner’s incorrect understanding of the claim language is fatal to its
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`unpatentability argument: in discussing how Belkhale allegedly meets the
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`“propagating” limitation, Petitioner provides no evidence that Belkhale discloses
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`propagating a “refer[ence] to a tag.” See Ex. 2004, ¶¶ 80-82. Claim 1 explicitly
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`requires this feature, and Petitioner has the burden to specify where each element of
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`the claim is found in the prior art. 35 U.S.C. § 316(e); 37 C.F.R. § 42.104(b)(4).
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`Petitioner has failed to meet its burden.
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`The Declaration of Dr. Ghiasi filed by Petitioner does not remedy the
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`deficiencies of the Petition. Dr. Ghiasi’s declaration regurgitates, nearly word-for-
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`word, the analysis and conclusions of the Petition regarding the alleged
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`obviousness of claim 1. Ex. 1007 at ¶¶ 93-140. Like the Petition, the Declaration
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`provides no evidence that Belkhale discloses propagating a “refer[ence] to a tag.”
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`For at least these reasons, the Petition fails to set forth a prima facie case that
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`claim 1 is obvious over Belkhale.
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`2.
`
`The Petition’s allegations that Belkhale’s “set attribute” is
`propagated through a circuit description do not provide
`evidence that Belkhale discloses propagating a reference to
`a tag.
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`The Petition includes two isolated passages, which, if read charitably, could
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`be seen as allegations that Belkhale discloses propagating information other than
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`delay values. Specifically, these passages may be seen as allegations that Belkhale
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`discloses propagating a tag through a circuit description. Even assuming these
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`allegations to be true, Petitioner still fails to provide evidence that Belkhale
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`discloses propagating a reference to a tag, as required by the claims.
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`First, the Petition includes an annotated version of Belkhale’s Figure 3.
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`Petition at 15. Petitioner may argue that this annotated figure is evidence of
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`Belkhale disclosing propagation of a “timing table” that includes both a delay
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`value and a set attribute:
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`Id. This argument would be contrary to P