(12) United States Patent
`Komatsuzaki
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 6,944,042 B2
`Sep. 13, 2005
`
`US006944042B2
`
`(54)
`
`(75)
`(73)
`
`MULTIPLE BIT MEMORY CELLS AND
`METHODS FOR READING NON-VOLATILE
`DATA
`
`Inventor: Katsuo Komatsuzaki, Ibaraki (JP)
`
`Assignee: Texas Instruments Incorporated,
`Dallas, TX (US)
`
`(*)
`
`Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21)
`(22)
`(65)
`
`(51)
`
`(52)
`
`(58)
`
`(56)
`
`Appl. No.:
`
`Filed:
`
`10/334,366
`Dec. 31, 2002
`
`Prior Publication Data
`
`US 2004/0125644 A1 Jul. 1, 2004
`
`Int. Cl.7 ....................... .. G11C 11/22; G11C 11/00;
`5/06; G11C 11/34; G11C 7/00
`US. Cl. ....................... .. 365/145; 365/154; 365/65;
`365/181; 365/190; 365/205
`Field of Search ............................... .. 365/145, 154,
`365/65, 181, 190, 205, 185.08
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`A
`
`4,716,552
`4,809,225
`4,853,893
`4,980,859
`5,097,449
`5,491,666
`5,623,442
`5,680,344
`5,923,582
`5,995,409
`6,009,011
`
`****
`
`12/1987
`2/1989
`8/1989
`12/1990
`3/1992
`2/1996
`4/1997
`10/1997
`7/1999
`11/1999
`12/1999
`
`Maltiel et al. ............ .. 365/222
`Dimmler et al.
`Eaton, Jr. et al.
`Guterman et al.
`Cuevas ......... ..
`
`365/185.08
`365/185.07
`
`Sturges . . . . . . . .
`
`. . . .. 365/201
`
`Gotou et al. ......... .. 365/185.08
`Seyyedy
`
`Voss ......................... .. 365/154
`Holland
`365/149
`Yamauchi ............ .. 365/185.01
`
`5/2000 Nishimura
`6,069,816 A
`6,122,197 A * 9/2000 Sinai et al. .......... .. 365/18522
`6,137,716 A * 10/2000 Wik .................... .. 365/18501
`6,141,242 A 10/2000 Hsu et al.
`6,222,765 B1 * 4/2001 Nojima ................ .. 365/18508
`6,259,126 B1
`7/2001 Hsu et al.
`6,263,398 B1
`7/2001 Taylor et al.
`6,285,575 B1
`9/2001 Miwa
`6,297,989 B1 * 10/2001 Cloud et al. ......... .. 365/18508
`6,363,011 B1 * 3/2002 Hirose et al. ........ .. 365/18507
`
`6,370,058 B1 * 4/2002 Fukumoto . . . . . .
`
`. . . .. 365/18508
`
`6,414,873 B1 * 7/2002 Herdt . . . . . . . .
`. . . .. 365/18508
`6,754,108 B2 * 6/2004 Forbes ................ .. 365/18525
`2003/0235095 A1 * 12/2003 Inoue ....................... .. 365/201
`2004/0016947 A1 * 1/2004 Choi ........................ .. 257/296
`
`FOREIGN PATENT DOCUMENTS
`
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`
`05342890 A * 12/1993
`06244384 A * 9/1994
`07226088 A * 8/1995
`411126492 A * 5/1999
`2000187989 A * 7/2000
`2001057085 A * 2/2001
`2003133532 A * 5/2003
`2003308691 A * 10/2003
`
`......... .. G11C/14/00
`.. H01L/27/108
`G11C/14/00
`G11C/16/04
`G11C/14/00
`G11C/14/00
`.. H01L/27/105
`....... .. G11C/11/401
`
`* cited by examiner
`
`Primary Examiner—Hoai Ho
`Assistant Examiner—Ly Duy Pham
`(74) Attorney, Agent, or Firm—Jacqueline J. Garner; W.
`James Brady III; Frederick J. Telecky, Jr.
`(57)
`ABSTRACT
`
`Memory cells are disclosed comprising volatile and non
`volatile portions, Where the non-volatile portions provide
`storage of multiple non-volatile data states or bits per
`memory cell. Methods are provided for reading non-volatile
`data states from a non-volatile portion of a memory cell into
`a volatile portion.
`
`8 Claims, 14 Drawing Sheets
`
`106-1
`
`

`

`US. Patent
`
`Sep. 13, 2005
`
`Sheet 1 0f 14
`
`US 6,944,042 B2
`
`2‘\
`
`21 J
`
`221
`
`_-
`
`PRO
`
`V85
`
`VSS
`
`4\
`
`VDD
`815‘ FT"
`10XMK12
`I.
`ELMJ
`
`173‘
`
`EN1
`
`{18
`
`15J
`
`VSS
`
`V0‘19
`
`13
`
`c1—/'
`
`20.]
`
`14 W
`
`V¥cz
`
`SJ
`
`FIG. 1
`
`(PRIOR ART)
`
`

`

`US. Patent
`
`Sep. 13, 2005
`
`Sheet 2 0f 14
`
`US 6,944,042 B2
`
`102“
`
`Q11—\
`
`.
`
`PMCN
`
`Q12 J
`
`g
`
`;
`
`.
`
`SRAMP
`ENABLE
`
`SRAM P
`
`DISABLE
`
`SRAM N
`DISABLE
`
`SRAM N
`ENABLE
`
`cFE4b 4“
`CFEZb
`CFE1b \
`
`J ‘
`
`vss k Q14
`
`'. CFE4a r 106a
`CFEZa
`/ CFE1a
`
`PL1
`
`FIG. 2A
`
`

`

`U.S. Patent
`
`Sep. 13,2005
`
`Sheet 3 0f 14
`
`US 6,944,042 B2
`
`SRAM P ENABLE
`SRAM P DISABLE
`SRAM N ENABLE
`SRAM N DISABLE
`
`120 \ CONTROL CIRCUIT NM
`PL5 _ W J
`
`PL1 -
`
`PL2 -
`
`PL3 -
`
`PL4 -
`
`Y
`
`FIG. 2B
`
`13° _\
`
`134
`
`SRAM SRAM FERAM
`Read
`Write
`Write
`
`F ERAM SRAM
`Read
`Wnte
`
`BL VDD
`
`WL
`0
`SRAM N ENABLE “m0
`SRAM N DISABLE v“;
`SRAM P ENABLE Y1")
`SRAM P DISABLE “>3
`PL] vm;
`PL2-PL5 van“
`N2 v03
`N1 WI?
`
`j ‘K133
`“*2
`FlG.3
`
`‘¥135 ‘\136
`
`

`

`US. Patent
`
`Sep. 13, 2005
`
`Sheet 4 0f 14
`
`US 6,944,042 B2
`
`102'
`
`x
`
`PMCN
`
`Q11 “A _
`
`Q12 J
`
`vss
`
`SRAM P
`ENABLE
`
`SRAM P
`DISABLE
`
`N2
`
`m
`
`01 x} , r 02
`Eu.
`lJ Q4
`
`Q7\
`
`8
`
`/Q
`
`-
`
`DISABLE
`
`SRAM N
`
`ENABLE
`
`vss k Q14
`
`k Q9
`
`Q10 .1 W
`
`Cre4b
`
`CFEda
`
`

`

`U.S. Patent
`
`Sep. 13,2005
`
`Sheet 5 0f 14
`
`US 6,944,042 B2
`
`14° "1
`
`SRAM SRAM FERAM
`Read
`Write
`Write
`
`144
`FERAM SRAM
`Read
`Write
`
`BL YD‘; _
`
`SRAM P ENABLE W": '
`SRAM P DISABLE "W '
`
`/
`/
`
`\
`\
`
`PM “"3:
`PL2-PL5 "'00:
`N2 v00
`‘I:
`
`\
`
`\__4/_\
`N
`A j_'—
`
`JMAV
`
`] t 143
`142
`FIG .
`
`‘L 145 L 146
`152
`
`141
`
`150 -\
`
`( BEGIN FERAM READ )/
`+
`PRECHARGE N1 AND N2 TO OV
`
`154
`
`156
`SET TARGETED PLATELINE SIGNAL TO
`UV AND SET NON-TARGETED PLATELINE /_
`SIGNALS TO VDD/2
`
`158
`SET TARGETED PLATELINE SIGNAL
`ABOVE VDD AND SET NON-TARGETED /“
`PLATELINE SIGNALS TO 0v
`1
`160
`SET PLATELINES TO VDD/2 /
`+
`162
`( END FERAM READ )/
`FIG. 4B
`
`

`

`U.S. Patent
`
`Sep. 13,2005
`
`Sheet 6 0f 14
`
`US 6,944,042 B2
`
`202
`“\
`
`PMCN
`'\
`
`VDD
`
`Q11
`SRA
`“A k’_ < ENABLE
`SRAM P
`012/’ F DISABLE
`VSS
`
`‘ A
`
`'
`
`v00 [- Q13
`
`NMCN A
`
`a
`
`DISABLE
`SRAM N
`
`< ENABLE
`
`EH
`
`VSS
`
`K Q14
`
`0E4
`
`r 206a
`
`FIG. 5A
`
`

`

`US. Patent
`
`Sep. 13, 2005
`
`Sheet 7 0f 14
`
`US 6,944,042 B2
`
`202 —\
`
`220
`
`SRAM P ENABLE
`
`
`CONTROL CIRCUIT
`SRAM P DISABLE
`
`SRAM N ENABLE
`
`SRAM N DISABLE
`
`WL
`
`
`
`FIG. SB
`
`23° N
`
`BL
`
`BL,
`
`“IL
`
`VDD
`
`VDD
`
`VDD
`
`SRAM N ENABLE VD”
`
`SRAM N DISABLE "’0
`
`SRAM P ENABLE VD“
`
`SRAM P DISABLE VD”
`
`PLl
`
`VDD
`
`PL6-PL8 "’0
`
`PL2-5,PL9-IO VDD
`
`N2
`
`234
`SRAM SRAM FERAM [ FERAM
`
`Read
`
`
`Write Write
`
`SRAM
`
`Wnte
`
`Read
`
`
`
`

`

`US. Patent
`
`Sep. 13, 2005
`
`Sheet 8 0f 14
`
`US 6,944,042 B2
`
`202'
`
`x
`
`PMCN
`
`Q11 N
`
`'
`
`(312 J
`<m U)
`
`SRAM P
`ENABLE
`
`RAM P
`DISABLE
`
`Z N
`
`Z _‘L
`
`VDD ,- Q13
`
`SRAM N
`
`DISABLE
`
`SRAM N
`ENABLE
`
`
`
`FIG. 5C
`
`

`

`U.S. Patent
`
`Sep. 13,2005
`
`Sheet 9 0f 14
`
`US 6,944,042 B2
`
`BEGIN FERAM READ
`
`242
`
`YES
`
`TARGET
`FECAP IN FIRST
`
`NO
`
`244
`
`V
`
`V
`
`SET ALL PLATELINES TO 0v
`SET ALL PLATELINES TO 0v /_ 246
`+
`260 J
`+
`
`SET NON-TARGETED SECOND
`SET NON-TARGETED FIRST
`PLATELINE SIGNALS AND SOME
`PLATELINE SIGNALS AND SOME /— 248
`SECOND PLATELINE SIGNALS
`_/ FIRST PLATELINE SIGNALS T0
`T0 VDD/2
`262
`VDD/2
`
`SET TARGETED SECOND
`SET TARGETED FIRST
`PLATELINE SIGNAL T0 VDD AND
`PLATELINE SIGNAL TO vDD AND /— 250
`SET OTHER SECOND
`_/ SET OTI-IER FIRST PLATELINE
`PLATELINE SIGNALS TO WM 264
`SIGNALS TO VDD/2
`
`SET TARGETED SECOND
`/- 252
`SET TARGETED FIRST
`PLATELINE SIGNAL TO mm 266 J PLATELINE SIGNAL TO vDD/2
`
`

`

`U.S. Patent
`
`Sep. 13,2005
`
`Sheet 10 0f 14
`
`US 6,944,042 B2
`
`SRA P
`ENABLE
`RAM P
`DISABLE
`
`SRAM N
`DISABLE
`
`SRAM N
`ENABLE
`
`PL1
`
`PL2
`
`306 --" ;
`
`FIG. 7A
`
`

`

`U.S. Patent
`
`Sep. 13,2005
`
`Sheet 11 0f 14
`
`US 6,944,042 B2
`
`302 X
`
`320 -\ CONTROL CIRCUIT
`
`;— SRAM P ENABLE
`;- SRAM P DISABLE
`:- SRAM N ENABLE
`:— SRAM N DISABLE
`;—-— WL
`
`PL1 _¥_,
`
`PL2 —>
`
`,
`
`330 \
`
`SRAM SRAM FERAM
`Read
`Wm‘: Write
`
`FERAM
`Read
`
`BL VDI: H
`BL,
`VD: TV
`WL “"3 mn
`
`/
`
`\
`
`PL} “'3:
`PL2 ""3:
`
`N2
`
`0
`
`van P W
`
`/
`
`\ pm
`
`331
`
`FIG. 8
`
`

`

`U.S. Patent
`
`Sep. 13,2005
`
`Sheet 12 0f 14
`
`US 6,944,042 B2
`
`SRAM P
`ENABLE
`
`DISABLE
`
`S A
`DISABLE
`
`SRAM N
`ENABLE
`
`i
`
`PL2
`
`FIG. 7C
`
`

`

`U.S. Patent
`
`Sep. 13,2005
`
`Sheet 13 0f 14
`
`US 6,944,042 B2
`
`SRAM P
`ENABLE
`SRAM P
`DISABLE
`
`:
`i
`5
`
`SRAM N
`DISABLE
`
`SRAM N
`ENABLE
`
`PL1
`
`Q14 J E
`
`V55
`
`FIG. 9A
`
`

`

`U.S. Patent
`
`Sep. 13,2005
`
`Sheet 14 0f 14
`
`US 6,944,042 B2
`
`402 —\
`
`SRAM P ENABLE
`420 -\ CONTROL CIRCUIT *4: SRAM P DISABLE
`" SRAM N ENABLE
`4;- SRAM N DISABLE
`:—WL
`
`FIG. 10
`
`

`

`US 6,944,042 B2
`
`1
`MULTIPLE BIT MEMORY CELLS AND
`METHODS FOR READING NON-VOLATILE
`DATA
`
`INCORPORATION BY REFERENCE
`
`The disclosure of US. patent application Ser. No. 10/293,
`195 entitled VOLATILE MEMORY WITH NON
`VOLATILE FERROELECTRIC CAPACITORS, ?led on
`Nov. 13, 2002, is hereby incorporated by reference as if fully
`set forth herein.
`
`10
`
`FIELD OF INVENTION
`
`The present invention relates generally to semiconductor
`memory devices and more particularly to volatile data
`memory cells having multi-bit non-volatile storage capabil
`ity and methods for operation thereof.
`
`15
`
`BACKGROUND OF THE INVENTION
`
`2
`Recently, non-volatile ferroelectric RAM devices have
`been developed, Which are commonly referred to as
`FERAMs or FRAMs. FERAM cells employ ferroelectric
`cell capacitors including a pair of capacitor plates With a
`ferroelectric material betWeen them. Ferroelectric materials
`have tWo different stable polariZation states that may be used
`to store binary information, Where the ferroelectric behavior
`folloWs a hysteresis curve of polariZation versus applied
`voltage. FERAMs are non-volatile memory devices,
`because the polariZation state of a ferroelectric cell capacitor
`remains When poWer is removed from the device. Ferroelec
`tric memories provide certain performance advantages over
`other forms of non-volatile data storage devices, such as
`Flash and EEPROM type memories. For eXample, ferro
`electric memories offer short programming (e.g., Write
`access) times and loW poWer consumption. HoWever, access
`times in SRAM and DRAM type memories are signi?cantly
`shorter than in FERAM devices.
`Hybrid memory devices have been developed, Which
`include volatile and non-volatile portions. For eXample,
`memories have been constructed combining SRAM cells
`With ferroelectric devices, Wherein the memory may be
`operated as an SRAM, With the capability to backup or save
`the volatile single SRAM data bit to a ferroelectric capacitor
`associated With the SRAM cell. The non-volatile data may
`thereafter be retrieved from the ferroelectric capacitor and
`transferred to the SRAM cell. In the interim, the SRAM cell
`may be operated as normal SRAM, even While non-volatile
`data resides in the ferroelectric capacitor. HoWever, conven
`tional hybrid memory devices store only a single non
`volatile bit per cell. Thus, there is a need for improved
`hybrid memory devices and methods by Which more than
`one non-volatile data state may be stored.
`
`SUMMARY OF THE INVENTION
`
`The folloWing presents a simpli?ed summary in order to
`provide a basic understanding of one or more aspects of the
`invention. This summary is not an extensive overvieW of the
`invention, and is neither intended to identify key or critical
`elements of the invention, nor to delineate the scope thereof.
`Rather, the primary purpose of the summary is to present
`some concepts of the invention in a simpli?ed form as a
`prelude to the more detailed description that is presented
`later.
`One aspect of the invention provides memory cells com
`prising a volatile portion adapted to store a binary volatile
`data state, and a non-volatile portion coupled With the
`volatile portion, Where the non-volatile portion is adapted to
`store multiple non-volatile data states. In one
`implementation, the non-volatile portion comprises a plu
`rality of ?rst ferroelectric capacitors coupled With a ?rst
`internal node of the volatile portion, and a plurality of
`second ferroelectric capacitors coupled With a second inter
`nal node of the volatile portion.
`In another aspect of the invention, the memory cell further
`comprises a control circuit for providing plateline signals to
`the non-volatile portion. In one eXample, the non-volatile
`portion comprises a plurality of ferroelectric capacitor pairs
`individually comprising one of the ?rst ferroelectric capaci
`tors and one of the second ferroelectric capacitors, in Which
`the individual pairs provide storage of a binary non-volatile
`data state and Where the plateline signals are individually
`coupled With the ferroelectric capacitor pairs. In one
`implementation, the control circuit selectively provides a
`boosted plateline signal greater than a supply voltage to a
`targeted ferroelectric capacitor being read, and provides Zero
`
`25
`
`40
`
`45
`
`In semiconductor memory devices, data is read from or
`Written to the memory using address signals and various
`other control signals. In random access memories
`(“RAMS”), an individual binary data state (e.g., a bit) is
`stored in a volatile memory cell, Wherein a number of such
`cells are grouped together into arrays of columns and roWs
`accessible in random fashion along bitlines and Wordlines,
`respectively, Wherein each cell is associated With a unique
`Wordline and bitline pair. Address decoder control circuits
`identify one or more cells to be accessed in a particular
`memory operation for reading or Writing, Wherein the
`memory cells are typically accessed in groups of bytes or
`Words (e.g., generally a multiple of 8 cells arranged along a
`common Wordline). Thus, by specifying an address, a RAM
`is able to access a single byte or Word in an array of many
`35
`cells, so as to read or Write data from or into that addressed
`memory cell group.
`TWo major classes of random access memories include
`“dynamic” (e.g., DRAMs) and “static” (e.g., SRAMs)
`devices. For a DRAM device, data is stored in a capacitor,
`Where an access transistor gated by a Wordline selectively
`couples the capacitor to a bit line. DRAMs are relatively
`simple, and typically occupy less data, because the charge
`stored in the cell capacitors tends to dissipate. Accordingly
`DRAMs need to be refreshed periodically in order to pre
`serve the content of the memory. SRAM devices, on the
`other hand, do not need to be refreshed. SRAM cells
`typically include several transistors con?gured as a ?ip-?op
`having tWo stable states, representative of tWo binary data
`states. Since the SRAM cells include several transistors,
`hoWever, SRAM cells occupy more area than do DRAM
`cells. HoWever, SRAM cells operate relatively quickly and
`do not require refreshing and the associated logic circuitry
`for refresh operations.
`A major disadvantage of SRAM and DRAM devices is
`volatility, Wherein removing poWer from such devices
`causes the data stored therein to be lost. For instance, the
`charge stored in DRAM cell capacitors dissipates after
`poWer has been removed, and the voltage used to preserve
`the ?ip-?op data states in SRAM cells drops to Zero, by
`Which the ?ip-?op loses its data. Accordingly, SRAMs and
`DRAMs are commonly referred to as “volatile” memory
`devices. Non-volatile memories are available, such as Flash
`and EEPROM. HoWever, these types of non-volatile
`memory have operational limitations on the number of Write
`cycles. For instance, Flash memory devices generally have
`life spans from 100K to 10MEG Write operations.
`
`55
`
`65
`
`

`

`US 6,944,042 B2
`
`3
`volt plateline signals to non-targeted ferroelectric capacitors
`during the non-volatile read.
`According to yet another aspect of the invention, the
`control circuit provides separate plateline signals to the ?rst
`and second sets of ferroelectric capacitors, and the ferro
`electric capacitors are individually operable to store a binary
`non-volatile data state. In this example, the control circuit
`selectively provides a plateline signal to one of the ?rst
`ferroelectric capacitors to be read and provides plateline
`signals of a ?rst voltage to some of the second ferroelectric
`capacitors and provides plateline signals of a second differ
`ent voltage to the remaining second ferroelectric capacitors
`during a non-volatile data read operation. This provides a
`reference voltage at the second internal node during a
`non-volatile read operation to read a non-volatile data state
`from the targeted one of the ?rst ferroelectric capacitors.
`Where one of the second ferroelectric capacitors is to be
`read, the control circuit provides one of the second plateline
`signals corresponding to the targeted second ferroelectric
`capacitor, and provides plateline signals of one voltage to
`some but not all of the ?rst ferroelectric capacitors and
`provides plateline signals of a different voltage to the other
`?rst ferroelectric capacitors. This creates a reference voltage
`at the ?rst internal node during the non-volatile read opera
`tion to read a non-volatile data state from the targeted one of
`the plurality of second ferroelectric capacitors.
`According to another aspect of the invention, a method is
`provided for reading a non-volatile data state from a non
`volatile portion of a memory cell into a volatile portion of
`the memory cell in a semiconductor device. The method
`comprises providing a boosted plateline signal greater than
`a supply voltage to a targeted ferroelectric capacitor in the
`non-volatile portion to read a non-volatile data state from the
`targeted ferroelectric capacitor. This extracts more signal
`charge from the targeted ferroelectric capacitor or capacitor
`pair. In one example, the method further comprises provid
`ing Zero volt plateline signals to one or more non-targeted
`ferroelectric capacitors in the non-volatile portion While
`providing the boosted plateline signal to the targeted ferro
`electric capacitor or capacitor pair.
`Yet another aspect of the invention provides a method of
`reading a non-volatile data state from a non-volatile portion
`in a hybrid memory having a plurality of ?rst ferroelectric
`capacitors coupled With a ?rst internal node in the volatile
`portion and a plurality of second ferroelectric capacitors
`coupled With a second internal node in the volatile portion.
`This method involves providing a plateline signal to a
`targeted one of the plurality of ?rst ferroelectric capacitors
`during a non-volatile read operation to read a non-volatile
`data state from the targeted ?rst ferroelectric capacitor. In
`addition, a reference voltage is provided to the second
`internal node of the volatile portion by selectively providing
`a ?rst reference plateline signal to at least one of the second
`ferroelectric capacitors and providing a second different
`reference plateline signal to remaining second ferroelectric
`capacitors during the non-volatile read operation.
`In one example, a supply voltage is provided to the
`targeted ferroelectric capacitor, and tWo different plateline
`signals are provided to subsets of the second ferroelectric
`capacitors to create a capacitive voltage divider. The second
`internal node of the volatile portion is thereby provided With
`a reference voltage through control of the second plateline
`signals. In one implementation, the provision of the refer
`ence voltage to the second internal node comprises pre
`charging plateline terminals of all of the ?rst and second
`ferroelectric capacitors to Zero volts and applying an inter
`mediate voltage betWeen 0V and a supply voltage to non
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`targeted ?rst ferroelectric capacitors and the remaining
`second ferroelectric capacitors. The intermediate voltage is
`then applied to the at least one of the second ferroelectric
`capacitors While applying the supply voltage to the targeted
`one of the plurality of ?rst ferroelectric capacitors.
`Still another aspect of the invention provides methods for
`reading a non-volatile data state from a memory cell, Where
`the cell comprises a non-volatile portion having ?rst and
`second ferroelectric capacitors coupled With a ?rst internal
`node of a volatile portion and third and fourth ferroelectric
`capacitors coupled With a second internal node of the
`volatile portion. The method comprises providing a boosted
`plateline signal greater than a supply voltage, such as about
`tWice the supply voltage or more, to the ?rst and third
`ferroelectric capacitors, and providing a second plateline
`signal less than the supply voltage to the second and fourth
`ferroelectric capacitors. The method may be advantageously
`employed to read non-volatile data Without having to pre
`charge or equaliZe the cell.
`In accordance With yet another aspect of the invention, a
`method is provided for reading a non-volatile data state in a
`memory cell having a non-volatile portion comprising a ?rst
`ferroelectric capacitor coupled With a ?rst internal node of
`the volatile portion and a second ferroelectric capacitor
`coupled With a second internal node of the volatile portion.
`This method comprises providing a boosted plateline signal
`greater than a supply voltage to the ?rst and second ferro
`electric capacitors, Which may facilitate shortening or elimi
`nation of precharging or equalizing steps prior to the non
`volatile data read operation. In one implementation of the
`method, providing the boosted plateline signal comprises
`providing a plateline signal about tWice the supply voltage
`or more to the ?rst and second ferroelectric capacitors.
`To the accomplishment of the foregoing and related ends,
`the folloWing description and annexed draWings set forth in
`detail certain illustrative aspects and implementations of the
`invention. These are indicative of but a feW of the various
`Ways in Which the principles of the invention may be
`employed. Other aspects, advantages and novel features of
`the invention Will become apparent from the folloWing
`detailed description of the invention When considered in
`conjunction With the draWings.
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a schematic diagram illustrating a conventional
`hybrid memory device having a volatile SRAM cell and
`ferroelectric capacitor elements for storing a single non
`volatile data bit;
`FIGS. 2A and 2B provide a schematic illustration of an
`exemplary memory cell in accordance With one or more
`aspects of the present invention;
`FIG. 2C is a schematic diagram illustrating another exem
`plary memory cell having NMOS transistors to selectively
`isolate the volatile and non-volatile portions from one
`another;
`FIG. 3 is a timing diagram illustrating exemplary opera
`tion of the memory cell of FIGS. 2A and 2B;
`FIG. 4A is a timing diagram illustrating another exem
`plary operation of the memory cell of FIGS. 2A and 2B in
`accordance With another aspect of the invention;
`FIG. 4B is a How diagram illustrating an exemplary
`method of reading a non-volatile data state from a non
`volatile portion of a memory cell into a volatile portion of
`the memory cell in accordance With the invention;
`FIGS. 5A and 5B provide a schematic illustration of
`another exemplary memory cell in accordance With the
`present invention;
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`5
`FIG. 5C is a schematic diagram illustrating another exem
`plary memory cell having NMOS transistors to selectively
`isolate the volatile and non-volatile portions from one
`another;
`FIG. 6A provides a timing diagram illustrating an exem
`plary operation of the memory cell of FIGS. 5A and 5B;
`FIG. 6B is a flow diagram illustrating another exemplary
`method of reading a non-volatile data state from a non
`volatile portion of a memory cell into a volatile portion of
`the memory cell in accordance With the invention;
`FIGS. 7A and 7B provide a schematic illustration of
`another exemplary memory cell in accordance With the
`present invention;
`FIG. 7C is a schematic diagram illustrating another exem
`plary memory cell having NMOS transistors to selectively
`isolate the volatile and non-volatile portions from one
`another;
`FIG. 8 is a timing diagram illustrating an exemplary
`operation of the memory cell of FIGS. 7A and 7B;
`FIGS. 9A and 9B provide a schematic illustration of
`another exemplary memory cell in accordance With the
`present invention; and
`FIG. 10 is a timing diagram illustrating an exemplary
`operation of the memory cell of FIGS. 9A and 9B.
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`DETAILED DESCRIPTION OF THE
`INVENTION
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`6
`Whereby the volatile and non-volatile portions 4 and 6 are
`decoupled from one another. The isolated volatile portion 4
`thus operates as a conventional SRAM cell, Which is exter
`nally accessed via the bitlines BL, BL‘ and the Wordline WL
`to read and Write data into the ?ip-?op formed by the
`transistors 11, 13, 10 and 12.
`In an FERAM Write, data may be Written to the non
`volatile portion 6 from the SRAM portion 4. For example,
`Where the data in the SRAM portion 4 is such that node 8 is
`at a loW voltage level (VSS) and the node 9 is at a high
`voltage level (VDD), the SRAM data may be stored in the
`ferroelectric capacitors C1 and C2 as folloWs. The signal
`FEN initially is brought high to alloW the ferroelectric
`capacitors C1 and C2 to charge up With EN1 and EN2
`enabled, and the plateline signal PL is initially loW. The
`voltage at a non-volatile portion node 14 rises When the
`transistor 20 turns on, and the ferroelectric capacitor C2 is
`programmed to a ?rst or “high” polariZation state. The
`plateline signal PL is then brought high to charge the C1 by
`bringing the non-volatile portion node 13 loW When the
`transistor 19 turns on. In this manner, the reversed voltage
`potential across the ferroelectric capacitor C1 causes it to be
`polariZed to an opposite second or “loW” polariZation state.
`In this manner, the high node 9 of the SRAM cell portion
`4 corresponds to C2 being programmed to the “high”
`polariZation state, and the loW level at the node 8 of the static
`cell 4 has been Written as a “loW” polariZation state to C1.
`Similar operation is found Where the data in the SRAM is of
`an opposite binary value, such as Where node 9 is at a loW
`voltage level (VSS) and node 8 is at a high voltage level
`(VDD). Once the SRAM data has been stored in the non
`volatile portion 6, the memory may thereafter be poWered
`doWn Without any data loss because the polariZation states of
`capacitors C1 and C2 are maintained, thereby preserving the
`data. HoWever, the SRAM portion 4 may optionally be
`operated as a volatile memory thereafter, Without disturbing
`the non-volatile data in the portion 6, such as by pulling the
`plateline signal PL and the signal FEN loW, to isolate or
`decouple the portions 4 and 6 from one another.
`To read the non-volatile data into the SRAM 4, the signal
`PRC and the Wordline WL are brought high to precharge the
`nodes 8 and 9 to ground through the transistors 17, 18, 21,
`and 22. The plateline PL is held loW and the FEN signal is
`brought high to couple the capacitor nodes 13 and 14 to the
`SRAM nodes 8 and 9 at 0 V. Then, the precharging transis
`tors 21 and 22 are turned off by bringing the PRC signal loW,
`and the Wordline WL is brought loW to turn transistors 17
`and 18 off. The plateline signal PL is brought high to provide
`voltages across the ferroelectric capacitors C1 and C2 such
`that the ferroelectric capacitor having a “high” polariZation
`state Will experience a polariZation reversal. The SRAM cell
`is then enabled by activation of EN1 and EN2 to sense the
`data from the ferroelectric capacitors C1 and C2, and to latch
`the sensed data state. Ideally, the capacitance of the internal
`nodes 8 and 9 of the SRAM 4 cell is sufficiently high so that
`the voltages at nodes 8 and 9 stay loW enough for at least
`partial reversal of polariZation to occur for the ferroelectric
`capacitor C2 Which had been Written to the “high” polar
`iZation state. If so, the voltage at node 9 Will be slightly
`higher than at node 8 during the FERAM read, Where the
`SRAM 4 operates as a sense amp to sense and latch the
`voltage difference as volatile SRAM data.
`HoWever, the inventor has appreciated that if the SRAM
`capacitance is insufficient to ensure partial reversal of polar
`iZation of the ferroelectric capacitor at the “high” polariZa
`tion state (e.g., C2 in this example), then the resulting
`voltage difference betWeen the internal SRAM nodes 8 and
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`The present invention Will noW be described With refer
`ence to the attached draWings, Wherein like reference numer
`als are used to refer to like elements throughout. The
`invention relates to a memory apparatus comprising a vola
`tile portion and a non-volatile portion, in Which tWo ferro
`electric capacitors are coupled to an internal node of the
`volatile portion. In order to better appreciate one or more
`features of the invention, a conventional hybrid memory
`device is hereinafter illustrated and described With respect to
`FIG. 1.
`FIG. 1 illustrates a conventional hybrid memory cell 2
`consisting of a CMOS SRAM cell 4 and a non-volatile (e.g.,
`shadoW) portion 6 for storing a single data bit. The SRAM
`cell 4 includes tWo PMOS transistors 10 and 12 and tWo
`NMOS transistors 11 and 13 forming a pair of cross-coupled
`inverters, enabled by transistors 15 and 16 according to
`45
`enable signals EN1 and EN2, respectively. Internal SRAM
`nodes 8 and 9 are cross-coupled to the inverters, and
`transistors 17 and 18 are provided to couple the nodes 8 and
`9 to complementary bitlines BL and BL‘, respectively,
`according to a Wordline control signal WL. The nodes 8 and
`9 are further coupled through a pair of NMOS transistors 19
`and 20 With the upper terminals of ferroelectric capacitors
`C1 and C2 at nodes 13 and 14, respectively, for non-volatile
`data storage of a single data bit in the portion 6, Wherein the
`transistors 19 and 20 are gated by a ferroelectric enable
`signal FEN.
`The loWer terminals of the ferroelectric capacitors C1 and
`C2 are coupled to a single plateline signal PL. In addition,
`tWo transistors 21 and 22 are provided for selectively
`precharging the bitlines BL and BL‘, respectively, to ground
`(VSS) according to a control signal PRC. In normal (e.g.,
`volatile SRAM) operation of the cell 2, the enable signals
`EN1 and EN2 are active, Whereby the transistor 15 pulls the
`upper source/drain terminals of transistors 10 and 12 to
`VDD and the transistor 16 grounds the loWer source/drain
`terminals of SRAM transistors 11 and 13 to VSS. The
`plateline signal PL and the enable signal FEN are low,
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`9 during sensing is small, possibly below the amount needed
`for proper sensing by the SRAM 4. In the device 2, the load
`capacitance is largely determined by the MOS transistors 10,
`12, 11, and 13 of the SRAM portion 4. A capacitive
`imbalance condition can reduce the sense margin of the
`device 2 and may lead to incorrect reading of the non
`volatile data (data ?ip), particularly Where there are sensi
`tivity imbalances in the transistors of the SRAM portion 4.
`For example, the transistors 11 and 13 may have different
`performance characteristics due to pattern siZe variation or
`due to impurity variations in the MOS channels thereof,
`requiring more signal charge to overcome the imbalance. If
`large performance characteristic imbalances exist betWeen
`the transistors 11 and 13, for example, more signal charge
`extraction is desirable to ensure correct sensing.
`The device 2 in FIG. 1 may also suffer from quick
`self-latching When the initial equalization is not complete
`and/or Where the ferroelectric capacitors C1 and C2 are not
`closely matched. For example, small differences in the
`capacitors C1 and C2 may upset the sensing operation
`during FERAM read operations prior to signal charge
`extraction if insuf?cient voltage is applied to extract the
`signal charge. In addition, the equaliZation prior to FERAM
`read operations takes time and increases the access time to
`obtain the non-volatile data from the ferroelectric capacitors.
`Furthermore, the cell of FIG. 1 can store only one bit of data
`in the ferroelectric capacitors C1 and C2.
`The present invention provides multi-bit hybrid memory
`cells combining volatile portions, such as single-bit SRAM
`circuitry, With the capability of storing multiple non-volatile
`data bits, such as in multiple ferroelectric capacitors coupled
`With the SRAM portion. Other aspects of the invention
`provide methods for reading non-volatile data in such mul
`tiple bit hybrid memory cells. In addition, methods are
`provided Which alloW minimiZation or elimination of equal
`iZation prior to non-volatile data read operations, by Which
`access times can be improved in hybrid memory devices.
`Referring to FIGS. 2A, 2B, and 3, one aspect of the
`present invention alloWs storage of multiple non-volatile
`data states or bits per memory cell. An exemplary memory
`cell 102 is illustrated in FIGS. 2A and 2B comprising
`volatile and non-volatile portions 104 and 106, respectively,
`and a control circuit 120 (FIG. 2B), Where FIG. 3 provides
`a timing diagram 130 illustrating exemplary operation of the
`memory cell 102. The exemplary volatile portion 104 is
`adapted to store a single binary volatile data state or bit, and
`includes an SRAM device comprising a ?ip-?op formed by
`tWo PMOS transistors Q1 and Q2 and tWo NMOS transistors
`Q3 and Q4 With internal nodes N1 and N2. HoWever, other
`types of volatile memory portions may be employed in a
`hybrid memory device Within the scope of the