US007102391B1
`
`(12)
`
`United States Patent
`Sun et a].
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 7,102,391 B1
`Sep. 5, 2006
`
`(54) CLOCK-GENERATOR ARCHITECTURE FOR
`APROGRAMMABLE-LOGIC-BASED
`SYSTEM ON A CHIP
`
`(75) Inventors; shin_Nan sun, Fremont’ CA (Us);
`Limin Zhu’ Fremont’ CA (Us);
`Theodore speers San Jose CA
`Gregory Bakker’ San JOSe’CA ms)’
`’
`’
`Assigneez Actel Corporation’ Mountain View’
`(Us)
`
`8/1993 Little et al. ............... .. 395/750
`5,237,699 A
`8/1994 Josephson et al. ........ .. 307/465
`5,336,951 A
`9/1995 Torode ................. .. 331/108 C
`5,451,912 A
`1/1996 BeItoluZZi et a1. .......... .. 331/69
`5,485,127 A *
`9/1996 Padoan et al. ........... .. 326/40
`5,559,449 A
`5,563,526 A 10/1996 Hastings et a1. ..
`326/37
`5,684,434 A 11/1997 Mann et a1.
`331/16
`5,687,325 A 11/1997 Chang ..... ..
`395/284
`5,757,212 A *
`5/1998 Sevalia ........ ..
`327/105
`5,774,701 A *
`6/1998 Matsui et al. ............. .. 713/501
`5,811,987 A
`9/1998 Ashmore, Jr. et al. ...... .. 326/39
`5,821,776 A 10/1998 McGowan ................. .. 326/41
`
`( * ) Notice:
`
`
`Subject to any disclaimer, the term ofthis - -
`
`1’??? 11S signgedwor dzdlsusted under 35
`
`'
`
`'
`
`'
`
`y
`
`y '
`
`,
`,
`i
`5,949,987 A
`
`.
`yam e: ange a.
`
`9/1999 Curd et a1. .......... .. 395/500.17
`
`5,999,014 A 12/1999 Jacobson etal. ........... .. 326/38
`
`(21) Appl. No.: 10/903,473
`
`22 F1 d:
`(
`)
`1e
`
`J l. 29 2004
`“
`’
`
`(Continued)
`OTHER PUBLICATIONS
`
`Related US‘ Application Data
`(63) continuationdmpart of application NO 10/8 43,701’
`?led on May 10, 2004.
`
`Author: Anonymous, 4-Pin nP Voltage Monitors With Manual Reset
`Input, Maxim Integrated Products, document 19-0411; Rev 3; Mar.
`1999’ PP' 1'8'
`
`(60) Provisional application No. 60/491,788, ?led on Jul.
`31> 2003'
`I
`C]
`/00
`
`(2006 01)
`
`51
`(
`)
`
`(52) US. Cl. ......................... .. 327/10; 327/99; 327/298
`(58) Field of Classi?cation Search ................... .. None
`See apphcanon ?le for Complete Search hlstory'
`References Cited
`
`(56)
`
`U.S. PATENT DOCUMENTS
`
`4,479,097 A * 10/1984 Larson et a1. ............. .. 331/111
`4,503,494 A
`3/1985 Hamilton et a1. ......... .. 364/200
`
`4,758,745 A
`4,855,954 A
`
`7/1988 Elgamal et a1. . . . . .
`8/1989 Turner et a1.
`
`. . . .. 307/465
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`
`4,870,302 A
`
`9/1989 Freeman . . . . . .
`
`. . . .. 307/465
`
`365/201
`4,879,688 A 11/1989 Turner et a1.
`5,101,122 A
`3/1992 Shinonara ................. .. 307/465
`
`5,132,571 A
`5,237,218 A
`
`7/1992 McCollum ............. .. 307/465.1
`8/1993 Josephson et al. ........ .. 307/465
`
`(Continued)
`Primary ExamineriTerry D. Cunningham
`. uu
`sslstant xammeri
`A I
`E I
`An T L
`(74) Attorney, Agent, or FirmiSierra Patent Group, Ltd.
`
`(57)
`
`ABSTRACT
`
`Aprogrammable system-on-a-chip integrated circuit device
`comprises at least one of a crystal oscillator circuit, an RC
`oscillator circuit, and an external oscillator input. A clock
`conditioning circuit is selectively coupleable to one of the
`programmable logic block, the crystal oscillator circuit, the
`RC oscillator circuit, and the external oscillator input. A
`real-time clock is selectively coupleable to one of the
`programmable logic block, the crystal oscillator circuit, the
`RC oscillator circuit, and the external oscillator input. A
`programmable logic block is coupled to the clock condi
`tioning circuit and the real-time clock.
`
`32 Claims, 17 Drawing Sheets
`
`CLOCK CONDITIONING CIRCUIT
`
`515
`
`514
`
`51a
`
`PROGRAMMABLE LOGIC BLOCK
`
`

`

`US 7,102,391 B1
`Page 2
`
`U.S. PATENT DOCUMENTS
`
`3/2000 KOPGC, Jr et a1- ---------- -- 326/39
`6,034,541 A
`7/2000 Zink ----------- --
`-- 365/18518
`6,091,641 A
`8/2000 Mann ---------- -
`6,104,257 A
`331/158
`6,134,707 A 10/2000 Herrmann et al.
`717/5
`6,145,020 A 11/2000 Barnett ........ ..
`. 710/8
`
`6’l50’837 A ll/ZOOO Beal et a1’ "
`6’l9l’660 Bl
`ZZZOOI NF“; 31'
`et a ' "
`g """""" "
`8/2001 Rangasayee et a1
`10/2001 TaT‘g et a1’ """" "
`12/2001 Enck-son
`2/2002 0mm et a1’
`3/2002 Tang et a1‘
`5/2002 Tang e.t 31'
`5/2002 Ghezz1etal.
`6/2002 Herrmann et a1‘
`7/2002 May et a1’ """ "
`72002 Jones et all‘
`Z
`glaitnéllieitaa'l
`
`’
`’
`6,272,646 B1
`6’304’099 Bl
`6,334,208 B1
`6’346’905 Bl
`6’356’l07 Bl
`6389321 Bl
`6,396,168 B1
`6’408’432 Bl
`6’4 14368 Bl
`6’4l5’344 Bl
`
`326/39
`33 l//lll
`
`' 713/500
`326/38
`.. 716/17
`' 341/159
`326/40
`700/2
`307/44
`717/139
`257/523
`" non/05
`
`2003/0210585 A1 11/2003 Bernardi et al. .......... .. 365/200
`2003/0210599 A1
`11/2003 McClure ...... ..
`. 365/225.7
`2003/0214321 A1
`11/2003 Swami et al. ............... .. 326/38
`2004/0008055 A1
`1/2004 Khanna et a1. ............. .. 326/40
`2004/0036500 A1
`2/2004 Bratt ......................... .. 326/39
`
`OTHER PUBLICATIONS
`
`Author: Anonymous, “Fan Controller and Remote Temperature
`Sensor With SMBus Serial Interface” for MAX1669, Maxim Inte
`grated Products, document 19-1574; Rev 0; Jan. 2000, pp. 1-8.
`Author: Anonymous, “Precision RESET Controller and 4K I2C
`Memory With Both RESET and RESET Outputs” for s24042/
`S24043, Summit Microelectronics, Inc., document 2011 2.0 May 2,
`2000,1313‘ 144‘
`Author: Anonymous, “SOT23, Low-Power uP Supervisory Circuits
`With Battery Backup and Chip-Enable Gating” for MAX6365
`MAX6368, Maxim Integrated Products, document 19-1658; Rev 1;
`Jun‘ 2001, pp‘ 145‘
`Author: Anonymous, “Cypress MicroSystems PsoC Microcontrol
`lers Now Available in Volume”, Cypress Semiconductor Corpora
`tion Press Release Sep. 5, 2001 [Internet: mhtml:?le://
`D:\Act401\Cypress%20Semiconductor%20Corporation.mht].
`
`Author: Anonymous, “nvSRAMiSRAM and EEPROM Within a
`Single chip» ZMD AG, pp‘ 14, Oct‘ 2001‘
`Author: Anonymous, “Intelligent Temperature Monitor and Dual
`PWM Fan Controller” for ADM1031, Analog Devices, pp. 1-32,
`2003'
`Author: Anonymous, “LM63:1° C/:3° C Accurate Remote Diode
`Digital Temperature Sensor With Integrated Fan Control”, National
`Semiconductor Corporation, document DS200570, pp. 1-28, May
`2003‘
`Author: Anonymous, “PSoCTM Con?gurable Mixed-Signal Array
`with
`OIl-bOaICl
`Controller”,
`CY8C25122,
`CY8C26233,
`CY8C26443, CY8C26643, Device Data Sheet for Silicon Revision
`D, Cypress MicroSystems Document #: 38-1201 CY Rev. *B CMS
`Rev 322 pp 1450 Aug 18 2003
`Au?'lor'z A’non'ymous,’ “PSCCTLI Mix'ed Signal Array”, Preliminary
`Data Sheet for CY8C29466, CY8C29566, CY8C29666, and
`CY8C29866, Cypress MicroSystems Document No‘ 3842013 Rev‘
`*1)‘ pp 141 Jun 2004
`’
`'
`’
`'
`'
`* cited by examiner
`
`'
`. . . .. 326/41
`
`'
`
`331/111
`"" "71616
`352
`'
`
`’
`’
`6,483,344 B1
`*
`
`’
`’
`6,515,551 B1
`6’526’557 Bl
`
`' "
`11/2002 Gupta . . . . . . . . . . . . . .
`5321;112:2131’ "
`y
`'
`2/2003 Mar et a1. ....... ..
`2;2003 Yomig et a1’ "
`47‘
`520821;; "" "
`'
`"
`’
`’
`327/298
`7/2003 Nguyen .... ..
`6,600,355 B1
`331/46
`9/2003 Sullam e? 31
`6514320 Bl
`714/7”
`“Z2003 Shokouh‘
`6,651,199 B1
`gig
`588: glimmer et a
`2,313’??? g}
`""""""" "
`’
`’
`331/176
`6/2004 Mar et a1. .... ..
`6,753,739 B1
`326/39
`2001/0030554 A1 10/2001 GheZZi et al.
`' 713/501
`2002/0007467 A1
`1/ 2002 Ma et a1
`2002/0108006 A1
`8/2002 Snyder ..................... .. 710/100
`2003/0001614 A1
`1/2003 S1ngh et al. ................ .. 326/40
`2003/0005402 A1
`1/2003
`2003/0074637 A1
`4/2003
`
`

`

`U.S. Patent
`
`Sep. 5, 2006
`
`Sheet 1 0f 17
`
`US 7,102,391 B1
`
`Programmable System
`on Chip Device
`
`Digital H0
`
`/10
`
`20
`/
`/
`/ J
`
`__
`
`l
`
`Digital l/O\
`\\
`
`//
`20/
`
`1_4
`Non-Volatile
`
`m
`
`Volatile Memory
`
`12
`—
`Programmable Logic
`Block
`
`Hardwired Analog
`Blocks
`@@@
`@ @ El
`
`System /24
`Controller
`
`Clock
`
`1
`Hardwired Digital
`Blocks
`
`Volatile Memory
`
`IE @ @ //22
`
`__
`
`/ ,/
`
`i
`
`Ana'og "0
`
`,
`
`/
`20
`Digital l/O
`FIG. 1
`
`

`

`U.S. Patent
`
`Sep. 5, 2006
`
`Sheet 2 of 17
`
`US 7,102,391 B1
`
`._<_.ZON_m_OI2BoxF
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`

`

`U.S. Patent
`
`Sep. 5, 2006
`
`Sheet 3 0f 17
`
`US 7,102,391 B1
`
`Programmable System
`on Chip Device
`
`Digital V0
`
`__
`
`\
`\
`
`60
`
`70
`/
`/
`/
`
`I
`
`Digital l/O
`\\
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`
`70//'
`
`55
`Nam-Volatile
`emory
`Non-Volatile
`“m
`
`V l
`olatile Memory
`
`2
`
`Programmable Logic
`Block
`
`Hardwired Analog
`Blocks
`@' @l @
`@@@
`
`74
`
`System
`Controller
`
`my; 79
`E Clock
`
`Hardwired Digital
`Blocks
`
`Volatile Memory
`
`/72
`@ g] Q /
`/
`
`_
`
`/
`
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`
`/
`/
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`l/O
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`"a °9
`
`/
`/
`/
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`
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`
`FIG. 3
`
`

`

`U.S. Patent
`
`Sep. 5,2006
`
`Sheet 4 0f 17
`
`US 7,102,391 B1
`
`Programmable System
`on Chip Device
`
`\
`
`_
`
`80
`
`/
`30
`
`Digital I/O\
`
`Q.
`Non-Volatile
`Memory
`Non-Volatile
`Memory
`Control
`
`Digital l/O\
`
`\
`
`Volatile Memory
`
`90/
`
`Programmable Logic
`Block
`
`Volatile Memory
`
`Microprocessor
`
`E
`
`\
`\
`
`/
`/
`
`l
`
`Hardwired Analog
`Blocks
`@
`@Fill?
`
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`M
`96
`em; \ Clock
`
`Hardwired Digital
`Blocks
`@@@
`@@@
`
`/92
`
`/
`90
`Digital l/O
`
`FIG. 4
`
`Analog H0
`
`

`

`U.S. Patent
`
`Sep. 5, 2006
`
`Sheet 5 0f 17
`
`US 7,102,391 B1
`
`General Purpose V0
`
`116 /
`
`V0 Tiles
`
`114
`
`112
`
`120
`
`FPGA Core
`
`11
`
`Interface Tiles (CT_US)
`
`1
`
`Ext Clk
`
`Ext
`Xtal
`
`140
`System
`Supervisor
`Master
`142
`
`VCC
`
`Analog V0
`
`FIG. 5
`
`138
`
`

`

`U.S. Patent
`
`Sep. 5, 2006
`
`Sheet 6 0f 17
`
`US 7,102,391 B1
`
`|:: i 64
`
`/158
`
`160
`
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`
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`
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`
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`
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`
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`
`Clock A
`/
`152
`
`Select
`Line
`
`1 56
`
`Clock B
`
`154
`
`

`

`U.S. Patent
`
`Sep. 5, 2006
`
`Sheet 7 of 17
`
`US 7,102,391 B1
`
`5:2292oH
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`

`U.S. Patent
`
`Sep. 5, 2006
`
`Sheet 8 0f 17
`
`US 7,102,391 B1
`
`192
`
`250\
`
`252/W1
`
`VOUT=
`v|*(w2/vv1)
`
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`De- ‘- - Control Llnes
`From FPGA
`Coder
`
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`
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`
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`
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`
`-BSZQEQ _________________________________________________________________ _.
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`284
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`Note: Capacitors will be made using metal
`layers. Area occupied by 950ff~53 Oum2
`FIG. 9
`
`Switch C
`
`

`

`U.S. Patent
`
`Sep. 5, 2006
`
`Sheet 9 0f 17
`
`US 7,102,391 B1
`
`Monitor
`Diode
`
`{i
`
`354
`
`352
`
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`+/- 12V
`/342
`
`340
`Power MOS _
`(NMOS for Negative
`PMOS for Posmve)
`
`Load Side
`
`FIG. 11
`
`

`

`U.S. Patent
`
`Sep. 5, 2006
`
`Sheet 10 0f 17
`
`US 7,102,391 B1
`
`
`
`

`

`U.S. Patent
`
`Sep. 5, 2006
`
`Sheet 11 0f 17
`
`US 7,102,391 B1
`
`136
`
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`
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`
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`422/ sample ItYIIT'IEerCOHII'OI
`
`Control Inputs
`
`Digital Outputs
`
`FIG. 14
`
`

`

`U.S. Patent
`
`Sep. 5, 2006
`
`Sheet 12 of 17
`
`US 7,102,391 B1
`
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`U.S. Patent
`
`Sep. 5, 2006
`
`Sheet 13 0f 17
`
`US 7,102,391 B1
`
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`

`U.S. Patent
`
`Sep. 5, 2006
`
`Sheet 14 0f 17
`
`US 7,102,391 B1
`
`1/40
`
`"dd me’
`
`System controller Circuit Block
`452 Power Up Control Circuit _454
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`
`//146
`
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`
`/
`Voltage
`conversion/supply circuits / 144
`
`System Supervisor
`
`//148
`
`FIG. 16
`
`

`

`U.S. Patent
`
`Sep. 5, 2006
`
`Sheet 15 0f 17
`
`US 7,102,391 B1
`
`468
`
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`
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`

`U.S. Patent
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`Sep. 5, 2006
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`US 7,102,391 B1
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`U.S. Patent
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`Sep.5,2006
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`Sheet17 0f17
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`US 7,102,391 B1
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`US 7,102,391 B1
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`1
`CLOCK-GENERATOR ARCHITECTURE FOR
`A PROGRAMMABLE-LOGIC-BASED
`SYSTEM ON A CHIP
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`This application is a Continuation-in-Part of co-pending
`US. patent application Ser. No. 10/843,701, ?led May 10,
`2004, and this application claims priority from US. Provi
`sional Patent application Ser. No. 60/491,788, ?led Jul. 31,
`2003.
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`The present invention relates to integrated circuits. More
`particularly, the present invention relates to a system-on-a
`chip integrated circuit device including a programmable
`logic block, at least one user non-volatile memory block,
`and analog circuits on a single semiconductor integrated
`circuit chip, ?ip chip, face-to-face, or other multiple die
`con?guration.
`2. Background
`Field-programmable gate array (FPGA) integrated cir
`cuits are knoWn in the art. An FPGA comprises any number
`of logic modules, an interconnect-routing architecture and
`programmable elements that may be programmed to selec
`tively interconnect the logic modules to one another and to
`de?ne the functions of the logic modules. To implement a
`particular circuit function, the circuit is mapped into the
`array and the appropriate programmable elements are pro
`grammed to implement the necessary Wiring connections
`that form the user circuit.
`An FPGA includes an array of general-purpose logic
`circuits, called cells or logic blocks, Whose functions are
`programmable. Programmable buses link the cells to one
`another. The cell types may be small multifunction circuits
`(or con?gurable functional blocks or groups) capable of
`realiZing Boolean functions of multiple variables. The cell
`types are not restricted to gates. For example, con?gurable
`functional groups typically include memory cells and con
`nection transistors that may be used to con?gure logic
`functions such as addition, subtraction, etc., inside of the
`FPGA. A cell may also contain a plurality of ?ip-?ops. TWo
`types of logic cells found in FPGA devices are those based
`on multiplexers and those based on programmable read only
`memory (PROM) table-lookup memories. Erasable FPGAs
`can be reprogrammed many times. This technology is espe
`cially convenient When developing and debugging a proto
`type design for a neW product and for small-scale manufac
`ture.
`An FPGA circuit can be programmed to implement vir
`tually any set of digital functions. Input signals are pro
`cessed by the programmed circuit to produce the desired set
`of outputs. Such inputs ?oW from the user’s system, through
`input bulfers and through the circuit, and ?nally back out the
`user’s system via output bulfers referred to as input/output
`ports (I/Os). Such bulfers provide any or all of the folloWing
`input/output (I/O) functions: voltage gain, current gain, level
`translation, delay, signal isolation or hysteresis. The input/
`output ports provide the access points for communication
`betWeen chips. I/O ports vary in complexity depending on
`the FPGA.
`Recent advances in user-programmable interconnect tech
`nology have resulted in the development of FPGAs Which
`may be customiZed by a user to perform a Wide variety of
`
`2
`combinatorial and sequential logic functions. Numerous
`architectures for such integrated circuits are knoWn.
`Examples of such architectures are found disclosed in US.
`Pat. No. 4,870,302 to Freeman, US. Pat. No. 4,758,745 to
`El Gamal et al., and US. Pat. No. 5,132,571 to McCollum
`et al. The architecture employed in a particular FPGA
`integrated circuit Will determine the richness and density of
`the possible interconnections that can be made among the
`various circuit elements disposed on the integrated circuit
`and thus profoundly a?fect its usefulness.
`Traditionally, FPGAs and other programmable logic
`devices (PLDs) have been limited to providing digital logic
`functions programmable by a user. Recently, hoWever,
`FPGA manufacturers have experimented With adding appli
`cation speci?c integrated circuit (ASIC) blocks onto their
`devices (See, e.g., US. Pat. No. 6,150,837). Such ASIC
`blocks have included analog circuits (see US. Pat. No.
`5,821,776). In addition, ASIC manufacturers have embed
`ded programmable logic blocks in their devices to add
`programmable functionality to otherWise hardWired devices
`(See, e.g., devices offered (or formerly o?‘ered) by Triscend
`Corporation, Adaptive Silicon Inc., and Chameleon Sys
`tems.
`Programmable logic devices With clock-conditioning cir
`cuitry including a phase lock loop circuit (PLL) are knoWn
`in the art, such as FPGAs (see, e.g., the Accelerator product
`available from Actel Corporation, Mountain VieW, Calif.),
`and CPLDs (see US. Pat. No. 6,272,646 to Rangasayee et
`al.). Programmable logic devices such as FPGAs, hoWever,
`do not typically include an on-chip crystal oscillator circuit
`or an RC oscillator circuit.
`System on a chip devices With analog circuitry; program
`mable logic, such as registers for con?guring and selecting
`the other circuitry on the device, and an on-chip crystal
`oscillator circuit are knoWn (see, e.g., US. Pat. No. 5,563,
`526 to Hastings and US. Pat. No. 6,614,320 to Sullam).
`Although the system on a chip disclosed by Sullam includes
`a PLL circuit and a selectable clock signal (32 KHZ or 24
`MHZ), the clocking circuitry is not programmable to output
`multiple clock frequencies along a broad spectrum of fre
`quencies, according to user needs. The PLL disclosed in
`Sullam is used to provide a precise clocking signal, but is not
`con?gurable to synthesiZe arbitrary clock frequencies.
`While these devices contain “programmable logic,” it is
`not logic of the type that can manage the overall operation
`of the system on a chip device, but logic that functions as
`registers and con?guration bits to select various circuits and
`make selected connections on the system on a chip devices.
`The logic is not of a su?icient siZe or density or complexity
`to be programmed to perform most any arbitrary function
`that might be required by a complex user circuit design to be
`programmed into the system on a chip device. Furthermore,
`the programmable logic of the knoWn system on a chip
`devices described above cannot function as the master
`control of the system on a chip device (see, e.g., Sullam,
`Where a microcontroller functions as the master control of
`the device). In addition to Sullam, other knoWn system on a
`chip devices have included a real time clock (see, e.g., US.
`Pat. Nos. 5,687,325 and 6,260,087 to Chang). The real time
`clock disclosed in the system of Chang, hoWever, functions
`to initiate DRAM refresh cycles.
`
`SUMMARY OF THE INVENTION
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`A programmable system-on-a-chip integrated circuit
`device comprises at least one of a crystal oscillator circuit,
`an RC oscillator circuit, and an external oscillator input. A
`
`

`

`US 7,102,391 B1
`
`3
`clock conditioning circuit is selectively coupleable to one of
`the programmable logic block, the crystal oscillator circuit,
`the RC oscillator circuit, and the external oscillator input. A
`real-time clock is selectively coupleable to one of the
`programmable logic block, the crystal oscillator circuit, the
`RC oscillator circuit, and the external oscillator input. A
`programmable logic block is coupled to the clock condi-
`tioning circuit and the real-time clock.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a block diagram of one illustrative embodiment
`of a system-on-a-chip according to one aspect of the present
`invention.
`
`FIG. 2 is a simplified diagram of a portion of an illustra-
`tive interconnect architecture that may be used to intercon-
`nect the inputs and outputs of the various circuit elements of
`the system-on-a-chip of FIG. 1 to form user circuit systems.
`FIG. 3 is a block diagram of another illustrative embodi-
`ment of a system-on-a-chip that includes a volatile memory
`block such as an SRAM block.
`
`FIG. 4 is a block diagram of another illustrative embodi-
`ment of a system-on-a-chip based on use of a highly
`successful flash FPGA architecture, for the programmable
`logic block.
`FIG. 5 is a block diagram of another illustrative embodi-
`ment of a system-on-a-chip based on use of a flash FPGA
`architecture for the programmable logic block.
`FIG. 6 is a schematic diagram of an illustrative glitchless
`clock multiplexer that is suitable for use in the SOC of the
`present invention.
`FIG. 7 is a block diagram ofa portion of the SOC of FIG.
`5 showing analog I/O function circuits grouped into sets
`according to one illustrative embodiment of the present
`invention.
`
`FIG. 8 is a diagram of a pre-scaler circuit that can scale
`external voltages by one of eight factors.
`FIG. 9 is a diagram of an illustrative configuration for the
`amplifier of FIG. 7.
`FIG. 10 is a diagram of an illustrative temperature moni-
`tor circuit that may be usefully employed in the analog I/O
`function circuit of FIG. 7.
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`FIG. 11 is a diagram of an illustrative gate drive circuit
`that may be usefully employed in the analog I/O function
`circuit of FIG. 7.
`
`45
`
`FIG. 12 is a diagram of an illustrative embodiment of
`internal interface circuits from FIG. 5 that are particularly
`useful for the SOC of the present invention.
`FIG. 13 is a schematic diagram of an illustrative bandgap
`reference that may be used in the SOC of the present
`invention.
`
`FIG. 14 is a more detailed diagram of the analog-to-digital
`converter shown in FIG. 5.
`
`FIG. 15A is a power-up sequence state-machine flow
`chart showing a typical SOC internal power up sequence.
`FIG. 15B is a timing diagram showing a typical SOC
`internal power up sequence.
`FIG. 16 is a more detailed block diagram of system
`supervisor master block 140 from FIG. 5.
`FIG. 17 is a diagram showing an illustrative power-up
`control circuit for performing functions in the power-up
`sequence of the SOC of the present invention.
`FIG. 18 is a block diagram showing a clock-generator
`architecture for a programmable-logic-based system on a
`chip according to the present invention.
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`FIG. 19 is a block diagram showing a more detailed view
`of the operation of an illustrative real time clock in the
`system on a chip of the present invention.
`
`DETAILED DESCRIPTION
`
`US. Provisional Patent application Ser. No. 60/491,788,
`filed Jul. 31, 2003 is hereby incorporated by reference into
`this disclosure. Those of ordinary skill in the art will realize
`that the following description of the present invention is
`illustrative only and not in any way limiting. Other embodi-
`ments of the invention will readily suggest themselves to
`such skilled persons.
`The term “system-on-a-chip” or “SOC” generally refers
`to an integrated circuit device that includes multiple types of
`integrated circuits on a single die, where the circuits are of
`types that have traditionally been constructed on separate
`silicon wafers.
`
`An SOC 10 according to the present invention design is
`shown generally in a block-diagram architectural
`level
`drawing in FIG. 1, which shows its main components. As
`shown in FIG. 1, an illustrative embodiment of the present
`invention is a system-on-a-chip integrated circuit 10 that
`includes a programmable logic block 12, at least one non-
`volatile memory block 14, analog ASIC circuit blocks 1611
`through 16f, digital ASIC circuit blocks 1811 through 18f,
`digital input/output (“I/O”) circuit blocks 20 and analog I/O
`circuit blocks 22. ASIC refers to “application specific inte-
`grated circuits” and is used to refer to circuit blocks that are
`largely hardwired,
`in contrast to those that are program-
`mable, writeable, or otherwise able to be modified or con-
`figured after manufacturing of the device. System-on—a-chip
`integrated circuit 10 also includes a system controller circuit
`block 24 and a clock circuit 26.
`
`Programmable logic block 12 may be an FPGA array.
`FPGA arrays are well known in the art, and it is contem-
`plated for purposes of the present invention that any type of
`FPGA circuit block may be employed in the system-on-a-
`chip integrated circuit 10 of the present
`invention. The
`number of data inputs and outputs and the number of
`implementable combinatorial and sequential logic functions
`will depend on the particular design of FPGA circuit used in
`the FPGA array. Persons of ordinary skill in the art will
`appreciate that other programmable logic blocks such as
`complex programmable logic devices (CPLD) and other
`programmable logic blocks may be used in the present
`invention.
`
`Non-volatile memory block 14 may be formed from an
`array of, as a non-limiting example, flash memory cells and
`a memory controller for the array. Flash memory cells are
`well known in the art and the present invention is not limited
`to use of any particular kind of flash memory cells or other
`non-volatile memory technology,
`such as nanocrystal,
`SONOS, solid-electrolyte switching devices, and other types
`as will be appreciated by persons of ordinary skill in the art.
`Persons of ordinary skill in the art will appreciate that, in
`some embodiments of the present invention, non-volatile
`memory block 14 may be segmented into a plurality of
`separately addressable arrays, each with its own memory
`controller. The number of data inputs and outputs and
`address inputs will depend on the size of the array used.
`Analog ASIC circuit blocks 1611 through 16f are illus-
`trated in FIG. 1, although persons of ordinary skill in the art
`will observe that the provision of six analog ASIC circuit
`blocks 1611 through 16f in FIG. 1 is merely illustrative and
`in no way limiting. Actual embodiments of system-on-a-
`chip integrated circuits according to the present invention
`
`

`

`US 7,102,391 B1
`
`5
`may have an arbitrary number of analog ASIC circuit blocks.
`Analog ASIC circuit blocks 1611 through 16f may alterna-
`tively be described as “hardwired,” “mask programmable,”
`or “ASIC” circuits or circuit blocks. These analog blocks are
`also referred to as “analog peripherals,” and may include, as
`non-limiting examples, a digital-to-analog converter (DAC),
`an analog-to-digital converter (ADC), a Pulse Width Modu-
`lator (PWM), a MOSFET Controller, a Voltage Reference
`circuit, a Low-dropout (LDO) regulator, an Analog multi-
`plexer (MUX), or an RF Transceiver. In addition to the more
`general-purpose types of analog blocks described above,
`stand alone analog circuit blocks for more specific functions
`may be provided, as described above. For example, a
`stand-alone hardwired current monitor, a stand-alone hard-
`wired temperature monitor, or a stand-alone hardwired volt-
`age monitor may be provided. Stand-alone hard analog
`blocks may include I/O circuits.
`Embedded analog peripherals may also be used to
`enhance generic microcontroller (“MCU”) functions with a
`programmable “soft” processor core programmed into the
`programmable logic block. As will be appreciated by per-
`sons of ordinary skill in the art, the numbers and kinds of
`inputs and outputs of the individual analog ASIC circuit
`blocks 1611 through 16fwill depend on the functional nature
`of the circuits employed.
`Digital ASIC circuit blocks 1811 through 18fare illustrated
`in FIG. 1, although persons of ordinary skill in the art will
`observe that the provision of six digital ASIC circuit blocks
`1811 through 18f in FIG. 1 is merely illustrative and in no
`way limiting. Actual embodiments of system-on-a-chip inte-
`grated circuits according to the present invention may have
`an arbitrary number of digital ASIC circuit blocks. Digital
`ASIC circuit blocks 1811 through 18f may comprise circuit
`blocks such as, but not limited to, state machines, analog
`sequencers, microprocessors, digital
`signal processors
`(“DSPs”). Hard digital blocks are especially useful to imple-
`ment interfaces such as the interface between the program-
`mable logic and the memory blocks on a device. The
`FPGA/Memory interface is described in more detail in the
`section describing the non-volatile memory controller. Hard
`digital blocks may also be used to implement interfaces
`between the programmable logic or the memory blocks and
`hard analog blocks. A hard digital block is used as a control
`block for the non-volatile memory block. The non-volatile
`memory controller is described in more detail herein.
`Such digital blocks may be implemented in a similar
`manner to the way in which such digital blocks are imple-
`mented in current application-specific integrated circuits
`(“ASICs”). In addition to being implemented as hard digital
`circuit blocks, all, or a portion of each of these types of
`blocks may be implemented in programmable logic, some-
`times referred to as “soft” implementations. As will be
`appreciated by persons of ordinary skill
`in the art,
`the
`numbers and kinds of inputs and outputs of the individual
`digital ASIC circuit blocks 1811 through 18f will depend on
`the functional nature of the circuits employed.
`System-on-a-chip integrated circuit 10 also includes digi-
`tal I/O circuit blocks 20. Digital I/O circuit blocks 20 may
`comprise conventional digital I/O circuitry, such as that
`commonly employed in known FPGA and similar integrated
`circuits.
`
`System-on-a-chip integrated circuit 10 also includes ana-
`log I/O circuit blocks 22. Analog I/O circuit blocks 22 may
`comprise any of the many analog amplifier circuits that are
`well known in the art.
`
`System-on-a-chip integrated circuit 10 also includes a
`system controller circuit block 24. A system controller
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`circuit block 24 provides master control functionality for the
`other blocks in the SOC device, including managing power
`up sequencing and inter-operation of the various compo-
`nents of the system on a chip. In addition,
`the system
`controller 24 may control off-chip devices via signals output
`via the digital or analog I/Os of the device of the present
`invention such as reset and enable signals. The system
`controller 24 includes various circuits for managing the
`different functions of the SOC device. In some embodi-
`
`ments, these circuits may all be implemented in hardwired
`circuit blocks, while in other embodiments, some of the
`circuits may be implemented in a portion of the program-
`mable logic of the programmable logic block 12. An advan-
`tage of implementing control functions in programmable
`logic is that the user is able to adapt the control functions to
`the user’s application. This is especially useful if the user
`wishes to employ the programmable system on a chip device
`to control elements of the user’s system that are outside the
`system on a chip device.
`In the embodiment of a system controller shown in FIG.
`1, a portion of the system controller’s circuits are imple-
`mented in hardwired blocks, and a portion are implemented
`in programmable logic. The system controller 24 shown in
`FIG. 1 includes a power-up control circuit, an analog power
`supply circuit, a voltage reference circuit, and a system
`supervisor circuit. The power-up control circuit includes
`circuitry for managing the SOC device during power-up, as
`will be