(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2006/0080515 A1
`(43) Pub. Date:
`Apr. 13, 2006
`Spiers et al.
`
`US 20060080515A1
`
`(54) NON-VOLATILE MEMORY BACKUP FOR
`NETWORK STORAGE SYSTEM
`
`(75) Inventors: John Spiers, Louisville, CO (US);
`Mark Lo?redo, Libertyville, IL (US);
`Mark G. Hayden, Fair?eld, CA (US);
`Mike A. Hayward, Boulder, CO (US)
`
`Correspondence Address:
`KENNETH C. WINTERTON
`HOLLAND & HART LLP
`P. 0. BOX 8749
`DENVER, CO 80201-8749 (US)
`
`(73) Assignee: LEFTHAND NETWORKS,
`Boulder, CO (US)
`
`INC.,
`
`(21) Appl. No.:
`
`10/711,901
`
`(22) Filed:
`
`Oct. 12, 2004
`
`Publication Classi?cation
`
`(51) Int, C],
`G06F 12/00
`
`(2006.01)
`
`(52) US. Cl. ............................................. .. 711/162; 714/14
`
`(57)
`
`ABSTRACT
`
`A data storage system including a primary data storage
`device and a backup data storage device stores data With
`enhanced performance. The primary data storage device has
`a primary data storage device memory for holding data, and
`the backup data storage device has a backup volatile
`memory, a backup non-volatile memory, and a processor.
`The backup storage device processor causes a copy of data
`provided to the primary data storage device to be provided
`to the backup data storage device volatile memory, and in
`the event of a poWer interruption moves the data from the
`backup volatile memory to the backup non-volatile memory.
`In such a manner, data stored at the backup data storage
`device is not lost in the event of a poWer interruption. The
`backup data storage device further includes a backup poWer
`source such as a capacitor, a battery, or any other suitable
`poWer source, and upon detection of a poWer interruption,
`switches to the backup poWer source and receives poWer
`from the backup poWer source While moving the data from
`the backup volatile memory to the backup non-volatile
`memory.
`
`250
`RECEIVE DATA TO BE STORED J
`FROM APPLICATION
`
`‘
`SEND COMMAND TO BACKUP
`DEVICE TO STORE DATA J
`
`254
`
`'1
`
`258
`
`NO
`
`RECEIVE
`ACKNOWLEDGEMENT
`
`REPORT TO APPLICATION THAT
`DATA IS STORED
`
`T
`ANALYZE PHYSICAL ADDRESS(ES)
`OF DATA AND RE-ORDER DATA, AND
`ANY OTHER DATA PRESENT, BASED
`ON PHYSICAL ADDRESS(ES)
`
`262
`
`266
`
`2
`WRITE DATA TO STORAGE DEVICE J
`
`T
`VERIFY DATA HAS BEEN WRITTEN
`TO THE STORAGE DEVICE MEDIA
`
`2
`
`REMOVE DATA FROM BACKUP DEVICE K
`
`T
`
`

`

`Patent Application Publication Apr. 13, 2006 Sheet 1 0f 14
`
`US 2006/0080515 A1
`
`APPLICATION
`
`I104
`
`APPLICATION
`
`f 104
`
`100
`
`f 108
`
`NAS
`
`f 108
`
`NAS
`
`FIG.1
`
`

`

`Patent Application Publication Apr. 13, 2006 Sheet 2 0f 14
`
`US 2006/0080515 A1
`
`108
`
`_/ 112
`
`NETWORK ATTACHED STORAGE
`
`NETWORK INTERFACE
`
`OPERATING
`SYSTEM
`g)
`
`MEMORY
`
`Kl
`
`BUS
`
`>,
`L 128
`
`STORAGE
`DEV|CE(S)
`
`STORAGE
`CONTROLLER
`
`BACKUP
`DEV|CE(S)
`
`)
`(
`(
`136 / \132 \140
`
`FIG.2
`
`

`

`Patent Application Publication Apr. 13, 2006 Sheet 3 0f 14
`
`US 2006/0080515 A1
`
`132
`
`STORAGE
`CONTROLLER
`
`<
`
`Bus
`
`140
`k STORAGE DEVICE
`
`144
`
`BACKUP
`DEVICE
`
`WRITE-BACK
`CACHE
`
`148 J
`
`FIG.3
`
`

`

`Patent Application Publication Apr. 13, 2006 Sheet 4 0f 14
`
`US 2006/0080515 A1
`
`152
`l
`
`POWER
`SUPPLY
`
`144
`j
`
`156
`
`BACKUP DEV|CE
`
`|NTERFACE
`
`160 \ PROCESSOR
`
`VOLATILE
`\ MEMORY
`
`_* 168
`
`NON-
`VOLATILE
`MEMORY
`\
`k 164
`
`FlG.4
`
`

`

`Patent Application Publication Apr. 13, 2006 Sheet 5 0f 14
`
`US 2006/0080515 A1
`
`176
`
`210
`
`194
`
`218
`
`190
`
`144
`
`P
`
`184
`
`329
`
`C
`
`22:22
`
`PROCESSOR
`
`180
`
`r
`
`— is
`
`_
`
`HHHHHHHHHHWHW #190
`
`Y J
`172
`
`

`

`Patent Application Publication Apr. 13, 2006 Sheet 6 0f 14
`
`US 2006/0080515 A1
`
`250
`RECEIVE DATA TO BE STORED J
`FROM APPLICATION
`254
`I’
`SEND COMMAND TO BACKUP J
`DEVICE TO STORE DATA
`
`NO
`
`RECEIVE
`ACKNOWLEDGEMENT
`
`REPORT TO APPLICATION THAT
`DATA IS STORED
`
`I
`
`258
`
`262
`
`K
`
`266
`
`ANALYZE PHYSICAL ADDRESS(ES)
`OF DATA AND RE-ORDER DATA, AND
`ANY OTHER DATA PRESENT, BASED
`ON PHYSICAL ADDRESS(ES)
`2
`I
`WRITE DATA TO STORAGE DEVICE J
`
`I
`
`2
`
`VERIFY DATA HAS BEEN WRITTEN
`TO THE STORAGE DEVICE MEDIA
`278
`I
`REMOVE DATA FROM BACKUP DEVICE J
`
`FIG.6
`
`

`

`Patent Application Publication Apr. 13, 2006 Sheet 7 0f 14
`
`US 2006/0080515 A1
`
`300
`_/
`
`304
`
`POWER ON
`+
`LOAD PROCESSOR OPERATING
`INSTRUCTIONS FROM PROM
`308
`+
`BEGIN CHARGING CAPACITORS J
`+
`312
`INITIALIZE, TEST, AND zERO
`SDRAM J
`+
`316
`CHECK NvRAM STATUS IN
`EEPROM J
`
`320
`
`|s NvRAM
`VALID?
`
`3/24
`UPDATE EEPROM STATISTICS
`
`328
`TRANSFER NvRAM TO SDRAM J
`+
`332
`\ MARK SDRAM VALID <—
`
`336
`
`CAPACITORS
`CHARGED '2
`
`ENABLE WRITES
`+
`ENABLE SDRAM TO NvRAM
`TRANSFER
`+
`MARK NvRAM AS INVALID IN
`EEPROM
`
`340
`~/
`344
`‘/
`348
`~/
`
`FIG.7
`
`

`

`Patent Application Publication Apr. 13, 2006 Sheet 8 0f 14
`
`US 2006/0080515 A1
`
`/1
`
`RESET
`
`|
`
`388
`
`IS SDRAM-NVRAM
`XFER IN PROGRESS?
`
`YES
`
`INITIALIZE, TEST, AND ZERO
`SDRAM J
`i
`368
`CHECK NVRAM STATUS IN J @322“; igmgFTEg
`EEPROM
`
`392
`K
`
`N0
`
`372
`
`384
`
`(
`
`TRANSFER NVRAM YES
`TO SDRAM
`
`NO
`
`376
`
`380
`
`| UPDATE EEPROM STATISTICS lI/i
`
`AF] MARK SDRAMVALID hi
`396
`
`CAPACITORS
`CHARGED ?
`YES
`ENABLE WRITES
`L
`ENABLE SDRAM TO NVRAM
`408
`#
`MARK NVRAM AS INVALID IN J
`
`400
`|~/
`404
`
`|
`
`|
`
`EEPROM %
`
`412
`
`FIG.8
`
`

`

`Patent Application Publication Apr. 13, 2006 Sheet 9 0f 14
`
`US 2006/0080515 A1
`
`V
`
`READY
`
`420
`
`E IS DESCR|PTOR PO|NTER
`FIFO EMPTY?
`
`O
`READ DESCR|PTOR PO|NTER FIFO AND
`LOAD DESCR|PTOR BASE ADDRESS
`+
`ASSERT BUS REQUEST
`
`424
`
`428
`
`432
`
`BUS GRANTED?
`
`436
`
`READ DESCR|PTOR AND WRITE
`DESCR|PTOR DATA TO LOCAL RAM
`
`440
`
`444
`
`460
`
`464
`
`2
`47
`
`480
`
`488
`
`496
`
`NO
`
`448
`/~
`|NCREMENT BAD
`DESCR|PTOR
`COUNT IN
`EEPROM
`
`452
`/~
`GENERATE BAD
`DESCR|PTOR
`|NTERRUPT
`
`YES
`456 6:)
`DECODE COMMAND TYPE |
`HALT PROCESSOR
`SRC=HOST
`YES TRANSFER FROM HOST
`DEST=SDRAM
`MEMORY TO SDRAM
`
`4
`68
`
`304
`GENERATE
`UNKNOWN ERROR
`|NTERRUPT
`
`NO
`SRC=SDRAM
`DEST=HOST
`
`NO
`SRC=SDRAM
`DEST=NvRAM
`
`NO
`
`476
`YES TRANSFER FROM SDRAM
`TO HOST MEMORY
`
`484
`YES TRANSFER FROM SDRAM
`TO NvRAM
`
`492
`
`SRC=NVRAIVI
`DEST=SDRAM
`
`YES TRANSFER FROM NvRAM
`TO SDRAM
`
`NO
`
`500
`
`SDRAM
`|N|T|AL|zAT|ON
`
`YES
`
`SEND SDRAM
`INITIALIZATION CYCLES
`
`NO
`
`FIG.9
`
`

`

`Patent Application Publication Apr. 13, 2006 Sheet 10 0f 14
`
`US 2006/0080515 A1
`
`468
`C TRANSFER FROM HOST DJ
`MEMORY TO SDRAM
`+
`508
`ASSERT BUS REQUEST ~/
`
`512
`
`532
`
`READ DATA FROM
`HOST MEMORY
`Jr
`WRITE DATA TO SDRAM
`{I
`GENERATE CRC VALUE
`Jr
`ASSERT BUS REQUEST
`
`J
`5
`J
`524
`J
`5
`J
`
`BUS GRANT ?
`
`536
`
`CALCULATE DESCRIPTOR
`CRC RESULT ADDRESS
`540
`#
`STORE CRC RESULT AND _/
`DESCRIPTOR STATUS
`
`FIG.10
`
`

`

`Patent Application Publication Apr. 13, 2006 Sheet 11 0f 14
`
`US 2006/0080515 A1
`
`TRANSFER FROM SDRAM
`TO HOST MEMORY
`
`45. 76
`
`2% 4S
`
`SET SDRAM WRITE ADDRESS J
`¢
`548
`READ SDRAM DATA ~/
`I
`552
`WRITE DATA TO INTF FIFO J
`AND GENERATE CRC
`+
`556
`ASSERT BUS REQUEST J
`4
`
`&
`
`564
`YES
`READ DATA FROM INTF FIFO, J
`WRITE DATA TO BUS
`568
`I
`ASSERT BUS REQUEST J
`
`560
`
`572
`
`CALCULATE DESCRIPTOR CRC _/
`RESULT ADDRESS
`I
`580
`SToRE CRC RESULT AND J
`DESCRIPTOR STATUS
`
`FIG.11
`
`

`

`Patent Application Publication Apr. 13, 2006 Sheet 12 0f 14
`
`US 2006/0080515 A1
`
`484
`
`592
`
`'
`
`TRANSFER FROM
`SDRAM TO NVRAM
`
`584
`INITIALIZE NvRAM BLOCK J 664
`ERASE ADDRESS
`588 \ MARK NvRAM
`+
`SEND NvRAM BLOCK J 668
`AS \fL'D
`ERASE COMMAND
`\ ASSERT BUS
`NO
`REQUEST
`BLOCK ERASE DONE ? V
`596
`YE
`SET SDRAM READ ADDRESS; J 672
`CALCULATSE
`INITIALIZE CRC
`600
`iv
`676
`READ SDRAM DATA
`|~/6O4 ,\ iggicgég??
`+
`ADDRESS
`WR|TE DATA TO INTF F|FO, J
`GENERATE CRC
`+
`680
`605
`STORE CRC
`J'
`RESULT AND
`SEND NvRAM PAGE WR|TE CMD |_/612
`DESCRWTOR
`+
`J STATUS
`READ DATA FROM INTF FIFO RAM;
`WR|TE DATA TO NvRAM PAGE RAM '
`
`1
`<—6 6
`660 MARK NVRAM
`\ TRANSFER
`ADDRESS
`656
`+
`\ MARK BLOCK
`As BAD IN PAGE
`
`NO
`
`INCREMENT
`64?“ BAD BLOCK 4
`COUNT
`
`PAGE BURST DONE ?
`
`620
`
`SET SDRAM READ ADDRESS;
`INITIALIZE CRC
`+
`YES
`NvRAM WR|TE DONE ? /J READ SDRAM DATA
`M
`628/~| WR|TE DATA TO INTF FIFO |
`
`NO
`
`624
`
`|
`
`632/4SEND NvRAM PAGE READ CMD|
`636
`READ DATA FROM |NTF FIFO
`640/
`AND FROM NVRAM PAGE RAM
`644
`
`FlG.12
`
`NO
`
`’?
`COMPARE OK .
`
`YES
`
`

`

`Patent Application Publication Apr. 13, 2006 Sheet 13 0f 14
`
`US 2006/0080515 A1
`
`492
`C TRANSFER FROM DJ
`NvRAM TO SDRAM
`4
`684
`SET NvRAM READ ADDRESS J
`T
`688
`SEND NvRAM PAGE J
`READ COMMAND
`692
`#
`READ DATA FROM NvRAM J
`PAGE RAM; vvR|TE DATA TO
`INTF F|FO
`696
`T
`SET SDRAM WRITE ADDRESS; J
`INITIALIZE CRC
`4
`700
`READ DATA FROM INTF FIFO J
`AND GENERATE CRC VALUES
`4
`704
`ASSERT BUS REQUEST J
`4
`
`708
`
`BUS GRANT ? &
`
`712
`YES
`CALCULATE DESCRIPTOR CRC J
`RESULT ADDRESS
`+
`716
`STORE CRC RESULT AND _/
`DESCRIPTOR STATUS
`
`FIG.13
`
`

`

`Patent Application Publication Apr. 13, 2006 Sheet 14 0f 14
`
`US 2006/0080515 A1
`
`)
`INCREMENT BLOCK
`ERASE ADDRESS
`
`+
`INCREMENT BAD
`BLOCK COUNT IN
`EEPROM
`I,
`PAGE BURST LEN ‘
`
`796 /
`
`800\
`DATA READ FROM
`INTF FIFO
`DATA WRITE TO
`FLASH PAGE RAM
`804
`
`BURST DONE?
`
`START LED BLINK
`
`756
`NVRAIVI STATUS IS
`BAD VCAP
`IN XFER
`
`,,
`
`764W —’, 780\ —’,812\
`760\
`POWER FAIL DEFECT
`_> INIT FLASH BLOCK
`SET SDRAM READ
`SET SDRAM READ
`ERASE ADDRESS
`ADDRESS BURST
`ADDRESS BURST
`AUTOMATIC
`720
`, POWER SWITCH 4')
`LEN ROTATE
`LEN ROTATE
`724
`To CAPS
`SEND FLASH BLOCK
`AMOUNT BYTE
`AMOUNT BYTE
`I
`ERASE COMMAND
`ENABLES
`ENABLES
`816
`r ABORT CURRENT
`|N|T+CRC
`|N|T+CRC
`728 AEg'$F:|’g$:TT|'EOF§'C|
`”\ START READ OF
`START READ OF )
`4'
`SDRAM DATA
`SDRAM DATA 820
`M
`'NCRE'V'ENT
`DATA WRITTEN TO
`DAUDNVTVFRLILE? To
`POWER FA'L
`INTF FIFO £4
`732 CCEEEIRFJRMIN
`GENERATE CRC
`SEND FLASH PAGE
`VALUES DURING
`READ COMMAND 828
`vvRITE TO FIFO H
`*
`DATA READ FROM /
`PAGE BURST LEN =
`|NTF FHIO
`512
`DATA READ FROM
`SEND FLASH PAGE
`FLASH PAGE RAM
`vvRITE COMMAND 832
`I
`COMPARE
`DATA OK,
`-
`
`MARK FLASH
`_> NVRAIVI STATUS IS
`BLgiié?Spiglg IN
`/ DISABLED XFER *
`740
`(ADDRESS 524)
`NVRAM STATUS IS 4
`4,
`BAD BLOCK MAX
`r
`\*l UP DATE FLASH
`856
`xFER ADDRESS
`(xFER ADDRESS +=
`/ PAGE BURST LEN)
`852 '—
`
`FIG.14
`
`_ IN EEPROM MARK
`} NVRAM INVALID
`744
`
`IN EEPROM INCR NvRAM
`HALT AND POWER
`COPY COUNT & STOP LED
`DOWN
`7 48 Q IN EEPROM MARK
`876’
`NvRAM vALID
`
`UPDATE xFER
`ADDRESS (XFER
`ADDRESS += PAGE
`BURST LEN)
`UPDATE XFER
`LENGTH xFER
`J;
`LENGTH PAGE
`BURST LEN)
`
`\
`
`

`

`US 2006/0080515 A1
`
`Apr. 13, 2006
`
`NON-VOLATILE MEMORY BACKUP FOR
`NETWORK STORAGE SYSTEM
`
`FIELD OF THE INVENTION
`
`[0001] The present invention relates to non-volatile data
`backup in a storage system, and, more speci?cally, to a data
`backup device utilizing volatile memory and non-volatile
`memory.
`
`BACKGROUND OF THE INVENTION
`
`[0002] Data storage systems are used in numerous appli
`cations and have Widely varying complexity related to the
`application storing the data, the amount of data required to
`be stored, and numerous other factors. A common require
`ment is that the data storage system securely store data,
`meaning that stored data Will not be lost in the event of a
`poWer loss or other failure of the storage system. In fact,
`many applications store data at primary data storage systems
`and this data is then backed-up, or archived, at predeter
`mined time intervals in order to provide additional levels of
`data security.
`[0003] In many applications, a key measure of perfor
`mance is the amount of time the storage system takes to store
`data sent to it from a host computer. Generally, When storing
`data, a host computer Will send a Write command, including
`data to be Written, to the storage system. The storage system
`Will store the data and report to the host computer that the
`data has been stored. The host computer generally keeps the
`Write command open, or in a “pending” state, until the
`storage system reports that the data has been stored, at Which
`point the host computer Will close the Write command. This
`is done so that the host computer retains the data to be
`Written until the storage system has stored the data. In this
`manner, data is kept secure and in the event of an error in the
`storage system, the host computer retains the data and may
`attempt to issue another Write command.
`
`[0004] When a host computer issues a Write command,
`overhead Within the computer is consumed While Waiting for
`the storage system to report that the Write is complete. This
`is because the host computer dedicates a portion of memory
`to the data being stored, and because the host computer uses
`computing resources to monitor the Write command. The
`amount of time required for the storage system to Write data
`depends on a number of factors, including the amount of
`read/Write operations pending When the Write command Was
`received, and the latency of the storage devices used by the
`storage system. Some applications utiliZe methods of reduc
`ing the amount of time required for the storage system to
`report that the Write command is complete, such as, for
`example, utiliZing a Write back cache Which reports that a
`Write command is complete before that data is Written to the
`media in the storage system. While this increases the per
`formance of the storage system, if there is a failure Within
`the storage system prior to the data being Written to the
`media, the data may be lost.
`
`SUMMARY OF THE INVENTION
`
`[0005] The present invention has recogniZed that a sig
`ni?cant amount of resources may be consumed in perform
`ing Write operations to Write data to a data storage device
`Within a data storage system. The resources consumed in
`such operations may be computing resources associated With
`
`a host computer, or other applications, Which utiliZe the data
`storage system to store data. Computing resources associ
`ated With the host computer may be underutilized When the
`host computer is Waiting to receive an acknoWledgment that
`the data has been Written to the storage device. This Wait
`time is a result of the speed and efficiency With Which the
`data storage system stores data.
`
`[0006] The present invention increases resource utiliZation
`When storing data at a storage system by reducing the
`amount of time a host computer Waits to receive an acknoWl
`edgment that data has been stored by increasing the speed
`and efficiency of data storage in a data storage system.
`Consequently, in a computing system utiliZing the present
`invention, host computing resources are preserved, thus
`enhancing the ef?ciency of the computing system.
`[0007] In one embodiment, the present invention provides
`a data storage system comprising (a) a ?rst data storage
`device including a ?rst data storage device memory for
`holding data, (b) a second data storage device including (i)
`a second data storage device volatile memory, (ii) a second
`data storage device non-volatile memory, and (iii) a proces
`sor for causing a copy of data provided to the ?rst data
`storage device to be provided to the second data storage
`device volatile memory, and in the event of a poWer inter
`ruption moving the data from the second data storage device
`volatile memory to the second data storage device non
`volatile memory. In such a manner, data stored at the second
`data storage device is not lost in the event of a poWer
`interruption.
`[0008] The ?rst data storage device, in an embodiment
`comprises at least one hard disk drive having an enabled
`volatile Write-back cache and a storage media capable
`storing data. The ?rst data storage device may, upon receiv
`ing data to be stored on the storage media, store the data in
`the volatile Write-back cache and generate an indication that
`the data has been stored before storing the data on the media.
`The ?rst data storage device may also include a processor
`executing operations to modify the order in Which the data
`is stored on the media after the data is stored in the
`Write-back cache. In the event of a poWer interruption, data
`in the Write-back cache may be lost, hoWever, a copy of the
`data Will continue to be available at the second data storage
`device, thus data is not lost in such a situation.
`
`[0009] In an embodiment, the second data storage device
`further comprises a secondary poWer source. The secondary
`poWer source may comprise a capacitor, a battery, or any
`other suitable poWer source. The second data storage device,
`upon detection of a poWer interruption, sWitches to the
`secondary poWer source and receives poWer from the sec
`ondary poWer source While moving the data from the second
`data storage device volatile memory to the second data
`storage device non-volatile memory. Upon completion of
`moving the data from the second data storage device volatile
`memory to the second data storage device non-volatile
`memory, the second data storage device shuts doWn, thus
`preserving the secondary poWer source.
`
`[0010] In one embodiment, the second data storage device
`non-volatile memory comprises an electrically erasable pro
`grammable read-only-memory, or a ?ash memory. The sec
`ond data storage device volatile memory may be a random
`access memory, such as a SDRAM. In this embodiment,
`upon detection of a poWer interruption, the processor reads
`
`

`

`US 2006/0080515 Al
`
`Apr. 13, 2006
`
`the data from the second data storage device volatile
`memory, Writes the data to the second data storage device
`non-volatile memory, and veri?es that the data stored in the
`second data storage device non-volatile memory is correct.
`The processor may verify that the data stored in the second
`data storage device non-volatile memory is correct by com
`paring the data from the second data storage device non
`volatile memory With the data from the second data storage
`device volatile memory, and re-Writing the data to the
`second data storage device non-volatile memory When the
`comparison indicates that the data is not the same. In another
`embodiment, the processor, upon detection of a poWer
`interruption, reads the data from the second data storage
`device volatile memory, computes an ECC for the data, and
`Writes the data and ECC to the second data storage device
`non-volatile memory.
`
`[0011] In a further embodiment, the ?rst data storage
`device and second data storage device are operably inter
`connected to a storage server. The storage server is operable
`to cause data to be provided to each of the ?rst and second
`data storage devices. The storage server may comprise an
`operating system, a CPU, and a disk I/O controller. The
`storage server, in an embodiment, (a) receives block data to
`be Written to the ?rst data storage device, the block data
`comprising unique block addresses Within the ?rst data
`storage device and data to be stored at the unique block
`addresses, (b) stores the block data in the second data
`storage device, (c) manipulates the block data, based on the
`unique block addresses, to enhance the efficiency of the ?rst
`data storage device When the ?rst data storage device stores
`the block data to the ?rst data storage device memory, and
`(d) issues one or more Write commands to the ?rst data
`storage device to Write the block data to the ?rst data storage
`device memory. Manipulating the block data may include
`reordering the block data based on the unique block
`addresses such that seek time Within the ?rst data storage
`device is reduced.
`
`[0012] Another embodiment of the invention provides a
`method for storing data in a data storage system. The method
`comprising: (a) providing a ?rst data storage device com
`prising a ?rst memory for holding data; (b) providing a
`second data storage device comprising a second volatile
`memory and a second non-volatile memory; (c) storing data
`to be stored at the ?rst data storage device at the second data
`storage device in the second volatile memory; and (d)
`moving the data from the second volatile memory to the
`second non-volatile memory in the event of a poWer inter
`ruption. The ?rst data storage device may comprise at least
`one hard disk drive having a volatile Write-back cache and
`a storage media capable storing the data. The ?rst data
`storage device, upon receiving data to be stored on the
`storage media, stores the data in the volatile Write-back
`cache and generates an indication that the data has been
`stored at the ?rst data storage device before storing the data
`on the media.
`
`[0013] In one embodiment, the second data storage device
`further comprises a secondary poWer source. The secondary
`poWer source may comprise a capacitor, a battery, or other
`suitable poWer source. In this embodiment, the moving step
`comprises: (a) sWitching the second memory device to the
`secondary poWer source; (b) reading the data from the
`second data storage device volatile memory; and (c) Writing
`the data to the second data storage device non-volatile
`
`memory. In another embodiment, the moving step further
`comprises: (d) sWitching the second memory device oif
`folloWing the Writing step. The moving step comprises, in
`another embodiment: (a) detecting a poWer interruption; (b)
`reading the data from the second data storage device volatile
`memory; (c) computing an ECC for the data; and (d) Writing
`the data and ECC to the second data storage device non
`volatile memory.
`
`[0014] In another embodiment, the moving step com
`prises: (a) detecting a poWer interruption; (b) reading the
`data from the second data storage device volatile memory;
`(c) Writing the data to the second data storage device
`non-volatile memory; and (d) verifying that the data stored
`in the second data storage device non-volatile memory is
`correct. The verifying step comprises, in an embodiment: (i)
`comparing the data from the second data storage device
`non-volatile memory With the data from the second data
`storage device volatile memory; and (ii) re-Writing the data
`to the second data storage device non-volatile memory When
`the comparing step indicates that the data is not the same.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0015] FIG. 1 is a block diagram illustration of a netWork
`having applications and netWork attached storage;
`
`[0016] FIG. 2 is a block diagram illustration of a data
`storage system of an embodiment of the present invention;
`
`[0017] FIG. 3 is a block diagram illustration of a data
`storage system of another embodiment of the present inven
`tion;
`[0018] FIG. 4 is a block diagram illustration of a backup
`device of an embodiment of the present invention;
`
`[0019] FIG. 5 is a block diagram illustration of a PCI
`backup device of an embodiment of the present invention;
`
`[0020] FIG. 6 is a How chart diagram illustrating the
`operational steps performed by a storage controller of an
`embodiment of the present invention;
`
`[0021] FIG. 7 is a How chart diagram illustrating the
`operational steps performed by a backup device processor
`folloWing the poWer on of the backup device of an embodi
`ment of the present invention;
`
`[0022] FIG. 8 is a How chart diagram illustrating the
`operational steps performed by a backup device processor
`folloWing a reset of the backup device of an embodiment of
`the present invention;
`[0023] FIG. 9 is a How chart diagram illustrating the
`operational steps performed by a backup device processor
`When receiving commands, for an embodiment of the
`present invention;
`[0024] FIG. 10 is a How chart diagram illustrating the
`operational steps performed by a backup device processor
`When transferring data from host memory to SDRAM, for an
`embodiment of the present invention;
`[0025] FIG. 11 is a How chart diagram illustrating the
`operational steps performed by a backup device processor
`When transferring data from SDRAM to host memory, for an
`embodiment of the present invention;
`[0026] FIG. 12 is a How chart diagram illustrating the
`operational steps performed by a backup device processor
`
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`Apr. 13, 2006
`
`When transferring data from SDRAM to NVRAM, for an
`embodiment of the present invention;
`[0027] FIG. 13 is a How chart diagram illustrating the
`operational steps performed by a backup device processor
`When transferring data from NVRAM to SDRAM, for an
`embodiment of the present invention; and
`[0028] FIG. 14 is a How chart diagram illustrating the
`operational steps performed by a backup device processor
`When a poWer failure is detected, for an embodiment of the
`present invention.
`DETAILED DESCRIPTION
`[0029] Referring to FIG. 1, a block diagram illustration of
`a computing netWork and associated devices, of an embodi
`ment of the present invention. In this embodiment, a net
`Work 100 has various connections to applications 104 and
`netWork attached storage (NAS) devices 108. The netWork
`100, as Will be understood, may be any computing netWork
`utiliZed for communications betWeen attached netWork
`devices, and may include, for example, a distributed net
`Work, a local area netWork, and a Wide area netWork, to
`name but a feW. The applications 104 may be any of a
`number of computing applications connected to the netWork,
`and may include, for example, a database application, an
`email server application, an enterprise resource planning
`application, a personal computer, and a netWork server
`application, to name but a feW. The NAS devices 108 are
`utiliZed in this embodiment for storage of data provided by
`the applications 104. Such network attached storage is
`utiliZed to store data from one application, and make the data
`available to the same application, or another application.
`Furthermore, such NAS devices 108 may provide a rela
`tively large amount of data storage, and also provide data
`storage that may be backed up, mirrored, or otherWise
`secured such that loss of data is unlikely. UtiliZing such NAS
`devices 108 can reduce the requirements of individual
`applications requiring such measures to prevent data loss,
`and by storing data at one or more NAS devices 108, data
`may be securely retained With a reduced cost for the appli
`cations 104. Furthermore, such NAS devices 108 may
`provide increased performance relative to, for example,
`local storage of data. This improved performance may result
`from relatively high speed at Which the NAS devices 108
`may store data.
`[0030] A key performance measurement of NAS devices
`108 is the rate at Which data may be Written to the devices
`and the rate at Which data may be read from the devices. In
`one embodiment, the NAS devices 108 of the present
`invention receive data from applications 104, and acknoWl
`edge back to the application 104 that the data is securely
`stored at the NAS device 108, before the data is actually
`stored on storage media located Within the NAS 108. In this
`embodiment, the performance of the NAS is increased,
`because there is no requirement for the NAS device to Wait
`for the data to be stored at storage media. For example, one
`or more hard disk drives may be utiliZed in the NAS 108,
`With the NAS reporting to the application 104 that a data
`Write is complete before the data is stored on storage media
`Within the hard disk drive(s). In order to provide security to
`the data before it is stored on storage media, the NAS
`devices 108, of this embodiment, store the data in a non
`volatile memory, such that if a poWer failure, or other failure,
`occurs prior to Writing the data to the storage media, the data
`may still be recovered.
`
`[0031] Referring noW to FIG. 2, a block diagram illustra
`tion of a NAS device 108 of an embodiment of the present
`invention is noW described. In this embodiment, the NAS
`108 includes a netWork interface 112, Which provides an
`appropriate physical connection to the netWork and operates
`as an interface betWeen the netWork 100 and the NAS device
`108. The netWork interface 112 may provide any available
`physical connection to the netWork 100, including optical
`?ber, coaxial cable, and tWisted pair, to name but a feW. The
`netWork interface 112 may also operate to send and receive
`data over the netWork 100 using any of a number of
`transmission protocols, such as, for example, iSCSI and
`Fibre Channel. The NAS 108 includes an operating system
`120, With an associated memory 124. The operating system
`120 controls operations for the NAS device 108, including
`the communications over the netWork interface 112. The
`NAS device 108 includes a data communication bus 128
`that, in one embodiment, is a PCI bus. The NAS device 108
`also includes a storage controller 132 that is coupled to the
`bus 128. The storage controller 132, in this embodiment,
`controls the operations for the storage and retrieval of data
`stored at the data storage components of the NAS device
`108. The NAS device 108 includes one or more storage
`devices 140, Which are utiliZed to store data. In one embodi
`ment, the storage devices 140 include a number of hard disk
`drives. It Will be understood that the storage device(s) 140
`could be any type of data storage device, including storage
`devices that store data on storage media, such as magnetic
`media, tape media, and optical media. The storage devices
`may also include solid-state storage devices that store data
`in electronic components Within the storage device. In one
`embodiment, as mentioned, the storage device(s) 140 com
`prise a number of hard disk drives. In another embodiment,
`the storage device(s) 140 comprise a number of hard disk
`drives con?gured in a RAID con?guration. The NAS device
`108 also includes one or more backup devices 144 con
`nected to the bus 128. In the embodiment of FIG. 2, the
`NAS device 108 includes one backup device 144, having a
`non-volatile memory, in Which the storage controller 132
`causes a copy of data to be stored at storage devices 140 to
`be provided to the backup device 144 in order to help
`prevent data loss in the event of a poWer interruption or other
`failure Within the NAS device 108. In other embodiments,
`more than one backup device 144 may be utiliZed in the
`NAS device 108.
`
`[0032] Referring noW to FIG. 3, a storage controller 132,
`storage device 140, and backup memory 144 of an embodi
`ment are described in more detail. In this embodiment, the
`storage device 140 is a hard disk drive having an enabled
`Write-back cache 148. It Will be understood that the storage
`device 140 may comprise a number of hard disk drives,
`and/or one or more other storage devices, and that the
`embodiment of FIG. 3 is described With a single hard disk
`drive for the purposes of discussion and illustration only.
`The principles and concepts as described With respect to
`FIG. 3 fully apply to other systems having more or other
`types of storage devices. As mentioned, the storage device
`140 includes an enabled Write-back cache 148. A Write-back
`cache 140 is utiliZed in this embodiment to store data Written
`to the storage device 140 before the data is actually Written
`to the media Within the storage device 140. When the data
`is stored in the Write-back cache 148, the storage device 140
`acknoWledges that the data has been stored. By utiliZing the
`Write-back cache 148, the storage device 140 in most cases
`
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`Apr. 13, 2006
`
`has signi?cantly improved performance relative to the per
`formance of a storage device that does not have an enabled
`Write-back cache.
`
`[0033] As is understood, storage devices may utilize a
`Write-back cache to enhance performance by reducing the
`time related to the latency Within the storage device. For
`example, in a hard disk drive, prior to Writing data to the
`storage media, the drive must ?rst position the read/Write
`head at the physical location on the media Where the data is
`to be stored, referred to as a seek. Seek operations move an
`actuator arm having the read/Write head located thereon to a
`target data track on the media. Once the read/Write head is
`positioned at the proper track, it then Waits for the particular
`portion of the media Where the data is to be stored to rotate
`into position Where data may then be read or Written. The
`time required to position the actuator arm and Wait for the
`media to move into the location Where data may be read or
`Written depends upon a number of factors, and is largely
`dependent upon the location of the actuator arm prior to
`moving it to the target track. In order to reduce seek times
`for Write operations, a disk drive may evaluate data stored in
`the Write-back cache 148, and select data to be Written Which
`requires a reduced seek time compared to other data in the
`Write-back cache, taking into consideration the current loca
`tion of the read/Write head on the storage media. The data
`Within the Write-back cache may thus be Written to the media
`in a different order than received, in order to reduce this seek
`time and enhance the performance of the storage device.
`
`[0034] A disad