(12) United States Patent
`Li et al.
`
`US006336174B1
`US 6,336,174 B1
`Jan. 1, 2002
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`(54)
`
`HARDWARE ASSISTED MEMORY BACKUP
`SYSTEM AND METHOD
`
`(75) Inventors: Qiang Li, Campbell; Cli?'ord E.
`Strang, J r.; Jon F. Zahornacky, both
`of San Jose, all of CA (US)
`
`(73) Assignee: Maxtor Corporation, Longmont, CO
`(Us)
`
`(*)
`
`Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21)
`(22)
`(51)
`(52)
`
`(58)
`
`(56)
`
`Appl. No.: 09/370,855
`Filed:
`Aug. 9, 1999
`
`Int. Cl.7 .............................................. .. G06F 12/00
`US. Cl. ......................... .. 711/162; 711/161; 714/6;
`365/228
`Field of Search ............................... .. 711/162, 160,
`711/161; 714/6—22; 710/10; 713/340; 370/537;
`365/228, 229
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`4,072,852 A *
`4,815,074 A
`4,959,774 A
`5,283,792 A
`5,379,431 A
`5,799,200 A
`
`*****
`
`2/1978
`3/1989
`9/1990
`2/1994
`1/1995
`8/1998
`
`Hogan et al. ............... .. 714/15
`
`Jacobsen .... ..
`
`370/537
`
`Davis ....................... .. 714/6
`
`Davies, Jr. et al. ......... .. 714/22
`Lemon et al. .............. .. 710/10
`
`Brant et al. ............... .. 713/340
`
`OTHER PUBLICATIONS
`
`nvSRAM Basics, Simtek 1999 Data Book, Chapter 8, pp.
`8—1 to 8—5.
`
`Primary Examiner—Do Hyun Yoo
`Assistant Examiner—Nasser MoaZZami
`(74) Attorney, Agent, or Firm—David M. Sigmond
`
`(57)
`
`ABSTRACT
`
`AhardWare assisted memory module (HAMM) is coupled to
`a conventional computer system. During normal operation
`of the computer system, the HAMM behaves like a conven
`tional memory module. The HAMM, hoWever, detects and
`responds to at least one of the following trigger events: 1)
`poWer failure, 2) operating system hang-up, or 3) unex
`pected system reset. Upon detection of a trigger event, the
`HAMM electronically isolates itself from the host computer
`system before copying digital information from volatile
`memory to nonvolatile memory. Once isolated, the HAMM
`takes its poWer from an auxiliary poWer supply. The HAMM
`can be con?gured to copy all or part of the digital informa
`tion to nonvolatile memory. Upon either a request or at
`poWer-up, the HAMM copies the digital information from
`the nonvolatile memory into the volatile memory. If there is
`a normal computer shutdoWn, the operating system Will ?rst
`Warn the HAMM before shutting doWn, thus precluding it
`from performing a backup operation. The operating system
`determines Whether the last shutdoWn Was unexpected by
`reading a register stored in a reserved area of memory. If the
`operating system Wants the digital information restored, it
`orders the HAMM to restore the backed-up digital informa
`tion from nonvolatile memory to volatile memory.
`
`* cited by examiner
`
`80 Claims, 5 Drawing Sheets
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`US. Patent
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`Jan.1,2002
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`U.S. Patent
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`Jan. 1, 2002
`
`Sheet 3 0f 5
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`US 6,336,174 B1
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`LOCAL POWER ON w 330
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`
`FIGURE 3
`
`

`

`U.S. Patent
`
`Jan. 1, 2002
`
`Sheet 4 0f 5
`
`US 6,336,174 B1
`
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`FIGURE 4
`
`

`

`U.S. Patent
`
`Jan. 1, 2002
`
`Sheet 5 0f 5
`
`US 6,336,174 B1
`
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`FIGURE 5
`
`

`

`US 6,336,174 B1
`
`1
`HARDWARE ASSISTED MEMORY BACKUP
`SYSTEM AND METHOD
`
`FIELD OF THE INVENTION
`
`The invention relates to memory backup and restoration
`of digital information, and more particularly, to a hardWare
`assisted memory backup system and method using nonvola
`tile memory.
`
`BACKGROUND OF THE INVENTION
`
`10
`
`The need for emerging ?le server technology With multi
`protocol ?le system semantics has created unique problems
`in data management for ?le service operations, such as
`saving data to disk storage in real-time and reliably. These
`problems are further exacerbated by the potential of cata
`strophic system failures, such as operating system (O/S)
`hang-up, and/or unexpected poWer failures and system
`resets. For some applications, the loss of certain types of
`data may not pose any serious problems. For client/server
`applications, hoWever, if the system loses “meta” data, i.e.,
`information concerning a system’s ?le structure, the ?le
`structure Will be dif?cult, if not impossible, to reconstruct.
`In a typical client/server application, a client computer
`can request a server computer to store ?le system data to a
`permanent storage device, such as a hard disk. Because a
`typical Write transaction can take several operations to
`complete, the client data is temporarily stored in server
`memory until the Write transaction is successfully com
`pleted. Once the data is safely stored to disk, the server
`computer can inform the client computer that the Write
`transaction Was completed. This entire store transaction can
`take as long as 20 milliseconds, Which is a long delay for the
`client.
`Unfortunately, if a catastrophic event occurs While all or
`some of the data is still in system memory, data loss can
`occur. Data loss occurs because the server system memory
`typically is volatile memory, such as Dynamic Random
`Access Memory (DRAM) or Static Random Access
`Memory (SRAM). For example, DRAM employs a system
`of transistors and capacitors to retain data. Because the
`capacitors cannot maintain an electrical charge inde?nitely,
`the capacitors must be continuously refreshed by a poWer
`supply. Thus, backing-up data stored in DRAM in the event
`of a poWer failure presents the additional problem of refresh
`ing DRAM until all data has been safely transferred to
`nonvolatile memory.
`Some conventional systems automatically transfer data
`from volatile memory (e.g., SRAM) to nonvolatile memory
`(e.g., Electrical Erasable Programmable Read-only Memory
`(EEPROM)), if the chip poWer drops beloW a ?rst prede
`termined voltage (e.g., 4.2 volts from 5 volts). If the chip
`poWer drops beloW the ?rst predetermined voltage, a store
`operation is started that continues until the chip poWer drops
`beloW a second predetermined voltage (e.g., 3.5 volts), after
`Which time the integrity of the data being transferred from
`volatile memory becomes uncertain. Thus, the store opera
`tion must complete before the chip poWer drops beloW the
`second predetermined voltage.
`The conventional systems described above provide a
`solution for systems requiring a limited amount of data
`transfer, such as 32K. Unfortunately, the amount of data that
`can be safely transferred by these systems is limited by the
`?nite interval of time Where the chip poWer is suf?ciently
`high to ensure a successful data transfer. Unfortunately, for
`systems requiring a larger data transfer, such as 8 Mb or
`more, these conventional systems do not provide a solution.
`
`15
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`2
`Moreover, these systems typically cannot operate With
`DRAM because they do not provide a refresh engine that can
`operate during poWer failure events. As discussed above, a
`refresh engine, or its equivalent, is necessary in DRAM
`based systems to maintain data stored in volatile memory
`While such data is being backed-up to nonvolatile memory.
`An additional problem With some conventional systems is
`their inability to provide memory backup in response to
`events other than poWer failure events, such as unexpected
`system resets or O/S hang-up. The conventional systems are
`unable to differentiate betWeen normal system shutdoWns
`and unexpected system shutdoWns initiated by, for example,
`a user pressing a hardWare reset button. The inability to
`differentiate betWeen normal and unexpected system shut
`doWns can decrease the life of the nonvolatile memory
`employed in such systems because of the ?nite number of
`Write cycles available in such memories. The ability to
`prolong the “Write” life of nonvolatile memory is important
`When one considers that a typical EEPROM cell or ?ash
`memory cell can break doWn after a ?nite number of Write
`cycles.
`Still another problem With conventional systems and
`methods is hoW such systems and methods store O/S kernel
`code for rebooting the system after a catastrophic failure. In
`conventional embedded systems, O/S kernel code is usually
`stored in specialiZed nonvolatile memory, Which requires
`additional memory mapping, and modi?cation of BIOS to
`load and initialiZe the kernel. Storing O/S kernel code in
`specialiZed nonvolatile memory typically increases the num
`ber of system components, increases BIOS development and
`maintenance efforts, and reduces system boot speed.
`Accordingly, there remains a need for a memory backup
`system and method that copies digital information from
`volatile memory to nonvolatile memory in response to
`catastrophic events, such as O/S hang-up and unexpected
`poWer failures and system resets. The system and method
`should be able to quickly copy a relatively large amount of
`information (e.g., 8 Mb or greater) from volatile memory
`(e.g., DRAM) to nonvolatile memory Without corrupting the
`integrity of the information. Moreover, the system and
`method should be able to differentiate betWeen normal
`system shutdoWn events and unexpected shutdoWn events to
`preserve the “Write” life of the nonvolatile memory. The
`system and method should also use conventional memory
`chip formats and packaging, such as Dual In-line Memory
`Module (DIMM) or Single In-line Memory Module
`(SIMM). These conventional package formats can enable
`the system to easily couple With the system memory bus of
`a conventional computer system, such as a Personal Com
`puter (PC).
`Additionally, there is a need for storing O/S kernel code
`into main system memory to reduce the number of system
`components, reduce BIOS development and maintenance
`efforts, and improve system boot speed.
`
`SUMMARY OF THE INVENTION
`
`The present invention is directed to a hardWare assisted
`memory module (HAMM) for communicating digital infor
`mation betWeen volatile and nonvolatile memory in
`response to a trigger event from, for example, a host
`computer system. The HAMM generally includes a volatile
`memory coupled to an information source for receiving and
`storing information; a nonvolatile memory coupled to the
`volatile memory for receiving and storing information com
`municated from the volatile memory; and a controller
`coupled to the memories for controlling the communication
`
`

`

`US 6,336,174 B1
`
`1O
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`15
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`35
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`
`3
`of information between the memories in response to the
`trigger event. The controller can determine the type of the
`trigger event from, for example, control information stored
`in the volatile memory.
`In a preferred embodiment of the present invention, the
`HAMM is coupled to a host computer system, such as a PC.
`During normal operation of the computer system, the
`HAMM behaves like a conventional memory module, for
`example, storing digital information received from a data
`bus. The HAMM, hoWever, detects and responds With a
`memory backup operation to at least one of the folloWing
`events: 1) unexpected poWer failure, 2) operating system
`hang-up, or 3) unexpected system reset. Upon detection of
`an event, the HAMM electronically isolates itself from the
`host computer system before copying the digital information
`from volatile memory to nonvolatile memory. Once isolated
`the HAMM takes its poWer from an auxiliary poWer supply,
`such as a battery.
`The HAMM can be con?gured to copy all or part of the
`digital information to nonvolatile memory. Upon either a
`request or at poWer-up, the HAMM copies the digital
`information from nonvolatile memory into volatile memory.
`If there is a normal or expected computer shutdoWn, the O/S
`Warns the HAMM before shutting doWn the host computer
`system, thereby precluding the HAMM from performing the
`memory backup operation. The O/S determines Whether the
`previous shutdoWn, if any, Was unexpected by reading a
`control register in a reserved area of volatile memory,
`preferably outside the memory map of the volatile memory.
`If the O/S Wants the ?le information restored, it orders the
`HAMM to restore the backed-up ?le information from
`nonvolatile memory to volatile memory.
`The present invention is also directed to a memory backup
`system. The system is coupled to a host computer system for
`providing memory backup in response to a trigger event.
`The system includes a volatile memory coupled to an
`information source for receiving and storing information; a
`nonvolatile memory coupled to the volatile memory for
`receiving and storing information communicated from the
`volatile memory; and a controller coupled to the memories
`for controlling the communication of information betWeen
`the memories in response to the trigger event. The controller
`determines the type of the trigger event from control infor
`mation stored in the volatile memory.
`The present invention is also directed to a memory backup
`method. The method includes the steps of: detecting a
`trigger event from a host computer system; determining if
`the trigger event is an unexpected host computer system
`failure or a normal host computer system shutdoWn by
`examining a data structure in volatile memory; copying
`digital information from volatile memory to nonvolatile
`memory only if the type of the trigger event is an unexpected
`host computer system failure; and storing control informa
`tion relating to the type of the trigger event in volatile
`memory.
`An advantage of the present invention can be best realiZed
`in a client/server application, Where memory access time is
`reduced during Write transactions. Because the HAMM
`provides assurance that data Will be backed-up in the event
`of a catastrophic failure, a ?le server system can complete a
`transaction With a client even though all or part of the data
`to be transferred is still in volatile memory in the ?le server
`system. By completing the Write transaction early, the over
`all transaction time is reduced. This time savings, multiplied
`by the number of Write transactions that take place in a
`typical client/server application, can be signi?cant.
`
`55
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`
`4
`Another advantage of the present invention described
`above, is the ability of the HAMM to copy large amounts of
`data (e.g., 8 Mb or larger) from volatile memory to non
`volatile memory. By using an auxiliary poWer supply, the
`volatile memory can be safely maintained until the data is
`copied. By contrast, some conventional systems must copy
`the data Within the time interval just before the chip poWer
`drops beloW a predetermined voltage. Thus, these conven
`tional systems can transfer only small amounts of data (e.g.,
`32K).
`An advantage of using the auxiliary poWer supply as
`described above, is the ability to use different types of
`volatile memory, particularly memory that requires refresh,
`such as DRAM. The auxiliary poWer supply can be used to
`refresh the DRAM While data is being copied during unex
`pected system poWer failure.
`An advantage of using isolation devices as described
`above, is the ability to isolate the HAMM from the host
`system’s poWer supply during control operations to prevent
`spurious events (e.g., poWer spikes, short circuits) from
`corrupting the data While performing control operations.
`Another advantage of the present invention is the added
`?exibility of responding to multiple triggering events, rather
`than just system poWer failures. This advantage is important
`because other events, such as O/S hang-up and unexpected
`system resets, can also cause data loss. Conventional sys
`tems that protect only against system poWer failures do no
`provide adequate data protection for many applications.
`Still another advantage of the present invention is the
`ability to permanently store a pre-initialiZed O/S kernel
`image in nonvolatile memory, and to quickly copy it into
`system memory using control logic disposed in the HAMM.
`From an O/S point of vieW, this is equivalent to permanently
`storing an O/S kernel in volatile system memory. Most
`conventional systems cannot provide this function cost
`effectively. Thus, the present invention provides an impor
`tant advantage over conventional embedded systems, and
`thin ?le systems in particular, by simplifying both the
`hardWare and softWare used to store and retrieve the O/S
`kernel code, thereby increasing system boot speed.
`BRIEF DESCRIPTION OF THE DRAWINGS
`The present invention has other advantages and features
`Which Will be more readily apparent from the folloWing
`detailed description of the invention and the appended
`claims, When taken in conjunction With the accompanying
`draWings, in Which:
`FIG. 1 is a functional block diagram of one embodiment
`of a ?le server system 100 in accordance With the present
`invention;
`FIG. 2 is a functional block diagram of one embodiment
`of a hardWare assisted memory module in accordance With
`the present invention;
`FIG. 3 is a How diagram of one embodiment of control
`logic illustrating event detection and store operations pro
`vided by the hardWare assisted memory module in accor
`dance With the present invention;
`FIG. 4 is a How diagram of one embodiment of control
`logic illustrating restore operations provided by the hard
`Ware assisted memory module in accordance With the
`present invention; and
`FIG. 5 is a functional block diagram of one embodiment
`of the controller in FIG. 2 for executing the control logic in
`FIGS. 3 and 4.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`While the present invention is described With reference to
`a client/server application, other applications may be used
`
`

`

`US 6,336,174 B1
`
`5
`With the present invention Without departing from the spirit
`and scope of the present invention, for example, database
`engines, peer-to-peer networks, netWorks that employ dis
`tributed ?le systems, and standalone computers. The term
`“data,” as used herein, includes all forms of digital infor
`mation including ?le system data, otherWise knoWn as
`“meta” data. Generally, the present invention is applicable to
`any applications that can bene?t from staging data in high
`speed memory While maintaining data integrity upon system
`failure.
`Referring to FIG. 1, there is shoWn a functional block
`diagram of one embodiment of ?le server system 100
`(hereinafter also referred to as “host system 100”) in accor
`dance With the present invention. Host system 100 prefer
`ably includes a CPU 102, a hardWare assisted memory
`module 104 (hereinafter also referred to as “HAMM 104”),
`a disk controller 106, a netWork interface 108, a system
`memory bus 110, an I/O bus 112, disk storage 114, and
`conventional memory 116. Host system 100 can be, for
`example, a conventional PC con?gured as a ?le server or,
`alternatively, a thin ?le server, such as the Plug & StorTM 100
`Thin Server, developed by Creative Design Solutions, Inc.,
`Santa Clara, Calif.
`CPU 102 can be a conventional computer processor, for
`example, a PentiumTM processor manufactured by Intel
`Corporation, Santa Clara, Calif. CPU 102 is coupled to
`system memory bus 110, Which can be a conventional
`computer bus. System memory bus 110 is further coupled to
`I/O bus 112, Which can be, for example, a Peripheral
`Component Interconnect (PCI) bus. The U0 bus 112 is
`coupled to netWork interface 108, Which can be a conven
`tional netWork interface (e.g., Ethernet) for providing
`bi-directional communication betWeen host system 100 and
`one or more client computers. Coupled to I/ O bus 112 is disk
`controller 106 for controlling the reading and Writing of data
`to disk storage 114. Disk controller 106 can be a conven
`tional hard disk controller, such as a Small Computer System
`Interface (SCSI) disk controller. Disk storage 114 is coupled
`to system memory bus 110 via disk controller 106. Disk
`storage 114 can be any conventional storage device used to
`store digital information, including, for example, hard disks
`and optical disk. Also shoWn in FIG. 1 is conventional
`memory 116, Which is coupled to the system memory bus
`110.
`The HAMM 104 is a preferred embodiment of the present
`invention. The HAMM 104 is coupled to system memory
`bus 110 using conventional memory module formats, pin
`outs, and/or packaging, for example, DIMM or SIMM.
`Preferably, the HAMM 104 replaces or supplements one or
`more conventional memory modules, and includes both
`volatile memory and nonvolatile memory. Multiple
`HAMMs can be coupled together as required by the system.
`The HAMM 104 is described in further detail beloW With
`respect to FIG. 2.
`In accordance With the operation of host system 100, a
`client computer (not shoWn) communicates With host system
`100 via netWork interface 108. Depending on the commu
`nication protocol (e.g., TCP/IP), if a client computer Wants
`to store data in disk storage 114, the client computer sends
`a “Write” request to host system 100. Upon acceptance of the
`client’s “Write” request, host system 100 receives data over
`the netWork and stores the data in volatile memory. Once the
`data is in volatile memory, host system 100 signals back to
`the client computer that the “Write” transaction has been
`completed. The data remains stored in volatile memory until
`it can be safely stored to disk storage 114 via disk controller
`106. If a catastrophic event occurs While all or some of the
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`data is still in volatile memory, the HAMM 104 copies all or
`some of the data to nonvolatile memory to prevent data loss,
`as described beloW With respect to FIG. 2.
`An advantage of the present invention is that completion
`of a “Write” transaction occurs While data is still in volatile
`memory, rather than Waiting for the data to be actually stored
`to disk. By signaling to the client that the “Write” transaction
`has completed even When data is still in volatile memory, the
`Write transaction time can be signi?cantly reduced. This
`advantage is made possible by the HAMM 104, Which
`assures that data in volatile memory is safely copied to
`nonvolatile memory.
`Referring to FIG. 2, there is shoWn a functional block
`diagram of one embodiment of the HAMM 104 in FIG. 1 in
`accordance With the present invention. The HAMM 104
`preferably includes volatile memory 202, nonvolatile
`memory 204, controller 206, isolation devices 208, and
`reserved memory 210. In a preferred embodiment, the
`volatile memory 202 is DRAM and the nonvolatile memory
`204 is ?ash memory. Flash memory is integrated circuit
`memory that does not need continuous poWer to retain
`stored data. It has a limited life span of, for example,
`100,000 Write cycles. Typical ?ash memory is erased in
`blocks of data rather than single bytes of data, thus reducing
`the erase and Write cycle times necessary to store data in
`such memories. Flash has relatively loW cost and can be
`con?gured to have a fairly large siZe.
`The amount of volatile memory 202 and nonvolatile
`memory 204 required can vary based on the needs of the
`host system 100. In one embodiment, the ratio of volatile
`memory 202 to nonvolatile memory 204 can be 2:1. For
`example, the HAMM 104 can include 8 Mb><8 DRAM and
`4 Mb><8 ?ash memory, thus establishing a 2:1 ratio betWeen
`DRAM and ?ash memory. Thus, in this example only half
`of the data in DRAM can be copied to ?ash memory.
`It is noted that the present invention is not limited to
`DRAM or ?ash memory, and other types of memory can be
`used Without departing from the spirit or scope of the present
`invention. For example, volatile memory 202 can include
`SRAM, Fast Page Mode DRAM (FPM DRAM), Extended
`Data Out DRAM (EDO), Synchronous DRAM (SDRAM),
`Double-data Rate SDRAM (DDR SDRAM), Direct Ram
`busTM DRAM (RDRAM), SyncLinkTM DRAM (SLDRAM),
`Video RAM (VRAM), and WindoW RAM (WRAM).
`Additionally, nonvolatile memory 204 can include
`EEPROM, ?ash memory, and solid state disk.
`Volatile memory 202 is coupled to system memory bus
`110 (FIG. 1) through data bus 212 and address/control bus
`216 via isolation devices 208. The isolation devices 208 can
`be transistors con?gured as on/off sWitches using conven
`tional Complimentary Metal-oxide Semiconductor (CMOS)
`technology. The isolation devices 208 electrically isolate the
`HAMM 104 from the host system 100 in response to certain
`trigger events. This alloWs the HAMM 104 to run indepen
`dent of the host system 100 after a catastrophic failure, even
`if the poWer to the host system 100 is lost.
`Controller 206 is coupled to volatile memory 202 via
`address/control bus 216 and data bus 212. Controller 206 is
`also coupled to nonvolatile memory 204 via data bus 212
`and address/control bus 217. Buses 216, 217 include both
`address and control signals for addressing and controlling
`volatile and nonvolatile memories 202, 204, respectively.
`Generally, controller 206 includes control logic, a clock, a
`poWer interface (e.g., battery interface), and a timing device.
`The control logic is for generating the address and control
`signals on buses 216, 217 for accessing volatile memory 202
`
`

`

`US 6,336,174 B1
`
`7
`and nonvolatile memory 204. The clock (e.g., a crystal
`oscillator), is used to time various control operations. The
`poWer interface provides a connection to the auxiliary poWer
`source, such as a battery. The interface can include conven
`tional circuitry for recharging a battery. The timing device is,
`for example, a Watchdog timer, for triggering operating
`system hang-up. Apreferred embodiment of controller 206
`is described in further detail beloW With respect to FIG. 5.
`Controller 206 manages control operations for the
`HAMM 104 Which include store and restore operations. The
`store operation copies data from volatile memory 202 to
`nonvolatile memory 204. The restore operation copies data
`from nonvolatile memory 204 to volatile memory 202. The
`store operation is only performed if there is catastrophic
`failure to preserve the life span of nonvolatile memory 202,
`for example, ?ash memory, Which may have a ?nite Write
`life of about, for example, 100,000 Write cycles.
`In a preferred embodiment of HAMM 104, a block of
`reserved memory 210 contains a control register 209 that is
`monitored by controller 206. The O/S communicates With
`controller 206 by Writing to control register 209. For
`example, the O/S can reset the Watchdog timer and inform
`the HAMM 104 of the status of a host system 100 shutdoWn
`by setting one or more bits in control register 209. To ensure
`that reserved memory 210 remains exclusive to communi
`cations betWeen the O/S and controller 206, an access
`sequence can be employed that prevents accidental access to
`reserved memory 210. Thus, if a softWare application steps
`into the address range of reserved memory 210, the prob
`ability of falsely triggering a control operation is virtually
`Zero. The programming of controller 206 Will determine the
`address range of reserved memory 210.
`During a store operation, controller 206 generates the
`appropriate addresses on bus 216 to enable the copying of
`data from volatile memory 202 to nonvolatile memory 204
`via data bus 212. The type of addressing scheme employed
`by controller 206 depends on the type of memory used in the
`HAMM 104. For example, DRAM could require a Column
`Access Select (CAS) addressing scheme and ?ash memory
`could require a most signi?cant bit addressing scheme. Both
`addressing schemes are Well-knoWn in the art. In a preferred
`embodiment, controller 206 can interpret non-standard
`addressing/control through bus 216 to enable the host sys
`tem 100 to access reserved memory 210, as described in
`further detail beloW. In the preferred embodiment, controller
`206 copies data from volatile memory 202 to nonvolatile
`memory 204 by controlling the address and control signals
`on buses 216, 217 of volatile memory 202 and nonvolatile
`memory 204, respectively, as shoWn in FIG. 2.
`Store operations are executed by controller 206 for at least
`one of the folloWing trigger events: 1) O/S hang-up, 2)
`unexpected system reset, or 3) unexpected poWer failure.
`Each of these trigger events are described, in turn, beloW. It
`is noted, hoWever, that the present invention is not limited to
`the events described beloW, and other trigger events are
`possible Without departing from the spirit and scope of the
`present invention.
`O/S Hang-up
`A trigger event occurs When the Watchdog timer in the
`HAMM 104 times out. In response to this trigger event,
`controller 206 initiates a store operation to copy all or part
`of the data stored in volatile memory 202 to nonvolatile
`memory 204. In an embodiment that uses DRAM, controller
`206 can also maintain refresh during store and restore
`operations. Preferably, the Watchdog timer is reset by a
`“Write” to one or more bits in control register 209.
`Unexpected System Reset & System PoWer Failure
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`Generally, a poWer failure is “unexpected” if the HAMM
`104 is not foreWarned by the O/S of a normal shutdoWn.
`Controller 206 is coupled to an auxiliary poWer supply, such
`as a battery, Which is used if an unexpected system poWer
`failure occurs. If the system poWer fails, isolation devices
`208 Will turn off and thereby electrically isolate the HAMM
`104 from the host system 100. During this time, the HAMM
`104 receives its poWer from the auxiliary poWer supply,
`Which provides for safe copying of data from volatile
`memory 202 to nonvolatile memory 204. The auxiliary
`poWer supply can also be used to refresh DRAM to maintain
`data While Waiting to be copied. The host system 100 should
`be properly shutdoWn by the O/S before replacing the
`auxiliary poWer supply. This Will ensure that data is properly
`stored in the event of unexpected poWer failure.
`If there is a normal or expected shutdoWn the O/S Will
`Warn the controller 206 so that the controller 206 does not
`perform a store operation after system poWer is terminated.
`Preferably, the O/S Warns the controller 206 of a normal or
`expected shutdoWn by Writing to the control register 209.
`The Warning can be communicated by, for example, setting
`one or more bits to indicate a normal shutdoWn (e.g., setting
`a bit to “0”). The controller 206 can determine Whether the
`last shutdoWn Was in response to a catastrophic failure by
`reading one or more bits in control register 209. Preferably,
`the control register 209 is read by the controller 206 after a
`reset operation is completed by the Basic Input/Output
`System (BIOS), thereby enabling BIOS to run system diag
`nostics. If the O/S Wants the data restored, the O/S Writes to
`one or more bits in control register 209 to order the con
`troller 206 to restore the data stored in nonvolatile memory
`204. Preferably, the restore operation is the revers