US007716411B2
`
`(12) Unlted States Patent
`Panabaker et al.
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 7,716,411 B2
`May 11, 2010
`
`(54) HYBRID MEMORY DEVICE WITH SINGLE
`INTERFACE
`
`(75) Inventors: Ruston Panabaker, Bellevue, WA (U S);
`Jack Crease)" Redmond’ WA (Us)
`.
`.
`.
`(73) Ass1gnee: Mlcrosoft Corporatlon, Redmond, WA
`(Us)
`
`( * ) Notice:
`
`Subject' to any disclaimer,~ the term of this
`patent is extended or adjusted under 35
`U,S,C, 154(b) by 117 days,
`
`(21) Appl. No.: 11/449,435
`
`(22) Filed:
`
`Jun- 71 2006
`
`(65)
`
`Prior Publication Data
`Us 2007/0288683 A1
`Dec. 13, 2007
`
`(51) Int. Cl.
`(2006.01)
`G06F 12/00
`(2006.01)
`G06F 13/00
`(52) us. Cl. ..................... .. 711/101; 710/100; 710/103;
`710/ 105; 710/154
`(58) Field Of Classi?cation Search ............... .. 711/105,
`711/170’ 101’ 103’ 154’ 100
`See application ?le for Complete Search history
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,581,505 A
`6,366,530 B1*
`6,380,581 B1
`6,456,517 B2
`6,496,854 B1
`6,564,285 B1
`6,670,234 B2
`6,804,146 B2
`
`12/1996
`4/2002
`4/2002
`9/2002
`12/2002
`5/2003
`12/2003
`10/2004
`
`Lee
`Sluiter et a1. .............. .. 365/240
`Noble
`Kim et a1.
`Hagersten et a1.
`Mills
`Hsu
`Johnson
`
`6,892,270 B2
`6,928,512 B2
`7,360,022 B2 *
`
`5/2005 Roohparvar
`8/2005 Ayukawa
`4/2008 Tian et a1. ................. .. 711/123
`évmham
`I'UZ
`6/2005 Ayukawa
`2005/0128853 A1
`8/2005 S h
`2005/0182893 A1
`900% Klillbuck
`Zoos/0204091 A1
`2006/0294295 A1* 12/2006 FukuZo ..................... .. 711/105
`
`OTHER PUBLICATIONS
`
`On Using Network RAM as a Non-Volatile Buffer. http://archvlsi.
`ics.forthgr/htmlipapers/TR227/TR.html.
`* Cited by examiner
`
`Primary ExamineriTuan V. Thai
`(74) Attorney, Agent, or FirmiWorkman Nydegger
`
`(57)
`
`ABSTRACT
`
`Described is a technology by Which a memory controller is a
`component of a hybrid memory device having different types
`of memory therein (e.g., SDRAM and ?ash memory), in
`Which the Controller Operates such that the memory device
`has only a single memory interface With respect to voltage
`and access ProtocolS de?ned for one type Of memory- For
`example, the controller alloWs a memory device With a stan
`dard SDRAM interface to provide access to both SDRAM
`and non-volatile memory With the non-volatile memory over
`laid in one or more designated blocks of the volatile memory
`address space (or vice-versa). A command protocol maps
`memory pages to the volatile memory interface address
`space, for example, permitting a single pin compatible multi
`chip package to replace an existing volatile memory device in
`any computing device that Wants to provide non-volatile stor
`age, While only requiring softWare changes to the device to
`access the ?ash.
`
`17 Claims, 10 Drawing Sheets
`
`Addressable
`Range
`
`333
`
`Commands.
`
`,;1\~
`‘I’,
`\
`x
`\
`-
`r
`320A \ ITBQISISIS
`it
`“
`
`De lgnaled
`Block (Vl?nduw
`in Flash A)
`
`\
`\
`
`Designmd
`Block (lMndow
`tn Flash 5) I
`
`3205
`
`302 B
`
`,
`_
`Hybnd Chip
`
`\
`
`308B
`r
`
`,
`Controller
`w ,
`Elmer 1
`
`H h
`as
`Block M
`
`H h
`53
`B'uck
`Al
`
`Hash
`5'” M
`
`Flash
`Block E
`
`Flash A
`\
`\_:sosA
`f E \
`
`/ f
`1
`
`\
`
`‘
`
`Flash
`Block 50
`
`\
`
`Flash
`Block E1
`
`Flash
`Block 52
`
`Flash
`Block E3
`
`Flash B
`\ 306B
`
`

`

`US. Patent
`
`May 11, 2010
`
`Sheet 1 0110
`
`US 7,716,411 B2
`
`processor
`
`-.
`
`
`
`-’ "
`
`
`
`I -
`
`
`
`Memory (Including Hybrid)
`
`
`
`, 0
`
`193
`
`_- 192
`
`'7 Display (42.9., with
`touchscreen)
`
`191-11,’
`
`‘I
`
`: Keyboard
`
`Operating
`System
`
`Applications
`
`"
`
`194
`
`19s
`
`domponentstegq -
`, Noti?cation Manager) §
`
`-;
`
`a
`
`__j
`
`Power Supply
`
`_ Audio Generator
`
`199
`
`,
`
`>
`
`.
`
`.
`
`,
`
`LEDYS)
`
`19B
`
`FIG. 1
`
`

`

`US. Patent
`
`May 11, 2010
`
`Sheet 2 0110
`
`US 7,716,411 B2
`
`202
`
`Command/r—
`Control/
`
`Memory Device with De?ned Interface
`
`Lines,
`etc.
`
`'
`
`t
`’—
`______
`
`'2
`
`20:
`’\
`Volatile
`<—> Memory
`
`Adfjress 4
`Llnes
`
`:
`
`i
`
`:
`
`Controller
`
`206
`
`" \
`
`Buffer
`Set "'_’ Nonvolatile
`I
`Memory
`
`I 1
`Data
`
`Lines ‘ '_ 210
`
`FIG. 2
`
`

`

`US. Patent
`
`May 11,2010
`
`Sheet 3 0110
`
`US 7,716,411 B2
`
`3 mtg \ ha 3
`2 \\ 61w 3
`
`r
`
`,se \ )
`\\<
`>\
`\
`\
`
`m m
`F \ \
`
`M H; u 0 1
`
`N, . _
`
`3 HD C \i\\
`0)? mm m Duo 3 D
`M No a 0
`
`e w m M
`
`su k 0
`
`\ 3
`
`Ye S
`
`, M
`
`\ \
`~ _
`
`. ,(Y B B B B B B B B B
`
`PM PM Fb Fm Flo Fm Fb Fb Flo F
`
`mm et r
`do e
`Oa\ m tW M
`
`
`
`3/\lmse\ Brlr % 1 -R\
`
`d I
`
`b \ SM
`
`I | | l I | I‘
`
`II I I l l I I l | l l l I ‘ I I l I I I I ‘I
`
`.0 \ {8W U
`
`Manny‘ 111 1| ff C
`
`ae \ D( P
`
`CD\ 3 MO A 9 \
`II\
`
`d , 11111111.‘.
`
`
`
`A II I I I l I I | \ I I I I | | l I I I | I I I I l II
`
`~ .mvd wow
`
`Firmware
`
`

`

`US. Patent
`
`May 11, 2010
`
`Sheet 4 0110
`
`US 7,716,411 B2
`
`33,
`
`3028
`
`FIG. 3B
`
`Addressable
`Range
`
`,x\\
`Com'mands,
`,I"
`‘~, Data, Status
`r"
`\\ Registers
`:
`320A
`‘\\
`:
`k,
`':
`: Designated
`,
`:Block (Window
`l
`: to Flash A)
`I
`l
`l
`: Designated
`'
`'
`:
`:Block (Window
`:
`{to Flash B) ,
`:
`:
`
`l
`
`3208
`
`l
`
`Address
`
`\\
`~
`
`.
`_
`Hyb?d ChIP
`
`I
`3088 I,
`,’
`I,
`
`Z
`
`I’
`
`Comm er
`u
`3104
`Buffem
`
`—
`
`’
`
`'
`
`'1‘
`,;
`,
`,1
`
`Flash
`Block A_0
`
`Flash
`Block 51
`
`Flash
`Block A.2
`
`Flash
`Block [A
`
`I
`
`I
`
`5
`l :
`:
`l
`:
`1
`i
`:1
`:
`;
`l i
`:
`I 5
`3
`1
`
`Buffer 2
`
`v’~-306A
`
`,-
`
`jf
`j
`
`304
`'
`
`'
`
`389
`/
`/
`CPU CE SDRAM
`1
`
`330
`
`\_
`
`i
`
`Flash
`Block 50
`
`Flash
`Block 51
`
`Flash
`Block gg
`
`Flash
`Block Q
`Hash,
`,_ \
`f 3065
`
`l
`
`V / _/
`Firmware
`
`

`

`US. Patent
`
`May 11,2010
`
`Sheet 5 0f 10
`
`US 7,716,411 B2
`
`FIG. 4
`
`Command
`Address
`(e.g., 1K) "A444
`
`Data Address
`A 442
`(e.g., 1K) 1
`
`332 (FIG. 3A),
`333 (FIG. 3B)
`
`/
`
`Address
`Range
`(e.g., 4M)
`
`

`

`U.S. Patent
`
`May 11,2010
`
`Sheet 6 of 10
`
`US 7,716,411 B2
`
`
`
`..m.$cam:83x2220053080a“x$2x89.
`
`
`oxcmm3:852:003_>_
`
`>92893.1$223.wmam
`
`In
`
`L5
`U.
`
`:3ch
`
`_>_<mow
`
`.9250
`
`050..
`
`32:80
`
`2680
`
`.1
`
`mxo
`
`v30
`
`uwo
`
`um>>
`
`nw<o
`
`*md‘m
`
`-50
`
`809mg
`
`Sac.
`
`.0663.
`
`.3080
`
`5:200
`
`wmm5u<
`
`:2500
`
`:23
`
`
`1.‘2025053
`cano
`
`
`555mm80106.0..xmmExcmm
`
`95>:23ENG65:00
`
`03:8
`
`2mEEE<
`
`a:
`
`3930II
`zoo958o:
`
`
`
`F<m.o<m425¢.
`
`wow
`
`
`
`
`

`

`U.S. Patent
`
`May 11,2010
`
`Sheet 7 of 10
`
`US 7,716,411 B2
`
`o'
`
`Go
`
`
`
`5553.Sun.
`
`
`
`.0363.0:80I
`
`83005mm
`
`
`
`muoooo:E:_oo
`
`26m
`
`
`
`.oumawmucmEEoo
`
`0GEea
`
`
`Ecowo_>wn__>_<m_owAlum/‘0
`.228I.9:Q. oaoEco
`
`
`5mg“..8.0330ouoo200..k3906
`momoo
`
`sum:0:
`
`I
`
`..:aoF<m.o<mér<.o<
`
`Alvjo
`
`#mo
`
`%m>>
`
`uw<m
`
`

`

`U.S. Patent
`
`May 11,2010
`
`Sheet 8 of 10
`
`US 7,716,411 B2
`
`59:0Ema
`
`59:0Ema
`
`$386.359
`
`Ammmoo<fitmmv
`
` $2968mmwfiu<“a
`
`
`
`
`
`#mo
`
`
`
`#w>>
`
`m1_<
`
`
`
`
`
`liwIAWIIbITIEm
`Nm>mmoouNm>wmoowNm>wmooumu—
`
`5322;LEEm
`
`
`
`
`

`

`US. Patent
`
`May 11,2010
`
`Sheet 9 0110
`
`US 7,716,411 B2
`
`FIG. 8
`
`802
`\ Send Flash
`IDLE Command
`
`1
`804
`\ Send Flash
`Block Address
`
`1
`
`806
`
`Send Flash
`Query Busy
`l
`808
`\ Send Flash
`Query Busy
`
`812
`\ Send Flash
`Read Burst
`
`

`

`US. Patent
`
`May 11,2010
`
`Sheet 10 0110
`
`US 7,716,411 B2
`
`902
`
`FIG. 9
`
`/
`011 RAM [ Flash 1
`[ DRAM
`11
`1
`| DRAM |
`4% [ DRAM
`
`I
`
`Flash ]
`
`Flash
`
`Flash A
`
`[ DRAM
`
`Flash
`
`DIMM
`Package
`
`Controller
`
`1::[DRAM Flash
`[ DRAM ][ Flash
`
`M1 [ DRAM
`
`Flash ]
`g [ DRAM ][ Flash ]
`:' [DRAM
`Flash ]
`
`

`

`US 7,716,411 B2
`
`1
`HYBRID MEMORY DEVICE WITH SINGLE
`INTERFACE
`
`BACKGROUND
`
`Various existing and new computing devices make use of
`high speed, volatile memory (e.g., dynamic random access
`memory, or DRAM) to hold operating instructions and data.
`Such devices include mobile phones, television set-top boxes,
`personal computer memory, and so forth. Increasingly com
`puting devices are also including large amounts of relatively
`inexpensive nonvolatile NAND ?ash memory to store appli
`cations and data.
`HoWever, many existing DRAM-based computer devices
`are designed Without the appropriate bus interfaces to support
`NAND ?ash memory; to support NAND ?ash memory
`requires a costly and lengthy redesign of the device chipset.
`Similarly, most NAND ?ash-based devices cannot simply
`add DRAM. Signi?cant changes to a device’s physical archi
`tecture are required to put ?ash memory into an updated
`model of What Was a DRAM-based device, for example, or
`vice-versa.
`While a combination of volatile and nonvolatile memory
`provides bene?ts in many situations, often the expense of
`redesigning a device chipset is too costly/risky for a vendor,
`Whereby the vendor forgoes neW features and business mod
`els that Would be otherWise enabled by having volatile and
`nonvolatile memory in a device. Further, there is no straight
`forWard Way to use existing architectural models and, for
`example, update an existing DRAM-based device With
`NAND ?ash memory; e. g., an entire circuit board Would need
`to be redesigned and replaced, instead of simply adding
`memory to or changing memory in an existing device (and
`updating softWare as appropriate). Moreover, there is a large
`difference in bus speeds betWeen non-volatile and DRAM
`based memory.
`
`SUMMARY
`
`This Summary is provided to introduce a selection of rep
`resentative concepts in a simpli?ed form that are further
`described beloW in the Detailed Description. This Summary
`is not intended to identify key features or essential features of
`the claimed subject matter, nor is it intended to be used in any
`Way that Would limit the scope of the claimed subject matter.
`Brie?y, various aspects of the subject matter described
`herein are directed toWards a hybrid memory device that
`includes a ?rst type of memory (e.g., volatile DRAM-type
`memory) and an interface corresponding to the ?rst type of
`memory, and a second type of memory (e.g., nonvolatile
`?ash-type memory). The memory device includes a control
`ler that is coupled to the interface, to the ?rst type of memory
`and to the second type of memory. Based on information such
`as commands and/ or memory addresses received at the inter
`face, the controller determines Whether a command such as an
`I/O request (e.g., a read or Write) is directed to the ?rst type of
`memory or to the second type of memory.
`Thus, by receiving commands, addresses and data at a
`controller of the hybrid memory device, different types of
`memory may be accessed by softWare (e.g., device ?rmWare
`or a program) via a single interface de?ned for one type of
`memory. The controller includes logic that determines
`Whether a command/address received on the interface of a
`?rst type of memory is directed to a second type of memory
`associated With the memory device, and if so, outputs signals
`to the second type of memory to communicate at least one
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`command to the second type of memory and/ or to perform at
`least one data input/output (I/O) operation on the second type
`of memory.
`Other advantages may become apparent from the folloW
`ing detailed description When taken in conjunction With the
`draWings.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The present invention is illustrated by Way of example and
`not limited in the accompanying ?gures in Which like refer
`ence numerals indicate similar elements and in Which:
`FIG. 1 shoWs an illustrative example of a computing device
`into Which various aspects of the present invention may be
`incorporated.
`FIG. 2 is a representation of an example hybrid memory
`device including a controller and tWo types of memory that
`are each accessible by a single interface de?ned for one of the
`memory types.
`FIG. 3A is a representation of an example hybrid memory
`device With an SDRAM interface With SDRAM and ?ash
`memory that is accessed via a designated block of memory in
`SDRAM addressable space.
`FIG. 3B is a representation of an example hybrid memory
`device With an SDRAM interface With SDRAM and ?ash
`memory that is accessed via a plurality of designated blocks
`of memory in SDRAM addressable space.
`FIG. 4 is a representation of addressable memory space
`corresponding to a ?rst type of memory With sections used for
`communicating data and commands With a second type of
`memory.
`FIG. 5 is an example representation of one suitable type of
`SDRAM device that may be incorporated into a hybrid
`memory device.
`FIG. 6 is an example representation of a hybrid memory
`device With an SDRAM interface containing an SDRAM
`device such as the device of FIG. 5 and a ?ash device.
`FIG. 7 is an example representation of a timing diagram for
`controlling an SDRAM device and a ?ash device.
`FIG. 8 is a representation of example steps corresponding
`to hoW the controller may output ?ash data to a SDRAM
`device con?gured for burst data output.
`FIG. 9 is a representation of hoW ?ash may be added to a
`dual inline memory module (DIMMM) for adding ?ash to
`DRAM-based (including SDRAM) personal computer
`memory.
`
`DETAILED DESCRIPTION
`
`Exemplary Operating Environment
`FIG. 1 illustrates an example of some suitable functional
`components of a computing device 188, such as may be found
`in a handheld/pocket-siZed/tablet-type personal digital assis
`tant, appliance, mobile phone and so forth, including a pro
`cessor 189, a memory 190, a display 192, and a keyboard 191
`(Which may be a physical or virtual keyboard). The memory
`190 generally includes both volatile memory (e.g., RAM) and
`nonvolatile memory (e.g., ROM, PCMCIA cards, and so
`forth). Further, as described beloW, the exemplary memory
`190 includes a hybrid memory device (corresponding to one
`or more chips) that contains more than one type of memory,
`such as ?ash and DRAM or ?ash and SDRAM (Synchronous
`DRAM), in Which one of types shares the other’s interface.
`An operating system 193 may be resident in the memory 190
`
`

`

`US 7,716,411 B2
`
`3
`and executes on the processor 189, such as a Microsoft®
`WindoWs®-based operating system, or another operating
`system.
`One or more application programs 194 and data 195 may
`be in the memory 190, e. g., With the programs 194 run on the
`operating system 193. Examples of applications include
`email programs, scheduling programs, PIM (personal infor
`mation management) programs, Word processing programs,
`spreadsheet programs, Internet broWser programs, and so
`forth. The computing device 188 may also include other
`components 196 such as a noti?cation manager loaded in the
`memory 190, Which executes on the processor 189. The noti
`?cation manager for example may handle noti?cation
`request, e.g., from the application programs 194.
`The computing device 188 has a poWer supply 197, for
`example implemented as one or more batteries or a light
`poWered system. The poWer supply 197 may further include
`an external poWer source that overrides or recharges the built
`in batteries, such as an AC adapter or a poWered docking
`cradle.
`The exemplary computing device 188 represented in FIG.
`1 is shoWn With three example types of external output
`devices, including the display 192, other output mechanisms
`198 (e.g., one or more light emitting diodes, or LEDs) and an
`audio generator 199, e. g., coupled to integrated speakers and/
`or to an audio jack. One or more of these output devices may
`be directly coupled to the poWer supply 197 so that When
`activated, it remains on for a duration dictated by a noti?ca
`tion mechanism even though the processor 189 and other
`components might shut doWn to conserve battery poWer. For
`example, an LED may remain on (as long as some poWer is
`available) until the user takes action. Others may be con?g
`ured to turn off When the rest of the system does or at some
`?nite duration after activation.
`
`Hybrid Memory Device With Single Interface
`Various aspects of the technology described herein are
`generally directed toWards expanding a memory of a comput
`ing device (such as the device 188) With respect to having
`relatively large amounts of volatile and nonvolatile memory
`in the computing device, Without requiring changes to an
`existing physical architecture of that computing device. In
`general, the description herein provides examples of incor
`porating NAND ?ash memory into a SDRAM-based device
`by adding or substituting a hybrid memory device (e. g., com
`prising one or more chips) containing SDRAM and the
`NAND ?ash, in Which the hybrid memory device has the
`same interface (including pinout, voltage protocol, and
`access protocol) as a conventional SDRAM component.
`HoWever, as Will be understood, these aspects and concepts
`apply to any type or types of volatile and/or nonvolatile
`memory, e.g., various types of DRAM (e.g., EDO) may be
`used instead of SDRAM, DRAM or SDRAM can be con
`versely incorporated into a ?ash-based device, NOR-based
`?ash memory may be mixed With SDRAM and/or With
`NAND-based ?ash, static RAM (SRAM) or other types of
`RAM may be one of the types of memory, more volatile
`memory can be added in place of an existing volatile memory
`device, more nonvolatile memory can be added in place of an
`existing nonvolatile memory device, and so forth. Note that
`the incorporating of different memory types into a hybrid
`memory device (With an interface that ordinarily corresponds
`to an original type of memory for a given design) typically
`adds overall memory to a device, but need not necessarily
`increase (and if desired by the designer can decrease) the
`amount of the original type of memory and/or the overall
`amount of memory.
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`4
`Moreover, as Will be understood, the concepts described
`herein are not limited to What are considered conventional
`computing devices (e.g., desktop, notebook, laptop, or tablet
`based computer systems, personal digital assistants, pocket
`siZed personal computers, or the like), but rather may be used
`in any device that has a need for storing data in volatile or
`non-volatile memory, including mobile phones, set-top
`boxes, hybrid hard disks, television sets, remote controls,
`audiovisual devices, electrical appliances, household appli
`ances and so forth. Each of these devices may add nonvolatile
`memory to a volatile memory design, or vice-versa, or
`increase memory, Without costly and risky hardWare rede
`signs. In this manner, for example, a device With volatile
`memory such as a mobile phone can noW have large amounts
`of non-volatile storage included in it such as to store pro
`grams, music, images, and so forth, simply by replacing a
`memory chip (or multiple memory chips), and updating some
`?rmware to Work With the non-volatile storage, as described
`beloW.
`As such, the present invention is not limited to the
`examples, structures or functionality described herein.
`Rather, any of the examples, structures or functionalities
`described herein are non-limiting, and the present invention
`may be used various Ways that provide bene?ts and advan
`tages in computing and data storage in general.
`Turning to FIG. 2 of the draWings, there is shoWn a general
`example concept of a hybrid memory device 202 device
`including volatile memory 204 (e.g., SDRAM) and nonvola
`tile memory 206 (e.g., NAND ?ash). A controller 208 con
`tains logic that determines Which of the memories 204 or 206
`to access, based on addresses and commands, e. g., originated
`at ?rmWare/ software and addressed through a CPU.
`As represented in FIG. 2, the controller 208 may include or
`otherWise be associated With a buffer set 210 comprising one
`or more buffers, Which in one implementation is used for
`speed matching purposes. For example, at present SDRAM is
`signi?cantly faster than ?ash, and thus a hybrid memory chip
`that has an interface that appears to external components be
`an SDRAM device needs to buffer data in the buffer set 210
`(e.g., SDRAM, DRAM or SRAM) in order to comply With the
`SDRAM protocol With respect to speed and output require
`ments, including burst mode requirements. Thus, the buffer
`set 210 typically comprises memory such as SDRAM or
`static RAM (SRAM) that is at least as fast as a given SDRAM
`chip and its protocol requires, otherWise the hybrid device at
`times Would appear to external components to be bad
`memory. Note that a hybrid memory device that added fast
`memory (e.g., SDRAM) to a sloWer (e.g., ?ash) interface
`Would not necessarily need such a buffer.
`FIG. 3A shoWs an example concept of hoW one hybrid
`memory device 302A generally operates, in Which ?ash
`memory 306 is arranged as some number of blocks (e.g.,
`blocks F-1 through F-n) and is accessed through an SDRAM
`interface. The hybrid memory device 302A also includes an
`SDRAM device 304. As described beloW, an on-chip control
`ler 308A (e.g., corresponding to the controller 208 of FIG. 2)
`determines Which section of SDRAM 304 or ?ash to access
`With respect to a current address originated at the CPU 389. In
`general, the controller 308A receives commands, data and
`addresses from the CPU 389 that are output according to the
`conventional SDRAM protocol. Note that the CPU is not
`required to knoW anything about the different types of
`memory on the hybrid chip, and operates as normal over its
`existing SDRAM-based bus.
`In FIG. 3A, the controller 308 includes logic that can detect
`addresses sent to the hybrid device’s SDRAM address lines
`that are part of its interface. Some of the addresses in the
`
`

`

`US 7,716,411 B2
`
`5
`addressable address range correspond to SDRAM, and for
`those addresses, the controller 308A allows the addresses,
`commands and data to be handled by the SDRAM device 304
`(e. g., forwards the equivalent ones and Zeros or does not
`disable the device from seeing the ones and Zeros). As a result
`for those addresses the hybrid device acts as a conventional
`SDRAM device.
`Certain addresses in the addressable range, however, (typi
`cally comprising a contiguous range referred to as a desig
`nated block 320) are known to the controller 308 to be asso
`ciated with the ?ash, and essentially act as a window into the
`?ash memory 306. For example, the designated block may
`correspond to the ?ash block siZe, e.g., 128 KB in one type of
`?ash device. When addresses within the designated block 320
`are transferred, the SDRAM device 304 is disabled (actually
`or effectively) by the controller 308. The controller 308
`instead sends commands to the ?ash memory device 306, or
`controls the ?ow of read and write data to the ?ash memory
`device 306. Depending on the design, the controller 308 may
`disable the SDRAM component 304 by changing an appro
`priate device input line (e.g., chip enable) of the device 304 to
`disable, by not forwarding received addresses to the device
`304, and/or by forwarding the addresses (e.g., if needed for
`refresh) but not allowing data writes or returning any data for
`a read.
`Note that the amount of ?ash 306 is not limited to the siZe
`of the designated block 320; rather there may be multiple
`?ash blocks (or other arrangements of ?ash memory), with
`the controller 308 accessing each block or the like according
`to additional mapping information that identi?es which part
`(e.g., block) of the total ?ash 306 is to be accessed. This
`additional mapping information may be written to other
`memory locations known to the controller 308, e.g., at the
`high end of addressable memory, (or possibly as a supplement
`to the designated block). Firmware 330, already present on
`essentially all computing devices, may be updated to read and
`write this information in accordance with a suitable protocol
`via the CPU 389, (as represented in FIG. 3A by the dashed
`lines from the ?rmware 330 through the CPU 389 to the
`controller 308A; in this manner, commands, data and status
`information 332 may be communicated between the device
`?rmware 330 (and/or other requesting code, hereinafter
`referred to as the ?rmware 330 for simplicity) and the hybrid
`memory device 302A.
`FIG. 3B is a representation of a similar concept to that of
`FIG. 3A, except that in FIG. 3B the alternative controller
`3 08B may have multiple buffers 3 1 0-1 and 3 1 0-2 correspond
`ing to multiple windows 320A and 320B, separately mapped
`to multiple ?ash blocks (e.g., currently ?ash block A1 and
`Flash block B0 in FIG. 3B). As can be readily appreciated,
`while only two such parallel (and thus typically faster)
`accesses to ?ash memory devices are shown in FIG. 3B, any
`practical number may be used.
`By way of example of how the controller maps the window
`(FIG. 3A) or windows (FIG. 3B) to the correct section or
`sections of ?ash, FIG. 4 shows a linearly-represented address
`range 440 corresponding to the range of a conventional
`SDRAM device, which in this example is 4 Mwords by 16
`bits. For purposes of simplicity, the mapping will be
`described with respect to the single designated block 320 of
`FIG. 3A, however it can be readily understood that separate
`mapping may be performed in essentially the same manner.
`In the example of FIG. 4, the last two blocks corresponding
`to the SDRAM address space are used by the controller 308
`and ?rmware 330 as a command channel 444 and data chan
`nel 442 to the ?ash memory device 306. The mapping and
`other information 332 (FIG. 3) in these blocks 442 and 444
`
`5
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`6
`may be read and written by the controller 308 via any suitable
`protocol understood by the controller 308 and the source of
`that additional information (e.g., ?rmware code 330). Thus,
`by accessing the additional information 332 (or 333 in FIG.
`3B) at the controller 308, e.g., the last two one kilobyte word
`blocks, command and data paths for communicating with the
`?ash device 306 are established. Other information may also
`be in these spaces. For example, the device ?rmware 330 can
`use this section of memory to employ a bootstrapping proto
`col by which the ?rmware 330 can determine whether the
`memory device is truly a hybrid device, because in general the
`hybrid memory device 302A of FIG. 3 otherwise would be
`indistinguishable from a conventional SDRAM device. Other
`possible data communicated via these blocks may, for
`example, inform the controller 308A where the designated
`block 320 is (or blocks in FIG. 3B are) located within the
`addressable memory; e. g., in this manner, the designated
`blocks can move, including dynamically if desired.
`Turning to an explanation of the operation of one example
`hybrid memory device, one suitable command protocol com
`prises a serial protocol used to transfer address block and
`command information (e.g., 332 in FIG. 3A) for the ?ash
`device. Note that because the controller 308A is responsible
`for translation of the command and address information, the
`protocol is con?gurable to access different types of ?ash
`devices; e.g., one type of NAND device uses a NOR SRAM
`interface, whereby the control logic accesses blocks of data,
`which are then be serialiZed to suit the SDRAM data delivery
`protocol. Write data to the ?ash 306 will likewise be con
`verted by the controller 308A as required by the ?ash proto
`col, e.g., 2 KB is written at a time to one such ?ash device.
`As can be readily appreciated, because SDRAM is pres
`ently one or more orders of magnitude faster than ?ash, the
`protocol includes a way for the controller 308A to signal to
`the ?rmware 330 when a ?ash read or write request is busy
`and when the request is ready. A status register in the location
`332 may be used. For example, the ?rmware 330 sends a read
`or write command via the command block 332; the status,
`which may be a bit that is part of the command, is set by the
`controller upon receiving a ?ash request to Zero to indicate
`busy. Note that the controller 308A need not ?ip the status to
`busy if on a read request the controller 308A knows that the
`designated block already contains the correct data for the
`current mapping.
`In a typical situation, the controller 308A sets the status to
`busy and for a read, and begins ?lling the buffer 310 with the
`requested data. When the buffer contains the correct data,
`(which may be more than requested in anticipation of a sub
`sequent read request), the controller 308A toggles the status
`to ready. The ?rmware 330, which is polling the status since
`it sends the request, then knows the requested data can be
`read, which the controller 308A then outputs from the buffer
`310. For example, in accordance with the SDRAM protocol,
`the controller will output a single set of data (e.g., byte) for the
`requested address if a single output is requested, or a timed
`burst output of multiple sets of data starting with that address,
`with the number of sets output corresponding to the current
`burst mode. Note that the current burst mode may be estab
`lished via a hardwired setting, including a setting that indi
`cates the burst mode is soft-controlled; in any event the mode
`is known to the controller 308A via the SDRAM-equivalent
`setup lines and/ or a command (for soft-controlled burst).
`Writes are similarly handled, with the data at the desig
`nated block copied by the controller 3 08A into the buffer 31 0,
`while the controller provides a busy signal that is polled by the
`?rmware until the write request is actually completed by
`writing to the slower ?ash. As with a read request, for a write
`
`

`

`US 7,716,411 B2
`
`20
`
`25
`
`7
`request the hybrid memory device 302A appears to the CPU
`389 to operate at the correct SDRAM speeds, and the CPU is
`unaware of any status polling going on between the ?rmware
`330 and the controller 308A. Via the protocol, synchronous
`memory is thus operated properly from the perspective of the
`CPU, but is actually operated asynchronously from the per
`spective of the requesting entity.
`Thus, by adding a memory controller to a hybrid memory
`device comprising SDRAM and ?ash with a standard
`SDRAM interface, the ?ash memory is overlaid in the
`SDRAM address space. A command protocol (e.g., serial) is
`used to manage the mapping of the ?ash blocks/pages to the
`SDRAM address space. This permits a single pin compatible
`multi-chip package to replace an existing SDRAM device in
`any computing device that wants to provide ?ash storage, yet
`do so with only ?rmware changes to the device. For example,
`the buffer of a conventional disk drive may be replaced with
`a single chip upgrade that provides ?ash storage, whereby the
`?ash storage can be used with new ?rmware to upgrade
`existing drives to hybrid drives. Further examples include
`adding nonvolatile storage to a set-top-box design, or a
`mobile phone design that was designed with no built-in mass
`storage at the time, but is now desirable, e.g., due to some new
`application or business model.
`By way of example of a speci?c architecture, FIGS. 5 and
`6 demonstrate the use of actual SDRAM and NAND Flash
`devices, with the interface and internal components con?g
`ured for one example SDRAM voltage protocol and SDRAM
`access protocol, whereby only software changes (e. g., in
`device ?rmware) are needed to now make use of the nonvola
`tile memory in the package. However, it is understood that
`essentially any device with de?ned addressing characteristics
`may be used. Note that the architecture in FIGS. 5 and 6 show
`the use of 16 bit data paths, which is a common application,
`although as can be readily appreciated, other data path widths
`work in the same manner. In this example, a multi-chip pack
`age is described that can physically replace the SDRAM chip
`in a computing device, yet incorporates both volatile
`SDRAM memory as well as nonvolatile NAND ?ash
`memory.
`The SDRAM device 504 represented in FIG. 5 comprises a
`burst mode device (e. g., a Micron® MT48LC4M16A2
`device) supporting 1 byte, 2 byte, 8 byte, or page transfers,
`and for example, may be used in a hybrid memory device 602
`(FIG. 6) that includes two gigabits of NAND Flash 606. As
`45
`represented in the example architecture for the SDRAM
`device of FIG. 5, as with a conventional SDRAM device, the
`hybrid memory device accepts RAS/CAS (the well-known
`row access strobe and column access strobe) signals on the
`address lines (e.g., A0-A11, BAO-BA1), and for other than
`single byte reads or writes, reads or writes data sequentially
`from the RAS/CAS starting address. Note that the computing
`device that uses this type of memory buffers the serially
`accessed data, which is typically done by the onboard cache
`in many computing devices.
`Because the data is provided serially based on a start
`address, the (relatively low latency) memory controller 308
`between the host (e.g., CPU) and the SDRAM 504 is able to
`detect the addresses being sent to the chip. By detecting
`particular address ranges, the CE# (enable) for the SDRAM
`60
`interface can be used to place the device 504 into a refresh
`cycle, with data provided by another source.
`In FIG. 5, the control logic of the controller 308 detects
`addresses sent to the SDRAM. As described above, when
`addresses within the designated bloc