(19) United States
`(12) Patent Application Publication (10) Pub. N0.: US 2006/0294295 A1
`Fukuzo
`(43) Pub. Date:
`Dec. 28, 2006
`
`US 20060294295A1
`
`(54) DRAM CHIP DEVICE
`WELL-COMMUNICATED WITH FLASH
`MEMORY CHIP AND MULTI-CHIP
`PACKAGE COMPRISING SUCH A DEVICE
`
`(
`
`76
`
`)
`
`-
`
`'
`
`Inventor' Yuklo Fukuzo’ Muenchen (DE)
`Correspondence Address,
`SLATER & MATSIL LLP
`17950 PRESTON ROAD
`SUITE 1000
`D ALL As.J TX 75252 (Us)
`
`(21) Appl_ No;
`
`11/166,789
`
`(22) Filed;
`
`Jun_ 24, 2005
`
`Publication Classi?cation
`
`(51) Int. Cl.
`G06F 12/00
`
`(2006.01)
`
`(52) US. Cl. .......................................... .. 711/105; 711/103
`
`(57)
`
`ABSTRACT
`
`An SDRAM memory chip device comprises a non-volatile
`memory controller for operating a non-volatile memory,
`e.g., a NAND-?ash, and a FIFO memory buiTer. The FIFO
`memory buiTer serves to operate background store and load
`operations between a FIFO buiTer array and the non-volatile
`memory, While a host system such as a CPU exchanges data
`With the SDRAM Work memory. The SDRAM memory chip
`device, therefore, has at least tWo additional pins as com
`pared With conventional SDRAM standard for generating a
`set of additional commands. These commands are employed
`by the FIFO memory buiTer to manage the data transfer
`between the FIFO buiTer and each of the non-volatile
`memory and the volatile SDRAM memory. TWo further pins
`re?ecting the ?ash memory status provide appropriate issu
`ance of load or store signals by the host system.
`
`14
`
`10
`
`F40
`
`20
`
`so
`
`SDRAM
`Clock
`Generator
`
`120
`
`SDRAM/FIFO
`Control
`in
`
`1
`
`170
`
`110
`30
`
`40
`
`Bank
`Select
`
`ister
`
`Decoder
`1
`
`12
`
`2
`
`Bank 4
`
`Column
`Address
`Butler
`FlFO
`B_BUS1
`Timing
`R
`Row Decoder Generator
`Addor‘gss
`5
`—
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`g HFO
`294
`B-Reiresh
`D .
`C Array
`1 2
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`
`lnput/
`Output
`
`y
`
`1
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`195
`
`290 294
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`380
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`
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`Comma
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`
`Data
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`
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`Logic
`Buffer
`
`/CE
`CLE
`ALE
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`/WE
`
`MP
`
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`[1-16]
`
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`/BY
`
`340
`
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`Multiplexer
`
`|
`Logic
`280
`
`CKE
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`é /WE
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`0
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`
`DO [1-32]
`DQlVl [1-4]
`
`

`

`Patent Application Publication Dec. 28, 2006 Sheet 1 0f 4
`
`US 2006/0294295 A1
`
`FIG1 APRIORART
`514
`1’
`
`512
`
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`
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`514b
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`
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`chip
`
`A
`/
`baseband
`chip
`
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`CPU
`core
`
`

`

`Patent Application Publication Dec. 28, 2006 Sheet 2 0f 4
`
`US 2006/0294295 A1
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`Patent Application Publication Dec. 28, 2006 Sheet 3 0f 4
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`US 2006/0294295 A1
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`Patent Application Publication Dec. 28, 2006 Sheet 4 0f 4
`
`US 2006/0294295 A1
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`

`US 2006/0294295 A1
`
`Dec. 28, 2006
`
`DRAM CHIP DEVICE WELL-COMMUNICATED
`WITH FLASH MEMORY CHIP AND MULTI-CHIP
`PACKAGE COMPRISING SUCH A DEVICE
`
`TECHNICAL FIELD
`
`[0001] The present invention relates generally to semicon
`ductor components and, in various aspects, to a DRAM chip
`device Well-communicated With ?ash memory chips and
`multi-chip packages comprising such a device.
`
`BACKGROUND
`
`[0002] Mobile systems such as cellular phones and digital
`cameras. have recently seen considerable improvements
`With respect to its system logic as Well as its associated
`memory. According to the speci?c requirements of such a
`system, a variety of memory types is noWadays included into
`mobile systems simultaneously.
`[0003] For example, cellular phones as Well as digital
`cameras have a system logic, Which comprises a number of
`chips performing speci?c tasks associated With a mobile
`system. A cellular phone, e.g., has a base band chip for
`performing Wireless communication tasks and further a
`digital signal processing (DSP) chip, Which may control a
`charged coupled device (CCD) that is attached to a camera
`part of the cellular phone.
`
`[0004] Recent developments indicate that this system of a
`communication CPU (CCPU) combined With multiple
`application CPU’s (ACPU) tends to be uni?ed into one
`combined chip. HoWever, the combination of a CCPU With
`a number of ACPU’s performing communication and digital
`signal processing tasks into one chip may meet considerable
`constraints as the number of interfaces needed for associat
`ing different memory types With the distinct sections of a
`respective uni?ed CPU consumes chip area and further
`requires and unnecessarily large amount of voltage supply.
`[0005] FIG. 1 illustrates the problem of multiple inter
`faces. A uni?ed CPU 502 comprises an interface 504, that
`provides a communication With a loW poWer SDRAM 516
`(synchronous dynamic random access memory) via 60 data,
`command and address lines, or pins respectively, if the
`SDRAM is a x32 component. The SDRAM 516 serves as a
`Work memory.
`
`[0006] Further, a second interface 506 has 27 data, com
`mand and address lines, Which provide communication With
`a NAND-?ash memory 514 serving as a permanent storage
`(non-volatile memory) for large amounts of user data, e.g.,
`image data.
`
`[0007] Still further, a third interface 508 has 44 data,
`command and address lines, Which provide communication
`With a NOR-?ash memory 510, Which also houses a pseudo
`SRAM 512. This latter memory is designed to store program
`?les and code data, since NOR-?ash memory 510 generally
`provides faster read or Write access to the cells of that
`memory, While the storage density is someWhat smaller as
`compared With the NAND-?ash memory 514.
`
`[0008] As a result, the CPU 502 has interfaces that sum up
`to 131 pins according to this prior art example. It has,
`therefore, been a requirement to reduce the number of
`interfaces needed to associate different types of memory
`With a single CPU. The easiest Way to proceed Would be to
`
`unify the system of non-volatile memories (NAND, NOR)
`for permanent data storage With the Work memory of the
`volatile SDRAM. HoWever, a technical di?iculty is raised as
`to the large difference in clock rate and data transfer speeds
`betWeen the SDRAM and the ?ash memory types. For
`example, SDRAM is clocked at a rate of, e.g., 300 MHZ,
`While ?ash memory is clocked at rates beloW 30 MHZ.
`
`[0009] The need for a uni?cation of the memory interfaces
`in order to reduce the amount of interface pads on the side
`of the system logic (i.e., CPU) is further increased due to
`future technology prospects. Currently, the 130 nm technol
`ogy employs tWo CPU chips (CCPU and ACPU), Which
`each require for example 200 pads in order to communicate
`With other system components via their interfaces. For the
`year 2007, for Which the 80 nm technology is planned, one
`enlarged uni?ed chip having 500 pads and providing core
`and application functions, Will be introduced to mobile
`systems. Further shrinking doWn to the 60 nm technology is
`then expected to meet problems yet unsolved due to the
`considerable amount of chip area consumed by the pads.
`
`[0010] US. Patent Application Publication No. 2005/
`0027928 Al, by M-Systems Flash Disk Pioneers, Ltd.,
`Israel, propose to cancel NOR-?ash and SRAM memory and
`to use the SDRAM interface for accessing the SDRAM as a
`Work memory and the NAND-?ash controller on the same
`chip device, simultaneously. The NAND-?ash memory itself
`is placed on a second chip, Which is connected to the
`controller by means of an internal interface. HoWever,
`means to handle the speed differences and to operate the
`different memory components in a cost and time effective
`way are not provided according to that proposal.
`
`SUMMARY OF THE INVENTION
`
`[0011] In one aspect, the present invention reduces the
`costs of implementing a uni?ed system logic, particularly in
`the case of mobile systems. In a further aspect, the invention
`reduces costs and efforts for providing Work and storage
`memory to a mobile system logic, and in particular to
`provide a uni?ed memory having an as small as possible
`number of interfaces in common With the system logic.
`
`[0012] In a further aspect, the invention reduces the poWer
`supply needed to operate a system logic and the communi
`cation With its associated memory.
`
`[0013] In one embodiment, a memory chip device is
`provided, Which includes a ?rst interface, Which is arranged
`to provide a communication betWeen a DRAM of the device
`and a host system, the DRAM, a controller for controlling
`operation of a non-volatile memory, a second interface,
`Which is arranged to provide a communication betWeen the
`controller and the non-volatile memory, and a ?rst-in/?rst
`out memory buffer. The ?rst-in/?rst-out bulfer is connected
`With the DRAM by means of a ?rst data transfer bus and the
`controller for controlling operation of the non-volatile
`memory by means of a second data transfer bus, for bulf
`ering data to be transferred betWeen the DRAM, or a host
`system, and the controller, Which controls operation of the
`non-volatile memory.
`
`[0014] Another aspect includes a multi-chip package,
`comprising the ?rst memory chip device as set in the
`foregoing, and a second memory chip device comprising the
`non-volatile memory.
`
`

`

`US 2006/0294295 A1
`
`Dec. 28, 2006
`
`[0015] In another aspect, a system includes a central
`processing unit (CPU), the multi-chip package (MCP) as set
`in the foregoing, for permanently storing or reading data
`processed by the CPU and for providing a Work memory for
`program ?les executed by the CPU, and a single bus
`interface for providing communication betWeen the CPU
`and the MCP.
`
`[0016] Amemory chip device has tWo interfaces. The ?rst
`interface is arranged to provide a communication betWeen a
`DRAM section of the device and an external host system,
`e.g., a CPU. According to a preferred embodiment, this
`interface is connected With an external bus, to Which the
`CPU also has access.
`
`[0017] The second interface of the memory chip device is
`arranged to provide a communication betWeen a non-volatile
`memory controller and the non-volatile memory. According
`to a preferred embodiment of the invention, this interface
`does not have access to further components by means of an
`external bus system, i.e., rather this second interface pro
`vides an internal bus betWeen the controller and the non
`volatile memory.
`
`[0018] As a consequence, the memory chip device asso
`ciates two different types of memory, e.g., a volatile
`memory, preferably a DRAM memory, and a non-volatile
`memory, preferably a ?ash memory, and most preferably a
`NAND-?ash memory, With a central CPU via one single
`interface, e.g., the ?rst interface.
`[0019] A ?rst-in/?rst-out memory buffer is implemented
`on the memory chip device and separates a DRAM core
`section from the non-volatile memory controller section. In
`particular, this ?rst-in/?rst-out (FIFO) memory bulfer sepa
`rates the data transfer betWeen the DRAM core section and
`the non-volatile memory controller section. As a result, data
`provided to the memory chip device from the host system
`via the ?rst interface is not directly provided to the non
`volatile memory controller, but ?rst has to be input to the
`FIFO memory bulfer.
`
`[0020] Further, as the ?rst interface is arranged to provide
`a communication betWeen the DRAM and the host system,
`this interface is arranged With sets of command, address, and
`data lines in agreement With Well-knoWn DRAM, or
`SDRAM standards.
`
`[0021] The FIFO memory bulfer provides a means to
`intermediately store the data incoming from the host system
`(e.g., CPU) or the DRAM core section. Further command
`signals incoming at the ?rst interface are evaluated in terms
`of commands valid for operations performed by the non
`volatile memory controller and/or the FIFO memory buffer.
`
`[0022] According to one aspect of the invention, tWo
`additional pins are provided for this purpose With the ?rst
`interface as compared With a conventional SDRAM inter
`face. These additional pins are arranged to transfer a ?fth
`and a sixth command signal in addition to the conventional
`/CS, /RAS, /CAS, and /WE command signals. It is noted that
`the conventional /BSL (bank select signal) is not referred to
`as a command signal throughout this document. According
`to another embodiment, a third set of additional pins is
`arranged to provide a FIFO memory bulfer bank select
`signal in case that memory is also arranged in terms of banks
`similar to the DRAM core section (Which then is an
`SDRAM).
`
`[0023] Using a command decoder, any combination of
`high or loW signal levels emulates a speci?c command that
`yields an operation of a control logic of the SDRAM core
`section. Using these tWo additional pins, a su?icient set of
`further commands may be emulated according to embodi
`ments of the invention, Which serve to control operation of
`the tWo separate data transfer buses mentioned above and
`further to control the operation of the non-volatile memory
`by means of the corresponding controller.
`
`[0024] According to one aspect of the invention, the
`non-volatile memory is a ?ash memory, in particular a
`NAND-?ash memory. In this case, the emulated commands
`mentioned With the previous aspect relate to a standard set
`of commands for the NAND-?ash controller.
`
`[0025] According to a further aspect of the invention, the
`non-volatile memory controller section further comprises an
`input/output data bulfer. As this buffer may be clocked With
`a local clock of the non-volatile memory controller, this unit
`supplies a speed exchange of the data transfer to the non
`volatile memory unit.
`
`[0026] According to a further aspect, the FIFO memory
`buffer is provided With a FIFO data processor, Which con
`trols the data transfer betWeen the FIFO memory array and
`the controller section of the non-volatile memory, and fur
`ther betWeen the FIFO memory array and the DRAM or
`SDRAM array. Alternatively, the latter data transfer, i.e., on
`the ?rst data transfer bus, may be managed by an SDRAM
`control logic, Which also performs FIFO memory bu?'er
`functions. This is particularly advantageous When the FIFO
`memory bulfer array is organiZed as an SDRAM memory
`similar to the SDRAM of the SDRAM core section serving
`as a Work memory. It is then straightforWard, to have the
`SDRAM control logic additionally control the FIFO
`memory array.
`
`[0027] According to this aspect, multiple Write or read
`operations may be performed on the ?rst data transfer bus
`betWeen the SDRAM array, the FIFO array and the host
`system (CPU). These operations are treated separately from
`those Write or read operations betWeen the FIFO array and
`the non-volatile memory. In the particular case that the host
`system communicates With the SDRAM only, the FIFO
`array is relieved from this communication and can take part
`in a second background communication With the non-vola
`tile memory. Accordingly, simultaneous Write or read opera
`tions can be performed to/ from the SDRAM array and
`to/from the non-volatile memory. The FIFO memory bulfer
`thus serves to optimiZe the process of the sloW store opera
`tion to the non-volatile memory in parallel With a fast store
`operation to SDRAM Work memory due to the CPU.
`
`[0028] According to a further aspect, one or tWo further
`pins are provided to the SDRAM interface, Which serve for
`transferring signal ?ags from the chip device to the host
`system (eg the CPU). These ?ags transfer a ready or busy
`status of the non-volatile memory and/or the FIFO memory
`buffer. The host system is thus alloWed to check these status
`?ag signals in order to issue appropriate command signals,
`resulting in suitable commands, When Writing to the
`SDRAM array, the FIFO array or the non-volatile memory,
`respectively.
`[0029] Although the invention is illustrated and described
`herein as embodied in a memory chip device, a multi-chip
`
`

`

`US 2006/0294295 A1
`
`Dec. 28, 2006
`
`package and a system including a CPU, it is nevertheless not
`intended to be limited to the details shown, since various
`modi?cations and structural changes may be made therein
`Without departing from the spirit of the invention and Within
`the scope and range of equivalents of the claims.
`[0030] The chip device, package and system of the inven
`tion, hoWever, together With additional objects and advan
`tages thereof Will be best understood from the folloWing
`description of speci?c embodiments When read in conjunc
`tion With the accompanying draWings.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0031] For a more complete understanding of the present
`invention, and the advantages thereof, reference is noW
`made to the folloWing descriptions taken in conjunction With
`the accompanying draWing, in Which:
`
`[0032] FIG. 1 shoWs an overvieW of a CPU and its
`associated memory according to prior art;
`
`[0033] FIG. 2, same as FIG. 1, but according to an
`embodiment of the invention;
`
`[0034] FIG. 3 shoWs a schematic block diagram of a
`memory chip device according to an embodiment of the
`invention;
`[0035] FIG. 4 shoWs a more detailed block diagram of a
`memory chip device according to an embodiment of the
`invention; and
`[0036] FIG. 5 shoWs a simpli?ed block diagram illustrat
`ing different load and store operations that may be per
`formed according to an embodiment of the invention.
`
`[0037] The folloWing list of reference symbols can be used
`in conjunction With the ?gures:
`
`[0038] 10 DRAM core section
`
`[0039] 12 DRAM interface
`
`[0040] 14 Pins
`[0041] 20 multi-port FIFO input/output bulfer
`
`[0042] 30 ?ash memory controller section
`
`[0043] 32 ?ash memory interface
`[0044] 40 DRAM chip device
`
`[0045] 50 host system, CPU
`[0046] 60 ?ash memory chip device
`
`[0047] 110 DRAM clock
`
`130 bank select component
`
`140 mode register
`
`150 command decoder
`
`[0048] 120 DRAM and FIFO control logic
`[0049]
`[0050]
`[0051]
`[0052]
`[0053]
`[0054]
`[0055]
`[0056]
`
`160 column address bulfer
`
`170 roW address bulfer
`
`180 data control (lSt bus)
`
`190 DRAM memory array
`
`192 1st data transfer bus
`
`[0057]
`[0058]
`[0059]
`[0060]
`[0061]
`[0062]
`[0063]
`[0064]
`[0065]
`[0066]
`[0067]
`[0068]
`[0069]
`[0070]
`[0071]
`[0072]
`[0073]
`[0074]
`[0075]
`[0076]
`[0077]
`
`210 FIFO data processor
`211 FIFO timing generator
`280 data control (2“1 bus)
`
`290 FIFO memory array
`294 2D01 data transfer bus
`
`310 ?ash memory clock
`
`320 ?ash controller
`
`330 source address register
`
`340 destination address register
`
`380 ?ash data register
`385 ECC logic
`
`390 ?ash input/output bulfer
`
`502 CPU
`
`504,504' interface
`506,520 second interface
`
`508 third interface
`
`510 NOR-?ash memory
`512 pseudo-SRAM
`
`514,514b NAND-?ash memory
`
`514a NAND-?ash controller system
`
`516, 516' SDRAM
`
`DETAILED DESCRIPTION OF ILLUSTRATIVE
`EMBODIMENTS
`
`[0078] FIG. 2 shoWs an overvieW block diagram of a
`system comprising a CPU 502, an SDRAM Work memory
`516' and a NAND-?ash memory 514!) for permanent storage
`of user data and executable program ?les according to a ?rst
`embodiment of the invention. CPU 502 has a single (?rst)
`interface 504' that provides communication With both the
`volatile Work memory 516' and the non-volatile storage
`memory 51419. The Width of this bus is increased to 64 data,
`command and address lines, or pins on the corresponding
`memory chip device, as compared With the 60 lines or pins
`shoWn in the prior art example of FIG. 1.
`
`[0079] HoWever, as interface 504' is the only interface left
`on the CPU side, the total number of lines, or pads required
`on the CPU board 502, is reduced from 131 to 64 according
`to this speci?c example. Therein, the ?ash memory 514!) is
`accessed via a second interface 520 from the SDRAM Work
`memory 516'. More precisely, the SDRAM Work memory
`516' comprises a NAND-?ash controller section 51411,
`Which controls operation of the NAND-?ash memory 51419.
`The 4 additional pins provided via the ?rst interface 504'
`serve to yield additional commands for operating the ?ash
`controller section 51411 as Well as a FIFO memory bulfer
`section provided With the SDRAM memory chip device.
`
`[0080] FIG. 3 shoWs a schematical block diagram With a
`similar SDRAM memory chip device 40, Which is interfaced
`With a ?ash memory device 60 according to a second
`embodiment of the present invention. The ?ash memory
`device 60 used in this embodiment is a NAND-?ash
`memory.
`
`

`

`US 2006/0294295 A1
`
`Dec. 28, 2006
`
`[0081] The SDRAM memory chip device 40 according to
`this embodiment may be divided into three sections: an
`SDRAM core section 10, a FIFO bulfer section 20 and a
`?ash controller section 30. Nevertheless, all three sections
`may be manufactured on the same chip or die, While the ?ash
`memory device 60 accessed via the interface directly from
`the SDRAM memory device may be manufactured on
`another chip, or die.
`
`[0082] The SDRAM core section 10 comprises an inter
`face 12 to a host system such as a central processing unit 50
`(CPU). The interface 12 comprises a plurality of pins 14,
`Which are arranged to adhere to the SDRAM standard.
`According to their functions, the pins may be grouped into
`those transferring clock signals, address signals, command
`signals, bank select signals and data signals. As indicated in
`FIG. 3 by the double arroWs, additional pins are provided to
`the interface as compared With the SDRAM standard. These
`additional pins are arranged to transmit signals, Which yield
`control of background store and load operations With respect
`to those data intended for permanent storage Within the
`NAND-?ash memory, While data are transferred betWeen
`the host CPU 50 and the SDRAM array 190.
`[0083] The ?rst interface 12 further comprises pins, Which
`signal the ready or busy status of the FIFO bulfer section 20
`and/ or the NAND-?ash memory 60 from the chip device 40
`to the CPU 50.
`
`[0084] The SDRAM core section 10 has a clock generator
`110, Which generates an internal clock (running at, e.g., 130
`MHZ) from the incoming clock signals. This clock is valid
`for the SDRAM core section 10 and the FIFO memory
`bulfer section 20. The clock is forWarded to the ?ash
`controller section 30, Where a ?ash clock generator 310
`generates a ?ash clock from the SDRAM section clock,
`Which is valid for this section, e.g., at 20 MHZ.
`[0085] Each of the three sections 10, 20, 30 of the chip
`device 40 comprises a memory array or buffer With registers.
`The SDRAM core section 10 comprises an SDRAM
`memory array 190 With a siZe of, e.g., 64 MB. The FIFO
`memory buffer 20 also comprises a FIFO SDRAM array 290
`With a siZe of 2 MB. The ?ash controller section 30
`comprises a data register 380 attached to the input/output
`buffer 390 having a siZe of 2 kB.
`
`[0086] Both arrays 190, 290 are connected by a ?rst data
`transfer bus 192. This ?rst data transfer bus is controlled by
`the SDRAM control logic 120, Which receives commands
`emulated from the command signals incoming at the inter
`face 12. The ?rst data transfer bus may have a Width of 8,
`16, 32, or 64 bits and is arranged either for bi-directional
`data transfer or consists of each a unidirectional read and
`Write bus.
`
`[0087] A FIFO data processor 210 controls a second data
`transfer bus 294 in response to emulated background store
`and load commands. The second data transfer bus 294
`connects the FIFO memory array 290 With a ?ash input/
`output buffer 390, that is associated With data registers 380
`and an ECC logic 385 (see detailed FIG. 4). This latter
`buffer and register section performs the transfer speed
`adaption With regard to the sloWer ?ash controller clock 310.
`The second data transfer bus 294 may have a Width of 8, 16,
`32, or 64 bits and is arranged either for bi-directional data
`transfer or consists of each a unidirectional read and Write
`bus.
`
`[0088] A standard NAND-?ash interface 32 provides the
`data transfer and the command control to or from the ?ash
`memory device 60. Therein, the NAND-?ash controller 320,
`Which controls this operation is positioned on the present
`memory chip device 40.
`
`[0089] FIG. 4 shoWs a more detailed block diagram
`according to the second embodiment of the invention.
`Herein, the ?rst interface 12 comprises multiple pins 14
`adhering to the SDRAM standard.
`
`/CS: chip select and command active signal;
`
`/RAS: roW active signal
`
`/CAS: column active signal
`
`[0090] The pin de?nitions of the clock signals are:
`[0091] CLK: system clock input With other signals being
`referenced to the CLK rising edge;
`[0092] /CLK: inverted signal of system clock, available
`for DDR memory (double data rate) With referencing of
`signals to the falling edge;
`[0093] CKE: clock enable signal
`[0094]
`The pin de?nitions of the command signals are:
`[0095]
`[0096]
`[0097]
`[0098]
`[0099]
`[0100]
`[0101] The command signals /LD and /ST go beyond the
`SDRAM standard and are provided additionally to interface
`12 for controlling background load (/LD) and for controlling
`a background store (/ ST) of data intended for long duration
`storage Within the non-volatile memory. Each of the com
`mand signals may attain a high or loW level With respect to
`a clock timing.
`
`/WE: Write or read enable signal
`
`/LD: data load enable signal
`
`/ ST: data store enable signal
`
`[0102] Counting CKE as a command signal, a set of at
`least 13 commands to operate the SDRAM core section 10
`may be emulated from any combination of signal levels (loW
`or high) of conventional SDRAM signals CKE, /CS, /RAS,
`/CAS, /WE by means of a command decoder 150. A so
`called command truth table may be set up thereof, Which
`associates available commands With particular combinations
`of signal levels, i.e., high or loW, of the incoming command
`signals at the respective pins. The commands are received
`and executed by an SDRAM core logic 120, Which also
`performs control tasks With respect to the FIFO bulfer
`section 20.
`[0103] Using the additional pins With respective signals:
`/LD and /ST, sets of further commands may be established
`according to combinations of signal levels With those of the
`signals stated above by means of the command decoder 150.
`In this embodiment, these are nine additional commands.
`Four of these commands relate to NAND-?ash commands:
`RST (reset), STR (status register), IDR (chip ID register),
`ABE (automatic block erase). TWo of the nine additonal
`commands relate to the control of the data transfer betWeen
`the SDRAM FIFO memory array 290 and the ?ash memory
`input/output buffer 390 (second data transfer bus 294): /LD
`(background load), /ST (background store). Further, three
`additional commands of the set of nine commands relate to
`controlling the data transfer betWeen the SDRAM core
`
`

`

`US 2006/0294295 A1
`
`Dec. 28, 2006
`
`memory array 190 and the FIFO memory array 290: CP
`(automatic copy), BU (automatic back up) and DAS (des
`tination-address-strobe).
`[0104] These three latter commands CP, BU and DAS are
`performed automatically, i.e., not as a background operation,
`directly in response to the command signals issued by the
`CPU. However, commands /LD and /ST are background
`operations. Accordingly, the duration of the performance is
`not previously knoWn and further signals FIFO and FLASH
`With respective ?ag signal pins are needed as described
`beloW in order to provide a feedback to the CPU 50 of What
`is currently the status in the background (betWeen FIFO
`buffer memory section 20, ?ash controller section 30 and
`?ash memory device 60).
`[0105] Once being emulated, the commands are received
`by either the SDRAM core logic 120 or the FIFO timing
`generator 211, Which represents the data processor 210
`shoWn in FIG. 3, for controlling the respective data transfer
`busses. The four ?ash memory control commands are for
`Warded to the NAND-?ash controller 320.
`
`[0106] The device further has indicator signals /FIFO and
`/FLASH, Which are sent to the CPU 50 via respective tWo
`additional pins of interface 12. These signals serve to ?ag the
`status of the FIFO bulfer section 20 and the ?ash controller
`section 30, or the ?ash memory device 60, respectively, to
`the CPU 50. The CPU 50 may issue appropriate command
`signals independent of these signals ?agged.
`[0107] SDRAM core section 10 further comprisesiac
`cording to this embodimentia mode register 140 and a
`bank select component 130. The bank select component 130
`bulfers the bank select signal incoming at a respective pin of
`the ?rst interface 12. Using this signal, one of the banks 0-3
`of the array 190 may be selected for read or Write access in
`agreement With the SDRAM standard. In addition to the
`bank select pin (pin de?nition: BSL), a further pin may
`optionally be provided to select a bank of the FIFO memory
`bulfer array 290, if this is array 290 as Well arranged in terms
`of banks according to the SDRAM standard. In FIG. 4, a pin
`de?nition FBS (FIFO bulfer select) is associated With this
`signal.
`[0108] SDRAM core section 10 further comprises roW and
`column address bulfers 160, 170 to receive addresses via
`pins ADD[0:20]. A data control component 180 is controlled
`by the SDRAM/FIFO control logic 120 in order to manage
`the data transfer on the ?rst data transfer bus.
`
`[0109] A background load operation in accordance With
`this embodiment may be performed as folloWs: An /LD
`command (background load command) is issued (e.g., With
`/CS and /LD being “loW” and /RAS, /CAS, /WE, /ST and
`CKE being “high”) With a source address “SA” of a NAND
`?ash memory page provided via the address pins ADD by
`the CPU 50. SA relates to the page of the NAND memory
`to be loaded into the FIFO buffer section.
`
`[0110] Immediately, the /FLASH ?ag is set via the respec
`tive pin. With a DAS command (destination address strobe:
`e.g., With /CS, /LD and /ST being “loW” and /RAS, /CAS,
`/WE and CKE being “high”) issued three clock periods later
`according a prede?ned rule, a bank of FIFO memory bulfer
`array 290 is selected (command FBS) and an address “DA”
`Within FIFO memory bulfer array 290 is provided as a
`destination address via address pins ADD.
`
`[0111] Next, the CPU 50 performs an automatic fore
`ground Write operation to the SDRAM array 190. An ACT
`command is issued three clock periods after the DAS
`command in order to activate a roW (e.g., With /CS and /RAS
`being “loW” and /CAS, /WE, /ST, /LD and CKE being
`“high”). A bank address (command ESL) and a roW address
`“RA” (via address pins) is transmitted thereWith. Then a
`Write WR (e.g., With /CS, /CAS and /WE being “loW” and
`/RAS, /LD, /ST and CKE being “high”) is performed With
`transferring a column address CA to the column address
`buffer 160.
`
`[0112] In response to this command, a data sequence of
`eight bits, i.e., a Word, is transferred via DQ pins DQ[1-32]
`of interface 12 into SDRAM array 190 and Written into those
`memory cells having the logical roW, column and bank
`address provided as stated above.
`
`[0113] In the meantime, the background load from the
`NAND-?ash memory to the FIFO bulfer has started. The
`addresses “SA” and “DA” Were transferred to respective
`destinations and source registers 330, 340 of the ?ash
`controller section 30. The /LD command is recogniZed by
`the FIFO timing generator 211.
`
`[0114] Flash controller section 30 has a generic interface
`32 to communicate With the ?ash memory device 60. This
`second interface 32 is provided With pins having a de?nition
`as folloWs:
`
`[0115] /CE chip enable With active loW
`
`[0116] CLE command latch enable With active high
`
`[0117] ALE address latch enable With active high
`
`[0118] /RE read enable
`
`[0119] /WE Write enable
`
`[0120] /WP Write protect enable
`[0121] RD,/BY ready or busy input signal
`[0122] NDQ[1-16] input/outpu