_
`
`Umted States Patent [19]
`Urbas et a1.
`
`llllllllllllllllllllllllllllllllllllllllllIllllllllllllllllllllllllllllllll
`[11] Patent Number:
`5,252,962
`[45] Date of Patent:
`Oct. 12, 1993
`
`USOO5252962A
`
`[54] SYSTEM MONITORING PROGRAMMABLE
`IMPLANTABLE TRANSPONDER
`
`5,028,918 7/1991 Giles et a1. ................... .. 340/ 825.54
`5,105,190 4/1992 Kip et al. ..................... 1. 340/825.54
`
`[75] Inventors: Donald J. Urbas, Evergreen; David
`Ellwwd, 691d“, both of C010-
`[73] Assignee: Bio Medic Data Systems, Maywood,
`Ni
`
`[21] App]. No_: 562,300
`,
`[221 Flledr
`
`4118-3, 1990
`
`FOREIGN PATENT DOCUMENTS
`0101125 2/1984 European Pa1.0fl‘. .
`8704900 8/1987 European P“ Off- '
`0261081 3/1988 European Pat. Off. .
`2070393 9/1981 United Kingdom .
`2077556 12/1981 United Kingdom .
`2163324 2/1986 United Kingdom .
`2164825 3/1986 United Kingdom .
`
`6
`[5 1
`
`.
`.
`[51] Int. Cl.5 ............................................ .. G08C 19/16
`P”’.’"”y Ex‘""”.’”_D9“a1d 1' Yusk?
`[52] us. (:1. ........................ .. 840/870.17; 340/825.54;
`Asszslanl Exam1ner—M1chae1 Horablk
`_
`A“
`A t
`F.
`Bl K 1
`340/573, 123/903
`“"9” gen’ °’ "m"- “m *‘P 3“
`[58] Field of Search .................... .. 340/870.17, 825.54,
`57
`ABS-TR AC1
`340/505, 573, 572, 825.31, 825.69; 342/44, 50,
`[
`1
`51; 128/903; 119/5102; 307/465; 455/19
`A passive transponder includes a receive antenna for
`.
`receiving an input signal. A frequency generator and
`References cued
`modulator receives the input signal and outputs a data
`US. PATENT DOCUMENTS
`Carri“ Signal having a frequency independent of the
`4,114,151 9/1978 Denne et al. ........................ .. 455/19
`input Signal frequency- A Programmable memory and
`4,631,708 12/1986 Wood et al. ..
`. 340/825 54
`thermistor are provided to produce user 1D data and
`4,730,188 3/1988 Milheiser
`340/825 69
`4,737,967 4/1983 Cah?l?n
`340/310 A temperature data which is combined with the output
`4,857,893 8/1989 Carroll ........ ..
`340/82554
`sigrm
`4,865,044 9/1989 Wallace et al.
`..... .. 128/903
`4,870,304 9/1989 Bloker et al.
`307/465
`4,992,794 2/1991 Brouwers ............................ .. 342/51
`
`23 Claims, 7 Drawing Sheets
`
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`Luminex Ex. 1008
`Luminex/Irori - Page 1
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`Luminex Ex. 1008
`Luminex/Irori - Page 2
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`Luminex Ex. 1008
`Luminex/Irori - Page 3
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`

`
`US. Patent
`
`Oct. 12,1993
`
`Sheet 3 of 7
`
`5,252,962
`
`FIG: 3A
`
`15V
`
`/7 0/474
`
`Luminex Ex. 1008
`Luminex/Irori - Page 4
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`

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`Luminex Ex. 1008
`Luminex/Irori - Page 5
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`

`
`US. Patent
`
`0a. 12, 1993
`
`Sheet 5 of 7
`
`5,252,962
`
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`Luminex Ex. 1008
`Luminex/Irori - Page 6
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`

`
`U.S. Patent
`
`Oct. 12, 1993
`
`Sheet 6 of 7
`
`5,252,962
`
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`Luminex/Irori - Page 7
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`

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`US. Patent
`
`Oct. 12,1993
`
`Sheet 7 of 7
`
`5,252,962
`
`Luminex Ex. 1008
`Luminex/Irori - Page 8
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`

`
`1
`
`5,252,962
`2
`susceptible to background noise interference is pro
`vided by the instant invention.
`
`SYSTEM MONITORING PROGRAMMABLE
`IMPLANTABLE TRANSPONDER
`
`5
`
`20
`
`SUMMARY OF THE INVENTION
`Generally speaking, in accordance with the instant
`invention, a passive transponder which identi?es, simul
`taneously senses and transmits a condition to be sensed,
`such as the internal temperature or the like of an object
`is provided. The transponder includes a receive antenna
`for receiving the interrogator signal. The transponder is
`driven by the interrogator signal. A sensor circuit dis
`posed within the transponder measures the condition to
`be sensed of an animal in which the transponder is em
`bedded. A data sequencer receives the interrogation
`signal and enables the sensor circuit to output a signal
`representative of the condition to be sensed. The data
`sequencer causes the signal representive of the condi
`tion to be output over a transmit antenna contained
`within the transponder.
`In one embodiment of the invention, the transponder
`also includes a programmable memory circuit which
`may be programmed with a user selected identi?cation
`code through use of a signal received by the transpon
`der. The data sequencer enables both the sensor circuit
`to output the temperature and the programmable mem
`ory to output an identi?cation code in sequence. A
`frequency generator and modulator is provided for
`receiving the signal representative of the condition to
`be sensed and the identi?cation code and modulating
`the data to be output on an output carrier signal in
`response to the input signal. The output signal fre
`quency is independent of the input signal frequency
`which may be less than 10 KHz.
`I
`Accordingly, it is an object of the instant invention to
`provide an improved passive transponder.
`A further object of the invention is to provide a pas
`sive transponder which simultaneously senses and trans
`mits the internal temperature of an object or animal into
`which it has been injected.
`Another object of the invention is to provide a pro
`grammable passive transponder.
`A further object of the invention is to provide a tran
`sponder which outputs a signal having a frequency
`independent of the frequency of the received signal.
`Still another object of the invention is to provide a
`passive transponder in which the signal output by the
`transponder has a frequency greater than the frequency
`of the received signal.
`Yet another object of the instant invention is to pro
`vide a passive transponder which is energized in re
`sponse to interrogation signals having a frequency of
`less than 10 KHz.
`'
`Still other objects and advantages of the invention
`will in part be obvious and will in part be apparent from
`55
`‘ the speci?cation and drawings.
`The invention accordingly comprises the features of
`construction, a combination of elements and arrange
`ment of parts which will be exempli?ed in the construc
`tions hereinafter set forth and the scope of the invention
`will be indicated in the claims.
`
`BACKGROUND OF THE INVENTION
`This invention is directed to a passive transponder
`and, in particular, to a passive transponder which is
`programmable after completion of manufacture utilized
`for monitoring the characteristic of the host into which
`it is embedded, and more in particular for identifying an
`animal and its characteristics.
`Transponders and scanner systems are well known in
`the art. These systems include an interrogator which
`transmits and receives signals from a passive transpon
`der. One such use is a transponder embedded in an
`animal. The prior art system known from US. Pat. No.
`4,730,188 includes an antenna which transmits a 400
`KHz signal which is received by the transponder em
`bedded in the animal and returns a divided signal of 40
`KHz and 50 KHz. This signal is coded in accordance
`with a combination of 40 KB: and 50 KHz portions of
`the transmitted signal to correspond to a prepro
`grammed ID number stored in a chip contained within
`the passive transponder. The ID number is prepro
`25
`grammed at the time of manufacture. This ID number
`allows identi?cation of the animal in which the tran
`sponder is embedded. The scanner then inputs this
`coded ID number into a microcomputer for processing.
`The prior art transponders have been less than com
`pletely satisfactory because the amount of information
`which may be transmitted thereby was limited to the
`preprogrammed identi?cation numbers contained
`therein. Accordingly, in a contemplated use such as
`animal identi?cation, the user must use the prepro
`grammed identi?cation number to identify the test ani
`mal. However, identi?cation numbers are usually used
`as shorthand manner for presenting data concerning the
`animals. This requires that the user match his animal
`information to the preassigned transponder identi?ca
`tion number resulting in an increase of time and effort.
`Additionally, this prior art device is unable to automati
`cally transmit system status information, such as muscu
`lar pressure or temperature of the animal. Accordingly,
`the amount of information transmitted is quite small.
`Because the transponders divide the received signal, a
`high frequency received signal must be broadcast to the
`transponder so that the divided signal will have a high
`enough frequency to transmit information. These
`higher frequencies are regulated by the FCC, therefore,
`the amount of power which can be supplied to the tran
`sponder, and in turn the read distance is limited. Addi
`tionally, because the transponder transmit antenna oper
`ates at 40 KHz, it is subject to background noise inter
`ference from television monitoring screens or computer
`CRTs which by necessity are normally present since
`they are used in conjunction with microprocessors
`which are used during scanning. These monitors also
`operate utilizing a 40 KHz and 50 KHz RF signal. Be
`cause these monitors have a high power output relative
`to the antenna they interfere with the operation of the
`interrogator when the interrogator is used in proximity
`to computers and other various monitors.
`Therefore, a passive transponder which simulta
`neously senses an environmental condition and trans
`mits this information along with user programmable
`identi?cation information in a manner which is less
`
`60
`
`35
`
`45
`
`65
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`For a fuller understanding of the invention, reference
`is made to the following description taken in connection
`with the accompanying drawings, in which:
`FIG. 1 is a block diagram of an interrogator con
`structed in accordance with the invention;
`
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`

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`20
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`5,252,962
`4
`3
`regulator 5. Recti?er/regulator 5 receives the AC sig
`FIG. 2 is a block diagram of a passive transponder
`nal from the receive antenna and recti?es the signal.
`constructed in accordance with the invention;
`The unregulated voltage is then regulated to 3 volts to
`FIGS. 3a, 3b are respective halves of the frequency
`power the digital circuitry contained within transpon
`generator and modulator of FIG. 2 constructed in ac
`der 200. In an exemplary embodiment, recti?er/regula
`cordance with the invention;
`tor 5 utilizes Schottky diodes to reduce the voltage
`FIG. 4 is a circuit diagram for a data sequencer con
`drop. Recti?er/regulator 5 limits the voltage to protect
`structed in accordance with the invention;
`the digital electronics. The recti?ed signal is then
`FIG. 5 is circuit diagram of the one time programma
`passed through a frequency generator modulator 6 and
`ble memory constructed in accordance with the inven
`tion;
`input to a data sequencer 7 and manchester encoder and
`preamble generator 10.
`FIG. 6 ,is a side elevation view of a transponder
`Data sequencer 7 receives as inputs the 7109 H2 sig
`constructed in accordance with the invention;
`nals, temperature data from a temperature to frequency
`FIG. 7 is a top plan view of a transponder con
`structed in accordance with the invention;
`converter 8 and the programmed ID data from one time
`programmable memory 9 and controls the sequencing
`FIG. 8 is a sectional view taken along line 8—8 of
`FIG. 7; and
`of the cyclical transmitted data stream which includes
`the preamble, ID data and temperature data. A one time
`FIG. 9 is a sectional view taken along line 9-9 of
`programmable memory 9 stores the ID data therein.
`FIG. 7.
`When data sequencer 7 receives the 7109 Hz input sig
`DETAILED DESCRIPTION OF THE
`nal, it ?rst outputs a preamble enable signal causing
`PREFERRED EMBODIMENTS
`manchester encoder and preamble generator 10 to out
`put a data preamble. It then outputs the ID data stored
`Reference is ?rst made to FIGS. 1 and 2 in which
`block diagrams of an exciter/receiver (“interrogator”)
`in one time programmable memory 9. Data sequencer 7
`100 and implantable passive transponder (“transpon
`sequentially accesses the address to be read from mem
`der”) 200 are provided. Interrogator 100 transmits an
`ory 9 through address bus 202 this causes memory 9 to
`exciter signal to transponder 200. The exciter signal is
`output the data to data sequencer 7 which gates the data
`received by transponder 200 and powers transponder
`and outputs the ID data at the appropriate time to man
`chester encoder and preamble generator 10.
`200. Once energized, transponder 200 is caused to out
`put a data signal. This data signal includes a preamble
`Reference is now made to FIG. 4 in which a circuit
`diagram of data sequencer 7 is presented. Data se
`portion, temperature data and identi?cation code. The
`30
`data signal is a PSK (phase shift keyed) signal with a 455
`quencer 7 includes a counter 700 which receives the
`7109 Hz signal, divides by 16 and outputs a 444 Hz
`KHz carrier frequency. The transmission is a continu
`ous, cyclic data stream containing the transponder ID
`signal. One time programmable memory 9 outputs a
`program inhibit signal indicative of whether the mem
`and temperature information. This information is re
`ceived by interrogator 100 and is demodulated, trans
`ory has been programmed by the user with an ID data.
`lated and input to a host computer for processing.
`The program inhibit signal has a value of 0 if the mem
`ory has already been programmed and a value of 1 if it
`As will be described in greater detail below, tran
`has not been programmed. A ?rst NAND gate 704
`sponder 200 includes a one time programmable memory
`receives the 7109 Hz signal output by frequency genera
`9. Programmer 100 which is coupled to a host computer
`tor and modulator 6 as a ?rst input and the inverted
`receives an identi?cation code that is to be programmed
`40
`into transponder 200. Interrogator 100 modulates the
`program inhibit signal as a second input. A second
`amplitude of the excitation signal to communicate with
`NAND gate 706 receives the 444 Hz clock signal and
`the program inhibit signal as inputs. The outputs of both
`transponder 200. When transponder 200 is in a program
`NAND gate 704, 706 are input to a third NAND gate
`mode one time programmable memory 9 may be pro
`grammed by interrogator 100.
`708 which gates each of the outputs and produces a
`clock signal having a value of either 444 Hz or 7109 Hz
`In an exemplary embodiment, interrogator 100 com
`municates with transponder 200 through inductive cou
`as an output.
`'
`A binary counter 710 receives the output of NAND
`pling known in the art from US. Pat. No. 4,730,188,
`gate 708 and utilizes this signal as the internal timing
`which patent is incorporated herein by reference as if
`fully set forth herein. The interrogation signal is less
`signal. Binary counter 710 provides a data clock at its
`output Q1 of 3555 Hz when a signal of 7109 Hz is re
`than 10 KHz and more precisely 7109 Hz. The return
`ceived. Binary counter 710 also sequentially accesses
`data stream output by the transponder is output on a
`higher frequency carrier signal of 455 KHZ.
`the addresses within programmable memory 9 through
`A more detailed description of the invention is now
`the address bus at this clock rate.
`provided. Description is made of the system in which
`During the reading of data from memory 9, the ac
`55
`transponder 200 already has been programmed and a
`' cessing of each memory causes ID data to be output by
`memory 9. This data is then input to a clock 718 which
`user selected identi?cation code has been stored in one
`time programmable memory 9. Interrogator 100 in
`receives as a clock input the 3555 Hz data clock output
`by binary counter 710. This is to synchronize the data
`cludes a frequency generator 1 which outputs a 7109 Hz
`being output by memory 9 with the transmit sequence
`signal. A power amp 2 receives the output signal and
`as represented by the data clock.
`causes the signal to flow through the primary coil of a
`A NAND gate 714 and a NAND 716 are provided to
`transmit antenna 3 which generates an excitation ?eld at
`gate the transmission of the preamble, ID data and tem
`a frequency of 7109 Hz from exciter 100.
`perature data portions of the cyclical transmitted data
`Reference is now made speci?cally to FIG. 2 in con
`nection with describing the internal con?guration of
`stream. NAND gate 714 receives the output of Q8 as
`65
`one of its inputs and the output of Q9 as its other and
`transponder 200. A receive antenna 4 mounted within
`outputs the preamble enable signal. NAND gate 716
`transponder 200 receives the exciter signal from interro
`receives the inverted output of Q8 and the output of Q9
`gator 100 and inputs a 7109 Hz signal to a recti?er/
`
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`5,252,962
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`signal of 7109 Hz. Frequency generator and modulator
`and outputs the temperature enable signal so that the
`6 multiplies the input clock signal by 64 to produce a
`two NAND gates will not enable the transmission of the
`respective data simultaneously. Additionally, a NAND
`transmit carrier frequency of 455 KHz to output a 455
`gate 720 utilizes the preamble enable signal to gate the
`KHz carrier signal containing the data. This carrier
`temperature data being produced by temperature to
`signal is phase shifted by 180° when the transmitted data
`frequency converter 8 so that when the preamble enable
`changes state to output a phase shift keyed signal.
`is low, the temperature waveform is blocked.
`Reference is now made to FIG. 3a and 3b, wherein a
`During the read operation, the program inhibit signal
`circuit diagram of frequency generator and modulator 6
`has a low value, therefore, its inverted signal is high.
`is provided. The circuit shown in FIG. 30 operates
`Because one input of NAND gate 706 is 0 (the program
`digitally on the received 7109 Hz signal and provides an
`inhibit value), it will continuously produce a high out
`input to an analog portion of the circuit shown in FIG.
`3b. The frequency generator and modulator multiplies
`put. Whereas the inputs of NAND gate 704 are a con
`tinuously high signal and the oscillating waveform sig
`the frequency of the received clock (7109 Hz) to pro
`nal of the received 7109 Hz signal, the output of NAND
`duce a 455 KHz carrier signal by comparing an internal
`digitally controlled oscillator with the period of one
`_ gate 708 will be a 7109 Hz clock signal. Binary counter
`cycle of the received clock signal.
`710 utilizes this signal producing a data clock of 3555
`An analog oscillator is provided having a capacitor
`Hz and a read out rate of 3555 Hz.
`649 which is charged by a combination of voltage
`In an exemplary embodiment, if the output of Q9 is
`low the preamble data is output and then the program
`sources 630, 634, 638, 642 and 646 having values of i, 21',
`ID data. Once the value of Q9 goes high, the preamble
`4i, 8:’ and 641‘ respectively. The current is input to capac
`enable goes high allowing the temperature data to be
`itor 649 to charge. Capacitor 649 is coupled to inverters
`transmitted through NAND gate 720. During the time
`648, 650 arranged in series. The output of inverter 650 is
`Q9 goes high, the EPROM of memory 9 is still se
`input to a MOSFET transistor 652 for discharging ca
`pacitor 649. This continuous charge and discharge pro
`quenced. However, the ID data is not output by the
`manchester encoder and preamble generator 10.
`vides an oscillator of a certain frequency. The rate of
`To obtain the temperature data portion of the output
`oscillation is based on the current sources so that the
`signal, a chip thermistor 19 is provided which outputs a
`amount of charge stored in capacitor 649 as a function
`resistance in response to changes in temperature. The
`of the amount of current and then discharged by transis
`tor 652 causes oscillations within the circuit producing
`resistance is input to temperature to frequency con- >
`pulses at about 910 KHz. In an exemplary embodiment
`verter 8 which converts the resistance to a frequency
`30
`which is input to data sequencer 7. In an exemplary
`capacitor 649 has a value of 10 pF.
`embodiment, temperature to frequency converter 8 is
`The 910 KHz signal is input to a divide by 256 circuit
`an RC oscillator that is controlled by the resistance of
`which includes NAND gate 610 and two binary count
`thermistor 19. The frequency of the oscillator increases
`ers 608, 612. The 910 KHz signal is input into binary
`with temperature. The oscillator has an approximate
`counter 608 and is also one input of NAND gate 610.
`frequency of 160 KHZ at 36° C. Data sequencer 7 gates
`The second input of NAND gate 610 is the divided
`this frequency and outputs the signal to manchester
`output Q3 of binary counter 608. The output of NAND
`encoder and preamble generator 10 at the appropriate
`gate 610 is input as the clock input of binary counter 612
`time allowing manchester encoder and preamble gener
`so that the output Q3 is a signal having a frequency of
`about 3554.68 Hz.
`ator 10 to output a cyclically transmitted data stream
`which includes the preamble, ID data and tem
`At the same time, the received 7109 Hz signal is re
`perature/frequency data.
`ceived by frequency generator and modulator 6 and is
`Manchester encoder and preamble generator 10 re
`inverted by an inverter 602. The inverted received sig
`ceives the 7109 Hz signal and responds to the preamble
`nal is input to a ?ip ?op 604 as the clock input. Flip ?op
`enable, temperature enable signals, data out and data
`604 is a divide by 2 so that its Q output is a signal having
`clock signal produced by data sequencer 7. When the
`a frequency of about 3554.5 Hz. This signal is asynchro
`preamble enable signal produced by data sequencer 7 is
`nous with the 3554.68 signal of the divide by 256 circuit.
`high it encodes the data being transmitted by data se
`A NOR gate 618 receives the two signals as does a
`NAND gate 616. A comparison is made between the
`quencer 7. The 7109 Hz clock is selected as the man
`chester clock and the data out signal is always high
`two signals to determine which occurs ?rst and adjust
`producing an output twice the normal data clock fre
`ments are made.
`quency. This allows a simple means of detecting the
`To prevent toggling back and forth between one
`beginning of the cyclical data sequence. In a ?rst stage,
`coming before the other at NAND gate 616, a delay
`circuit is provided. The delay circuit includes the ?ip
`the manchester clock is mixed with the ID data to pro
`?op 606 providing an input to the flip flop 620. Flip ?op
`duce manchester encoded preamble and ID data signal.
`In a next step, when the temperature enable signal is
`606 receives the 910 KHz signal as the clock input and
`high, the manchester encoder and preamble generator
`provides a Q output to flip ?op 620 received at the D
`input of ?ip ?op 620. Flip ?op 620 again clocks this
`10 replaces the manchester encoded ID data with the
`temperature data completing one cycle of data transmis
`signal with the 910 KHz pulses of the oscillating clock
`formed about capacitor 649. This delays the output of
`sion. This data is transmitted at 3555 baud to frequency
`generator and modulator 6. By way of example, the
`?ip ?op 620 by at least one cycle of the 910 KHz pulse
`signal.
`preamble, ID data and temperature data are produced
`in this order. However, as the entire output signal is
`A pair of NAND gates 624, 626 are provided. The
`output Q of ?ip ?op 604 representing the divided down
`continuous and cyclical, the temperature data may be
`output ?rst.
`received signal having the 3554.5 Hz frequency is input
`Frequency generator and modulator 6 receives the
`to both NAND gates 624, 626 'as is the delay Q output
`data to be transmitted from manchester encoding and
`of ?ip flop 620. However, NAND gate 624 receives the
`inverted output of the divide by 256 circuit (the 3554.68
`preamble generator 10 as well as the received clock
`
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`8
`7
`Hz signal) while NAND 626 receives the actual signal
`current sources to the capacitor. If the received clock
`cycle is longer, then the oscillator frequency is too high
`itself. The outputs of NAND gate 624, 626 control are
`and a down pulse is generated and output to the up
`input to an updown counter 628. The outputs QA-QD
`of updown counter 628 control the amount of current
`down counter.
`-
`The phase shift keyed data is output through rec
`?owing from each current source through switches 632,
`636, 640, 644 respectively to the capacitors 649.
`ti?er/regulator and a transmit antenna 11. A 455 KB;
`?eld is produced which is received by receive antenna
`The relative outputs of NAND gates 624, 626 control
`12 of interrogator 100.
`whether the amount of current fed to capacitor 649
`The received signal is input into an impedance buffer
`should be increased or decreased thus affecting the
`frequency of the pulses produced. This is a delayed
`13 which buffers the high impedance of the tuned re
`ceive coil forming receive antenna 12 so that the much
`function so that no matter which signal, the divided
`lower impedance of the receive ?lter does not reduce
`receive signal or the divided oscillator signal goes high
`the received signal strength. The impedance matched
`?rst it will be delayed before the gates 624, 626 are able
`signal is an input to a receive ?ltering and ampli?cation
`to determine whether the count of up down counter 628
`circuit 14. Receive ?lter ampli?cation circuit 14 ?lters
`should go up or down. If the output Q of ?ip ?op 604
`out unwanted signals and ampli?es the received signal
`goes high ?rst, it is delayed by ?ip ?ops 606, 620. If at
`for further processing.
`the same time the output at Q3 of binary counter 612 is
`In an exemplary embodiment, receive ?ltering and
`low, the input of NAND gate 624 would be high while
`ampli?cation circuit 14 uses a multiple pole ceramic
`the input of NAND gate 626 would be low. The output
`band pass ?lter with a +/—-l5 KHz pass bandwidth
`of NAND gate 624 would cause an up pulse at counter
`and 60 dB attenuation in the stop band to ?lter out
`628.
`unwanted signals. The signal is then ampli?ed with a
`The counting of ?ip ?ops 608, 612 are controlled by
`?ip ?op 614 which receives the Q output of ?ip ?op 604
`gain of 40 dB. The circuit is shielded and the power
`supply are isolated to keep external electromagnetic
`as its clear. Flip ?op 614 in turn controls the resetting of
`in?uences from corrupting the received signal.
`?ip ?ops 608, 612 and thereby controls the output of the
`divide by 256 circuit. Additionally, the clock input of
`The ampli?ed received signals are then input to a
`mixer and phase locked loop 15. The mixer receives the
`?ip ?op 614 is the output of AND gate 616. If the out
`put Q3 is l, the Q output of ?ip ?op 614 goes high
`received signal with a 410 KHz signal to produce a base
`band received signal at 45 KHz. The phase locked loop
`causing output Q3 of ?ip ?op 612 to go low again re
`produces a positive pulse with every 180° phase shift of
`starting the whole process. Counting can only occur
`when the Q output of ?ip ?op 604 is low.
`the received signal. These pulses are then input to a
`If it is determined by NAND gates 624, 626 that
`micro-controller 16 where the received ID data is re
`constructed and the temperature dependent frequency
`pulses are not being output at 910 KHz corrections are
`forming part of the output data stream from transpon
`made by updown counter 628. Switches 632, 636, 640,
`der 200 is detected and analyzed.
`644 are analog switches which allow the current from
`Micro-controller 16 reconstructs the ID data portion
`the respective current source 630, 634, 638, 642 to be
`of the received signal and temperature information from
`output to the capacitor 649 to charge it up at a faster
`the frequency pulses output by temperature to fre
`rate thereby increasing the frequency of pulses. As the
`quency converter 8. Microcontroller 16 outputs data
`need for an increased frequency arises, the number of
`and appropriate protocol signals which may include a
`switches 632, 636 and the like which will be turned on
`ready to send signal indicating that the data is about to
`to allow current to pass to capacitor 649 increases se
`quentially until the frequency of the pulses is sufficient.
`be sent, the transmitted data is then sent in serial fashion
`A divide by 2 ?ip ?op 654 receives the 9l0 KHz pulse
`to an RS 232 interface 17 which converts the data from
`digital levels to RS 232 levels. This converted informa
`as a clock signal and outputs as a Q output a 455 KHz
`signal. The 455 KHz signal is the carrier frequency for
`tion is then passed through a connector 18 to the host
`45
`the data which is transmitted by transponder 200. An
`computer at which the data is to be processed.
`exclusive OR gate 656 receives the 455 KHz signal and
`. By providing a passive transponder which contains a
`chip thermistor and, a temperature frequency con
`the data to be transmitted including the preamble, ID
`verter, it becomes possible to monitor the temperature
`data and temperature data as a second input. The exclu
`sive OR gate shifts the phase of the carrier signal by
`of the animal in which the transponder has been im
`planted. Temperature is utilized merely by way of ex
`180“ in response to the data so that a phase shift keyed
`data output signal is produced by exclusive OR gate
`ample. Through use of a data sequencer as described
`656. This phase shift keyed signal is then transmitted to
`above, other system status characteristics, such as mus
`interrogator 100 where it is operated upon.
`cular pressure, light levels or other ?uid conditions may
`By multiplying the received clock by 64, a transmit
`55
`_ be continuously monitored and transmitted to a remote
`host computer. Additionally, by providing a frequency
`carrier frequency of 455 KHz is obtained. By digitally
`comparing the period of 64 cycles of the internal digi
`multiplier within the transponder it becomes possible to
`tally controlled oscillator with the period of one cycle
`use an interrogation signal of less than 10 KHz, a non
`FCC regulated frequency, making it possible to increase
`of the received clock, a‘ very inaccurate frequency
`the power utilized to send this signal thus allowing
`source can be synchronized with a very accurate fre
`increased read distances between the inductively cou
`quency source to produce an accurate carrier frequency
`pled interrogator and transponder. Further, by utilizing
`at a much higher frequency without imposing limits on
`a frequency generator and modulator in which an inter
`the frequency values. As disclosed above, this is accom
`nal digitally controlled time period is compared with
`plished by determining whether the received clock
`cycle is shorter or longer than the 64 cycles of the oscil
`one cycle of the received clock and operated thereon, a
`very inaccurate frequency source, the internally gener
`lator. If the received clock cycle is shorter, then the
`oscillator frequency is too low and a up pulse will be
`ated oscillator clock, can be synchronized with a very
`generated output to an updown counter controlling the
`accurate frequency source, the received signal, to pro
`
`60
`
`65
`
`35
`
`50
`
`Luminex Ex. 1008
`Luminex/Irori - Page 12
`
`

`
`5,252,962
`9
`10
`of the enable gates and the temperature gates are identi
`duce an accurate frequency source at a much higher
`frequency which is more suitable for transmitting the
`cat] as that described above.
`more complex transmit data stream of the transponder.
`When the last address of the one time programmable
`memory 9 is programmed, the value is changed from 1
`to 0. This causes the program inhibit signal which is
`output to change the internal clock of data sequencer 7
`from the 444 Hz rate to the 7109 Hz rate. Accordingly,
`during the next interrogation by interrogator 100, inter
`rogator 100 determines that it should not program tran
`sponder 200 based upon this new received PSK data
`rate.
`