United States
`
`US 200401l0390A1
`
`Patent Application Publication (10) Pub. N0.: US 2004/0110390 A1
`Takagi et al.
`(43) Pub. Date:
`Jun. 10, 2004
`
`SEMICONDUCTOR MEMORY DEVICE AND
`METHOD OF FABRICATING THE SAME
`
`(30)
`
`Foreign Application Priority Data
`
`(19)
`
`(12)
`
`(54)
`
`(75)
`
`Inventors: Hideo Takagi, Aizuwakamatsu (JP);
`Takayuki Enda, Ajzuwakamatsu (JP);
`Miyuki Umetsu, Aizuwakamatsu (JP);
`Tsukasa Takammsu’ Aizuwakamatsu
`(JP)
`
`Correspondence Address:
`WESTERMAN, HATTORI, DANIELS &
`ADRIAN, LLP
`1250 CONNECTICUT AVENUE, NW
`SUITE 700
`WASHINGTON, DC 20036 (US)
`
`(73)
`
`Assignee: FASL LLC, Sunnyvale, CA
`
`(21)
`
`Appl, No;
`
`10/714,909
`
`(22)
`
`Filed:
`
`Nov. 18, 2003
`
`(CORE AREA)
`
`Dec. 6, 2002
`
`(JP) .................................... .. 2002-355933
`
`Publication Classification
`
`_
`I
`Int. Cl.7 .............................................. .. H01L 21/4763
`(51)
`(52) U.s. Cl.
`....................... .. 438/710; 438/639; 438/724;
`438/723
`
`ABSTRACT
`(57)
`_
`_
`_
`_
`_
`_
`_
`A silicon nitride film for storing electric charge 1S formed on
`a semiconductor substrate While placing a tunnel oxide film
`in between, and the silicon nitride film is then subjected to
`hydrogen plasma treatment so as to effectively erase unnec-
`essary charge stored therein during various process steps in
`fabrication of the semiconductor memory device, to thereby
`stabilize the threshold voltage (Vth) of the semiconductor
`memory device.
`
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`
`

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`Patent Application Publication
`
`Jun. 10, 2004 Sheet 1 of 7
`
`US 2004/0110390 A1
`
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`
`

`
`Patent Application Publication
`
`Jun. 10, 2004 Sheet 2 of 7
`
`US 2004/0110390 A1
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`
`

`
`Patent Application Publication
`
`Jun. 10, 2004 Sheet 3 of 7
`
`US 2004/0110390 A1
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`

`
`Patent Application Publication
`
`Jun. 10, 2004 Sheet 4 of 7
`
`US 2004/0110390 A1
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`

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`Patent Application Publication
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`Jun. 10, 2004 Sheet 5 of 7
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`US 2004/0110390 A1
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`
`

`
`Patent Application Publication
`
`Jun. 10, 2004 Sheet 6 of 7
`
`US 2004/0110390 A1
`
`FIG. 6A
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`

`
`US 2004/0110390 A1
`
`Jun. 10, 2004
`
`SEMICONDUCTOR MEMORY DEVICE AND
`METHOD OF FABRICATING THE SAME
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`[0001] This application is based upon and claims the
`benefit of priority from the prior Japanese Patent Application
`No. 2002-355933, filed on Dec. 6, 2002, the entire contents
`of which are incorporated herein by reference.
`
`BACKGROUND OF THE INVENTION
`
`which comprises the steps of forming a charge storage film
`for storing electric ch arge; and erasing electric ch arge stored
`in the charge storage film by subjecting the charge storage
`film to hydrogen annealing after the formation thereof.
`
`[0012] Still another aspect of the present invention relates
`to a semiconductor memory device such that having a charge
`storage film for storing electric charge, and having,
`in
`addition to a first contact hole used for wiring connection, a
`second contact hole not used for wiring connection but used
`for facilitating diffusion of hydrogen radicals or hydrogen
`molecules into said charge storage film.
`
`[0002]
`
`1. Field of the Invention
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0003] The present invention relates to a semiconductor
`memory device and a method for fabricating the same, and
`in particular such that being preferably applicable to those
`having a charge storage film for storing electric charge.
`
`[0004]
`
`2. Description of the Related Art
`
`[0005] Any semiconductor memory device storing data by
`storing electric charge has a charge storage film for storing
`the charge, and writes or erases data by varying threshold
`voltage (Vth) of the memory cell transistor depending on the
`amount of charge stored in the charge storage film.
`
`[0006] The aforementioned writing or erasure of data in,
`for example, a SONOS (semiconductor/oxide film/nitride
`film/oxide
`film/semiconductor)-type
`semiconductor
`memory device is effected by generating a potential differ-
`ence between a gate electrode (word line) of a selected
`memory cell and a semiconductor substrate (bit line), and
`then by injecting hot electrons into the charge storage film,
`or by injecting holes based on band-to-band tunneling.
`
`fabrication of the semiconductor
`[0007] Conventional
`memory device has, however, been suffering from a problem
`that the charge storage film was likely to store unnecessary
`charge during various process steps in the fabrication. This
`resulted in generation of error or variation of charge to be
`stored in the charge storage film when the semiconductor
`memory device is operated for writing or erasure, which
`undesirably varied the threshold voltage and prevented the
`device from being stably operated.
`
`[0008] The present invention is accomplished considering
`the aforementioned problem, and is to provide a semicon-
`ductor memory device and a method of fabricating the
`device, both of which being aimed at avoiding storing of
`unnecessary charge into the charge storage film, and thus
`stabilizing the threshold voltage.
`
`SUMMARY OF THE INVENTION
`
`reached the following
`inventors
`[0009] The present
`aspects of the present invention after extensive investiga-
`tions.
`
`[0010] One aspect of the present invention relates to a
`method of fabricating a semiconductor memory device
`which comprises the steps of forming a charge storage film
`for storing electric charge; and erasing electric charge stored
`in the charge storage film by subjecting the charge storage
`film to hydrogen plasma treatment after the formation
`thereof.
`
`[0011] Another aspect of the present invention relates to a
`method of fabricating a semiconductor memory device
`
`[0013] FIGS. 1A through 1D are schematic sectional
`views sequentially showing process steps of a method of
`fabricating a SONOS-type semiconductor memory device
`according to an embodiment of the present invention;
`
`[0014] FIGS. 2A through 2D are schematic sectional
`views sequentially showing process steps as continued from
`FIG. 1D;
`
`[0015] FIGS. 3A through 3C are schematic sectional
`views sequentially showing process steps as continued from
`FIG. 2D;
`
`[0016] FIGS. 4A and 4B are schematic views of a core
`portion of the SONOS-type semiconductor memory device,
`previously shown in FIG. 3C, according to an embodiment
`of the present invention;
`
`[0017] FIGS. 5A and 5B are schematic views of the core
`portion of the SONOS-type semiconductor memory device
`obtained by the method of fabricating the SONOS-type
`semiconductor memory device in the embodiment of the
`present invention, as continued from FIGS. 4A and 4B;
`
`[0018] FIGS. 6A and 6B are schematic sectional views
`sequentially showing process steps of the method of fabri-
`cating the SONOS-type semiconductor memory device
`according to the embodiment of the present invention, as
`continued from FIGS. 5A and 5B; and
`
`[0019] FIG. 7 is a schematic diagram of the threshold
`voltage (Vth) of the SONOS transistor.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`[0020] Basic Concept of the Present Invention
`
`In the field of fabricating semiconductor memory
`[0021]
`devices, hydrogen plasma treatment is typically carried out
`after contact holes for establishing wiring contact are
`formed, in order to remove foreign matters such as carbon
`contained in a barrier layer, which are derived from TDMAT
`(Tetrakis dimethylamino titanium) used as a source gas for
`forming the barrier layer by the CVD process. Removal of
`such foreign matters can be accomplished by hydrogen
`plasma treatment within 35 seconds or around.
`
`[0022] On the other hand, conventional fabrication of the
`semiconductor memory device has been sulfering from a
`problem that, once the charge storage film for storing
`electric charge was formed,
`the film was likely to store
`unnecessary charge during various process steps thereafter
`in the fabrication, which resulted in error or variation in the
`threshold voltage. The storing of unnecessary charge into the
`
`|PR2014-00898
`(cid:44)(cid:51)(cid:53)(cid:21)(cid:19)(cid:20)(cid:23)(cid:16)(cid:19)(cid:19)(cid:27)(cid:28)(cid:27)(cid:3)
`Exhibit MX027||-1015, p. 9
`(cid:40)(cid:91)(cid:75)(cid:76)(cid:69)(cid:76)(cid:87)(cid:3)(cid:48)(cid:59)(cid:19)(cid:21)(cid:26)(cid:44)(cid:44)(cid:16)(cid:20)(cid:19)(cid:20)(cid:24)(cid:15)(cid:3)(cid:83)(cid:17)(cid:3)(cid:28)
`
`

`
`US 2004/0110390 Al
`
`Jun. 10, 2004
`
`charge storage film is, however, unavoidable in the fabrica-
`tion process, and thus only possible way was to erase the
`unnecessary charge already being stored into the film. After
`thorough considerations for addressing the problem,
`the
`present inventors reached the present invention described
`below.
`
`[0023] The present invention is designed so as to form the
`charge storage film, subject
`the charge storage film to
`hydrogen plasma treatment for a predetermined duration of
`time, to thereby allow hydrogen radicals to diffuse into the
`film, with which the stored unnecessary charge (negative
`charge) is cancelled. Carrying-out of the hydrogen plasma
`treatment after the contact holes are formed will be advan-
`
`tageous since the unnecessary charge in the charge storage
`film can be removed without causing any increase in the
`number of process steps.
`
`[0024] The hydrogen plasma treatment for removing the
`unnecessary charge in the charge storage film is by no means
`achievable by the aforementioned short-term hydrogen
`plasma treatment for removing impurities such as carbon,
`due to special feature of the process whereby the stored
`unnecessary charge in the charge storage film must be
`erased. Our experimental results on the threshold voltage
`characteristics, which will be described later, revealed that
`the purpose of erasing the unnecessary charge in the charge
`storage film would never be achieved unless the hydrogen
`plasma treatment would be continued at least for 40 seconds,
`for the case where the erasure was to be elfected through a
`titanium nitride film (CVD-TiN film) of 5 nm thick. We
`have, on the other hand, reached a conclusion that it was
`appropriate to finish the treatment within 90 seconds from
`the viewpoint of throughput in fabrication of the semicon-
`ductor memory device. Based on the discussion in the
`above, we concluded that a duration of time of 40 to 90
`seconds was optimum for the hydrogen plasma treatment
`while taking both goals into account, that are, erasure of the
`unnecessary charge stored in the charge storage film, and
`assurance of a practical throughput in the fabrication pro-
`cess.
`
`[0025] As for a process in which the unnecessary charge
`stored in the charge storage film is erased by hydrogen
`annealing in place of hydrogen plasma treatment, we con-
`cluded that an optimum duration of time is 30 to 90 minutes
`while taking both goals into account, that are, erasure of the
`unnecessary charge stored in the charge storage film, and
`assurance of a practical throughput in the fabrication pro-
`cess.
`
`[0026] As described in the above, the present invention is
`to provide a method capable of preventing the charge storage
`film from being stored with unnecessary charge, and of thus
`stabilizing the threshold voltage without causing any
`increase in the number of process steps in the fabrication, by
`making use of hydrogen plasma treatment (or hydrogen
`annealing) under well-adjusted conditions.
`
`[0027] Specific Embodiments Applied with the Present
`Invention
`
`[0028] Next, specific embodiments of the present inven-
`tion will be described referring to the attached drawings,
`which is an adaptation of the above-described basic concepts
`on the semiconductor memory device and the method of
`fabricating the same. In the present embodiment, a buried-
`
`bit-line-type SONOS semiconductor memory device is dis-
`closed as one example of the semiconductor memory device.
`Design of the semiconductor memory device employs pla-
`nar-type SONOS transistors in the memory cell area (core
`area), and CMOS transistors in the peripheral circuit area.
`
`[0029] FIGS. 1A to 6B are schematic views sequentially
`showing process steps of a method of fabricating a semi-
`conductor memory device containing the buried-bit-line-
`type SONOS transistors of the present embodiment.
`In
`FIGS. 1A to 3C, the left halves show sectional views of the
`core area taken in parallel to a gate electrode (a word line),
`and right halves show those of the peripheral circuit area.
`
`First, as shown in FIG. 1A, a semiconductor
`[0030]
`substrate 1 comprising a p—type silicon (Si) is thermally
`oxidized to thereby form a silicon oxide (SiO2) film 11 of
`approx. 20 nm thick. A resist pattern 31 is formed by
`photolithography so as to expose an area for forming tran-
`sistors in the peripheral circuit area, phosphorus (P) ion is
`implanted over the entire surface, and the impurity is ther-
`mally diffused by annealing to thereby form an N-well 2.
`The resist pattern 31 is then removed typically by ashing
`using ()2 plasma.
`
`[0031] Next, as shown in FIG. 1B, a resist pattern 32 is
`formed by photolithography so as to expose an area for
`forming an NMOS transistor in the peripheral circuit area,
`boron (B) ion is implanted over the entire surface, and the
`impurity is thermally diffused by annealing to thereby form
`a P-well 3, where a triple-well structure is obtained in the
`NMOS transistor formable area. The resist pattern 32 is then
`removed typically by ashing using 02 plasma.
`
`[0032] Next, a silicon nitride film 12 of approx. 100 nm
`thick is deposited on the silicon oxide film 11 by the CVD
`process. A resist pattern 33 is then formed by photolithog-
`raphy so as to be opened corresponding to areas where
`element isolation regions are to be formed, and the silicon
`nitride film 12 is dry-etched so as to be opened correspond-
`ing to areas where element
`isolation regions are to be
`formed, as shown in FIG. 1C. The resist pattern 33 is then
`removed typically by ashing using 02 plasma.
`
`[0033] Next, as shown in FIG. ID, a thick silicon oxide
`film 13 is formed by so-called LOCOS process only in the
`areas not covered with the silicon nitride film 12, to thereby
`partition the element active region. The silicon nitride film
`12 is then removed by dry etching.
`
`[0034] Next, as shown in FIG. 2A, 2| resist pattern 34
`having a bit-line pattern is formed by photolithography,
`arsenic
`ion is implanted over the entire surface under
`masking by the resist pattern 34, and the impurity is ther-
`mally diffused by annealing to thereby form a bit-line,
`impurity-diffused layer 4 which is used in common with
`source-and-drain region, in the core area. The resist pattern
`34 is then removed typically by ashing using 02 plasma.
`
`[0035] Next, as shown in FIG. 2B, the silicon oxide film
`11 is removed by wet etching using hydrofluoric acid (HF),
`to thereby expose the surface of the semiconductor substrate
`1 in the core area and the element active regions in the
`peripheral circuit area.
`
`[0036] Next, as shown FIG. 2C, a tunnel oxide film
`(silicon oxide film) 14 of approx. 7 nm thick is formed by
`thermal oxidation, a silicon nitride film 15 of approx. 10 nm
`
`|PR2014-00898
`(cid:44)(cid:51)(cid:53)(cid:21)(cid:19)(cid:20)(cid:23)(cid:16)(cid:19)(cid:19)(cid:27)(cid:28)(cid:27)(cid:3)
`Exhibit MX027||-1015, p. 10
`(cid:40)(cid:91)(cid:75)(cid:76)(cid:69)(cid:76)(cid:87)(cid:3)(cid:48)(cid:59)(cid:19)(cid:21)(cid:26)(cid:44)(cid:44)(cid:16)(cid:20)(cid:19)(cid:20)(cid:24)(cid:15)(cid:3)(cid:83)(cid:17)(cid:3)(cid:20)(cid:19)
`
`

`
`US 2004/0110390 A1
`
`Jun. 10, 2004
`
`thick is formed on the tunnel oxide film 14 by the CVD
`process, and a silicon oxide film 16 of approx. 7 nm thick is
`formed on the silicon nitride film 15 by the CVD process.
`This completes an ONO film 100 which comprises three
`films of the tunnel oxide film 14, silicon nitride film 15, and
`silicon oxide film 16. The silicon nitride film 15 herein
`
`functions as a charge storage film for storing electric charge
`in the semiconductor memory device.
`
`[0037] Next, as shown in FIG. 2D, a resist pattern 35 is
`formed by photolithography so as to expose the peripheral
`circuit area, and the ONO film 100 in the peripheral circuit
`area is removed by dry etching. The resist pattern 35 is then
`removed typically by ashing using O2 plasma.
`
`[0038] Next, the surface of the semiconductor substrate 1
`is heated at a temperature as high as 1,000° C. so as to form
`a silicon oxide film (SiO2 film) of approx. 8 nm thick, as
`shown in FIG. 3A. An unshown resist pattern is then formed
`so as to be opened in the area for forming a PMOS transistor
`in the peripheral circuit area, and the silicon oxide film in the
`PMOS transistor formable area is removed by wet etching
`using hydrofluoric acid
`The u11shown resist pattern is
`then removed typically by ashing using O2 plasma, and the
`surface of the semiconductor substrate 1 is again heated at
`a temperature as high as 1,000° C. so as to form a silicon
`oxide film (SiO2 film) of approx. 10 nm thick, to thereby
`form two different gate insulating films, that are, a gate
`insulating film 17a of approx. 10 nm thick in the PMOS
`transistor formable area and a gate insulating film 17b of
`approx. 13 nm thick in the NMOS transistor formable area.
`
`[0039] Next, as shown in FIG. 3B, :1 polysilicon film 18
`of approx. 100 nm thick is deposited by the CVD process in
`the core area and peripheral circuit area. Further on the
`polysilicon film 18, a tungsten silicide film 19 of approx. 150
`nm thick is formed by the CVD process.
`
`[0040] Next, as shown in FIG. 3C, the tungsten silicide
`film 19 and polysilicon film 18 are patterned by photoli-
`thography and succeeding dry etching, to thereby form gate
`electrodes comprising the tungsten silicide film 19 and
`polysilicon film 18 respectively in the core area, and in the
`PMOS transistor formable area and NMOS transistor form-
`able area of the peripheral circuit area. The gate electrode
`herein in the core area is formed so as to cross with the
`bit-line, impurity-diffused layer 4 nearly at right angles.
`
`[0041] LDD-structured source-and-drain regions 20, 21
`are then formed only in the peripheral circuit area.
`
`[0042] More specifically, in the PMOS formable area, a
`p-type impurity ion is implanted into the surficial area of the
`semiconductor substrate 1 on both sides of the gate elec-
`trode, to thereby form an extension regions 22. On the other
`hand, in the NMOS formable area, an n-type impurity ion is
`implanted into the surficial area of the semiconductor sub-
`strate 1 on both sides of the gate electrode, to thereby form
`extension regions 23.
`
`[0043] Next, a silicon oxide film is deposited by the CVD
`process over the entire surface, and is then anisotropically
`etched (etch-back) from the top surface thereof so as to
`allow the silicon oxide film to remain only on both side faces
`of the gate electrodes, to thereby form sidewalls 24.
`
`in the PMOS transistor formable area, a
`[0044] Next,
`p-type impurity ion is implanted into the surficial portion of
`
`the semiconductor substrate 1 on both sides of the gate
`electrode and sidewalls 24, to thereby form deep source-
`and-drain regions 20 which partially overlap the extension
`regions 22. On the other hand,
`in the NMOS transistor
`formable area, an n-type impurity ion is implanted into the
`surficial portion of the semiconductor substrate 1 on both
`sides of the gate electrode and sidewalls 24, to thereby form
`deep source-and-drain regions 21 which partially overlap the
`extension regions 23.
`
`[0045] Thereafter, an insulating film 25, which comprises
`a BPSG film or a silicon oxide film formed in a high density
`plasma, is deposited by the CVD process over the entire
`surface, and then planarizcd by the CMP (chcmical-mc-
`chanical polishing) process. A schematic plan view of the
`core area is shown in FIG. 4A, and a schematic sectional
`view taken along line I-I and line II—II in FIG. 4A is shown
`in FIG. 4B.
`
`[0046] Next, as shown in FIGS. 5A and 5B, contact holes
`26 through which electrodes are drawn out are formed in the
`insulating film 25 by photolithography and succeeding dry
`etching. A schematic plan view of the core area is shown in
`FIG. 5A, and a schematic sectional view taken along line I-I
`and line III-III in FIG. 5A is shown in FIG. 5B. As shown
`
`in FIG. 5A, in the present embodiment, the contact holes 26
`used for wiring connection are formed for every sixteen
`word lines 19 so as to reach the bit-line, impurity—diffused
`layers 4 at predetermined positions. There are also formed
`dummy contact holes 26a, which substantially do not con-
`tribute to wiring connection, so as to reach the bit-line,
`impurity-diffused layers 4.
`
`[0047] Next, the surface of the semiconductor substrate 1
`is cleaned by using a cleaning solution containing hydrof-
`luoric acid
`(hydrofluoric acid prc-trcatmcnt) or by
`using plasma (plasma pre-treatment), and as shown in FIG.
`6A, a titanium (Ti) film 27, where Ti is a refractory metal,
`of approx. 5 to 80 nm thick is formed by the IMP (Ionized
`Metal Plasma) process. On the titanium film 27, a titanium
`nitride film 28 of approx. 5 to 50 nm thick is further formed
`by the CVD process using TDMAT as a source gas. FIG. 6A
`shows a sectional view taken along the line I-1 and line
`III-III in the core area shown in FIG. 5A.
`
`the titanium nitride
`In the present embodiment,
`[0048]
`film 28 is formed typically in a thickness of 5 nm by the
`CVD process, and is then subjected to hydrogen plasma
`treatment at 350° C. to 450° C. for 40 seconds to 90 seconds.
`The titanium nitride film 28 herein is formed at a film
`
`forming temperature of 350° C. to 450° C. or around. It is
`also allowable to repeat, a plural number of times,
`the
`process steps of forming the titanium nitride film 28 in a
`thickness of 5 nm, and of subjecting the film to hydrogen
`plasma treatment for 70 seconds. Exemplary conditions for
`the hydrogen plasma treatment include hydrogen (H2) flow
`rate of 300 SCCM, nitrogen (N2) flow rate of 200 SCCM,
`RF power of 750 W, and RF frequency of 350 kHz. Such
`hydrogen plasma treatment is successful in erasing unnec-
`essary charge in the silicon nitride film 15 stored therein
`during the fabrication process. Raising the RF power to 850
`W, for example, can raise the density of hydrogen radical
`and can successfully enhance effect of the erasure.
`In
`addition, if the hydrogen plasma treatment is carried out
`before the titanium nitride film 28 is formed, hydrogen
`radical can more effectively be diffused through the contact
`
`|PR2014-00898
`(cid:44)(cid:51)(cid:53)(cid:21)(cid:19)(cid:20)(cid:23)(cid:16)(cid:19)(cid:19)(cid:27)(cid:28)(cid:27)(cid:3)
`Exhibit MX027||-1015, p. 11
`(cid:40)(cid:91)(cid:75)(cid:76)(cid:69)(cid:76)(cid:87)(cid:3)(cid:48)(cid:59)(cid:19)(cid:21)(cid:26)(cid:44)(cid:44)(cid:16)(cid:20)(cid:19)(cid:20)(cid:24)(cid:15)(cid:3)(cid:83)(cid:17)(cid:3)(cid:20)(cid:20)
`
`

`
`US 2004/0110390 A1
`
`Jun. 10, 2004
`
`holes without being consumed in formation of methylamine
`(HNCI-I3) or its analogue which otherwise possibly gener-
`ates as a byproduct of titanium nitride when TDMAT is used
`as a source gas. Hydrogen plasma treatment before forma-
`tion of the titanium nitride film 27 is also advantageous in
`allowing hydrogen to effectively diffuse through the contact
`holes without being gettered by titanium.
`
`[0049] For the case where the titanium nitride 28 is formed
`by the CVD process using TDMAT as a source gas, suc-
`ceeding hydrogen plasma treatment for as long as 35 sec-
`onds or more can beneficially remove impurities such as
`carbon derived from TDMAT.
`
`It is also allowable to carry out the aforementioned
`[0050]
`hydrogen plasma treatment
`typically by the double-fre-
`quency process which is based on so-called ICP (induction-
`coupled plasma) process. The same effect can be obtained by
`hydrogen annealing, employed in place of hydrogen plasma
`treatment, at 400° C. to 450° C. or around for 30 minutes to
`90 minutes or around.
`
`[0051] Next, a tungsten film is deposited by the CVD
`process over the entire surface, and the tungsten film is
`planarized by the CMP process to thereby form tungsten
`plugs 29 as being buried in the contact holes 26 as shown in
`FIG. 6B.
`
`[0052] Thereafter, unshown various wirings including alu-
`minum wiring are formed, and an unshown protective insu-
`lating film is formed as an uppermost layer. This completes
`a SONOS-type memory cell array in the core area, and
`CMOS-type transistors in the peripheral circuit area. The
`bit-line, impurity-diffused layers 4 in the core area herein are
`connected to the wirings. On the other hand, the dummy
`contact holes 26a shown in FIG. 5A are not used for the
`
`wiring connection even in the process of forming various
`wirings.
`
`[0053] After the above-described process steps, the semi-
`conductor memory device of the present embodiment
`is
`completed.
`
`the
`[0054] While in the above-described embodiment,
`hydrogen plasma treatment was carried out in succession to
`the formation of the titanium nitride film 28 by the CVD
`process,
`the present
`invention is by no means limited
`thereto, and any other process will be allowable provided
`that the silicon nitride film 15, which is a charge storage
`film, can be subjected to the hydrogen plasma treatment after
`the formation thereof. For example, the hydrogen plasma
`treatment can be effected at the time of the foregoing plasma
`pretreatment after the formation of the contact holes 26, or
`can be effected after the formation of the titanium film 27.
`
`[0055] While the LOCOS process was employed in the
`element isolation in the above-described embodiment, it is
`achievable by the STI (shallow trench isolation) process. It
`is also allowable to form the gate electrode by the SALI-
`CIDE process using a cobalt film, although the gate elec-
`trode in the above embodiment was formed by stacking the
`tungsten silicide layer on the polysilicon layer. While the
`core area of the SONOS-structured semiconductor m