1060
`
`A 14-11s l-Mbit CMOS SRAM with Variable
`Bit Organization
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 23, NO. 5, OCTOBER 1988
`
`YOSHIO KOHNO, TOMOHISA WADA, KENJI ANAMI, MEMBER, IEEE, YUJI KAWAI,
`
`KOJIRO YUZURIHA, TAKAYUKI MATSUKAWA, AND SHIMPEI KAYANO
`
`1
`
`1
`
`i l l
`
`I
`
`n
`
`W i
`t
`
`32KbCE:A::tA
`
`32Kb CELL ARRAY
`
`GLOBAL ROW DECODER
`
`5 BLOCK R W DE DER
`
`BL2
`
`32KbCELLARRAY
`
`BL3
`
`U
`z
`K
`
`BLOCK ROW DECODER
`32Kb CELL ARRAY
`
` CONTROLLER^
`Fig. 1. Block diagram of RAM
`
`Abstract -This paper will describe a 14-11s l-Mbit CMOS SRAM with
`both 1M wordX l-bit and 256K wordX4-bit organizations. The desired
`organization is selected by forcing the state of an external pin. The fast
`access time is achieved by use of a shorter divided-word-line (DWL)
`structure, a highly sensitive sense amplifier, a gate-controlled data-bus
`driver, and a dual-level precharging technique. The 0.7-pm double-
`aluminum and triple-polysilicon process technology with trench isolation
`offers a memory cell size of 41.6 pn? and a chip sue of 86.6 mn?.
`
`I.
`
`INTRODUCTION
`
`ITH recent advances in process technologies and
`new circuit techniques, hgh-speed, high-density
`SRAM’s have been developed. These RAM’S have been
`used mainly as main memory
`in supercomputers,
`cache/buffer memory in minicomputers and workstations,
`and as test pattern memory in VLSI test equipment. Re-
`cently, 256K CMOS SRAM’s were reported whch acheved
`access times of faster than 25 ns [1]-[3] by utilizing the
`address transition detection (ATD) techniques, configura-
`tions with shortened bit lines and word lines, polycide
`gates, and double-aluminum processes. Several medium-
`speed l-Mbit CMOS SRAM’s with byte-wide organization
`have already been reported [4]-[7], however, their access
`times are above 25 ns. This paper will describe a variable
`bit-organization 1M word X 1-bit or 256K word X 4-bit
`CMOS SRAM [SI with a typical access time of 14 ns. This
`RAM was fabricated employing double-aluminum and
`triple-polysilicon CMOS technology with a 0.7-pm mini-
`mum design rule. In order to obtain the fast access time, a
`32-block architecture with a divided-word-line (DWL)
`structure [9], a h a y sensitive sense amplifier, a gate-con-
`trolled data-bus driver, and a dual-level precharging tech-
`nique were combined with an ATD scheme.
`In Section 11, circuit technologies, which include the
`c h p architecture, the modified DWL structure, the sense
`amplifier, the gate-controlled data-bus driver, the dual-level
`data-bus precharge, and the variable bit-organization func-
`tion will be described. In Section 111, the process technol-
`ogy will be explained. Characteristics of the RAM and
`conclusions are given in Sections IV and V, respectively.
`
`Manuscript received March 17, 1988; revised May 23, 1988.
`The authors are with the LSI Research and Development Laboratory,
`Mitsubishi Electric Corporation, 4-1 Mizuhara, Itami, Hyogo 664, Japan.
`IEEE Log Number 8822500.
`
`11. CIRCUIT DESIGN
`A . Chip Architecture
`
`The block diagram of the RAM is illustrated in Fig. 1.
`The RAM is organized as either 1M w o r d x l bit or
`256K word x 4 bit. These organizations are controlled by
`t h e X l / x 4 control pin. The address signals are split into
`Y, Z, and W. The X-, Y-, Z-, and
`four groups--,
`W-address signals are used for row selection, column selec-
`tion, block selection, and sense-amplifier selection, respec-
`tively. The W address is only used in the 1M word X 1-bit
`organization. Each address input buffer has a local ATD
`pulse generator. A detection signal from any of the local
`ATD pulse generators activates the internal clocks which
`control the bit-line loads and the sense amplifiers in order
`to accelerate a readout operation.
`A block diagram of the memory archtecture is shown in
`Fig. 2. The 1-Mbit memory cell array is organized as 512
`rowsx2048 columns and is divided into 32 blocks. Only
`one memory cell block is activated at a time for power
`
`0018-9200/SS/1000-1060$01.00 01988 IEEE
`
`Spansion Exhibit 2009
`Macronix et al v. Spansion
`IPR2014-00898
`Page 00001
`
`

`

`KOHNO el ai.: CMOS SUM WITH VARIABLE BIT ORGANIZATION
`
`106 1
`
`-
`
`4sp(sEAIIpuca9s
`Fig. 2. Block architecture.
`
`DATA-
`
`GLOBAL ROW DECODER
`1-
`
`BLOCK ROW DECODER
`
`I
`P 1 '
`. P
`
`
`
`1
`
`2
`
` 4
`
`8
`
`1 6 3 2
`
`NUMBER OF R O W S IN A GROUP n R
`Fig. 4. Effect of modified DWL.
`
`I I I I
`
`20
`2 1
`
`22
`23
`24
`xo
`x 1
`
`Fig. 3. Word-line selection circuit
`
`reduction. Each block contains 512 x 64 columns with one
`redundant column. Only 65 memory cells are connected to
`a word line (DWL). The word line has been formed from
`tungsten-silicide polycide with a sheet resistance of 5 Q/sq.
`The short word line with low-resistive material reduces the
`word-line delay time to around 0.5 ns, whch is one key
`factor in reducing access time. Each block is further di-
`vided into four submatrices of 512 rowsXl6 columns,
`compatible with the nibble-wide organization (256K word
`X 4 bit). Row address input signals are hierarchically de-
`coded, using the DWL structure [9]. The block row de-
`coders of the DWL structure are arranged between every
`two blocks, resulting in a total of 16 block row decoders.
`The global row decoder is placed at one side of the
`memory array.
`
`B. Modified D WL Structure
`
`Fig. 3 shows a word-line selection circuit in the modified
`DWL structure introduced for improvement of the con-
`ventional DWL. XO- X8 and 20- 2 4 are address signals
`for row selection and block selection, respectively. The
`upper X address group of X2-X8 is predecoded in the
`global row decoder whch activates one of the row-group
`select lines. The row group consists of four rows. Each of
`the row-group select signals is input to eight NAND gates of
`each block row decoder. One of the four rows is selected
`by the predecoded signals of the lower addresses of XO
`and X1. Fig. 4 shows the effect of the modified DWL
`structure on the capacitance of the bit line and row select
`
`line, and the width of the row decoders (including the
`global row decoder and the block row decoders). The bit
`lines and the row select lines are fabricated by the first-
`and second-level aluminum, respectively. As the number of
`rows in a group ( n R ) increases, the bit-line capacitance
`decreases because the crossover capacitance with the row
`select lines decreases. However, the slope of the curve is
`very broad, especially beyond 4 of n R . In contrast, the
`capacitance of the row select lines increases rapidly as n R
`increases. Moreover, the capacitance on the predecoded
`signals of XO and X1 decreases. On the other hand, the
`width of the global row decoder decreases and the width of
`the block row decoder increases as n R is larger. Therefore,
`the width of the row decoders is minimized at 4 of n R .
`Consequently, this modified DWL structure has been ap-
`plied to the 1-Mbit SRAM, setting n R at 4. The modified
`DWL architecture with the small bit-line capacitance con-
`tributes to the fast access time by a 1.5-percent decrease of
`chip size compared to the conventional DWL.
`
`C. Sense Amplifier
`
`Fig. 5 shows the readout circuitry, which includes the
`sense amplifier, data-bus driver. dual-level data-bus pre-
`charger, and data-output buffer. The sense amplifier is
`comprised of three stages. The first and second stages are
`symmetric types, which have dual inputs and dual outputs.
`T h s symmetric sense amplifier is suitable to amplify the
`1/0 line's signals with a small voltage swing. Therefore,
`both ZERO READ and ONE READ access times coincide with
`each other. The third stage is a normal current mirror
`circuit, which has dual inputs and a single output. Each
`stage has a gain of around 3. In total, a voltage difference
`of less than 50 mV between 1/0 lines is successfully
`The pulses (SEQ1, SEQ2, SEQ3, DEQ, and
`amplified.
`DEQ) are generated from an internal clock, whch is
`caused by the ATD signal. The signals SEQl and SEQ2
`
`~
`
`Page 00002
`
`

`

`1062
`-
`vo
`
`vo
`
`-
`
`,s~a2
`
`,,
`
`U
`
`-
`-
`f 2 0 -
`t
`
`W
`
`(a) +
`
`4 0
`
`7
`
`GATE CONTROLLED i (b)
`,
`, ,
`
`IEEE JOUKNAI. OF SOLID-STAIE CIRCUITS, \'OL. 23. NO. 5. OClOBER
`
`1988
`
`I/O LINES- 1
`
`E-\
`
`I----
`
`U
`
`Fig. 7. Timing diagram.
`
`reduces the data-bus capacitance by around 40 percent.
`This reduction is effective in minimizing the delay time of
`the data bus.
`
`E. Dual-Level Datu-Bus Prechurge
`
`In order to further reduce the delay time on the data
`bus, the data bus is precharged at a middle voltage level
`[l], [4]. However, a special receiver circuit of the middle-
`level data bus is required to suppress a wrong data output
`during the middle-level precharging period. For example,
`the Schmitt trigger latch STL circuit [l] and the dual-
`
`>
`
`DUALLEVELDATA-BUSPRECHARGER
`
`SE03
`I
`
`DATA-OUFUT BUFFER
`0
`I
`
`DATA-
`
`Fig. 5. Readout circuit.
`
`+F
`
`0 2
`
`v)
`m
`U
`U
`n
`W
`
`(b)
`
`I O -
`
`(a)
`
`o
`
`'
`
`---a / - p *
`'
`'
`
`'
`
`'
`
`l
`
`'
`
`.
`
`
`
`equalize the complementary signals in the sense amplifier.
`Bit lines and 1/0 lines are also equalized by this internal
`clock. These equalizations accelerate the sensing speed.
`
`D. Gate-Controlled Data-Bus Driver
`
`The data-bus driver is also shown in Fig. 5. The data-bus
`driver is a tri-state CMOS inverter whose gates are con-
`trolled by the sense-enable signal SE. If it is selected, the
`S E signal is high and the SE signal is low. Accordingly,
`t h s data-bus driver works as a CMOS inverter with the
`same drivability. As shown in Fig. 2, when the memory cell
`array is divided into many blocks, the parasitic capacitance
`of the data bus becomes larger, because of the long wiring
`capacitance and the output capacitance of the data-bus
`driver. Fig. 6 shows the relation between data-bus capaci-
`tance and the number of memory cell blocks. The solid
`line (curve a ) and the broken line (curve b ) correspond to
`the gate-controlled tri-state data-bus driver and a conven-
`tional tri-state data-bus driver with a CMOS transmission
`gate [5], respectively. In order to maintain the drivability
`of the data-bus driver, the channel width of the conven-
`tional data-bus driver is doubled. The data-bus capaci-
`tance increases gradually as the number of blocks in-
`creases. In the 32-block archtecture, which is applied to
`the 1-Mbit SRAM, the gate-controlled data-bus driver
`
`~
`
`undesirable delay time. To remove this delay time in the
`receiver circuits, the dual-level data-bus precharging tech-
`nique is newly introduced. Ths technique does not need
`any special receiver circuits. The timing diagram of the
`is shown in Fig. 7. The pulses (SEQ3,
`readout operation
`DEQ, and DEQ) are used for the data-bus precharging.
`The precharged level of the data bus is split into two levels
`according to the previous READ data, which are stored in
`the small latch circuit connected to the input of the data-
`output buffer (Fig. 5). The low and high levels are around
`2 and 3 V, respectively. As the logical input threshold level
`of the data-output buffer is set to 2.5 V, a wrong data
`output during the precharge period is suppressed. The
`gate-controlled data-bus driver and the dual-level pre-
`charge technique realize a high-speed data transfer from
`the sense amplifier to the data-output buffer.
`
`F. Vuriable Bit-Organization Function
`
`The testing time of RAM'S consists of dc parametric test
`and ac (functional and operating margin) tests. The ac test
`time increases in proportion to the memory capacity when
`N-test patterns (linear addressing patterns) are used.
`Therefore, the test time of 1-Mbit SRAM's is quadrupled
`compared with that of 256-kbit SRAM's when the bit
`organizations are the same. To overcome this problem in
`DRAM'S the test mode [lo] is introduced. However, the
`
`Page 00003
`
`

`

`KOHNO et ul.: CMOS SRAM WITH VARIABLE BIT ORGANIZATION
`
`1063
`
`~~
`
`Process
`
`~~
`
`~~
`
`~
`
`TABLE I
`PUOCES.5 PAKA\LLlERS
`~-
`_________~_
`Twin-well CMOS, N-Sub
`Double Level Aluminum
`Triple Level Polysilicon
`Gate Length (NMOS)
`0.7um (LDD)
`(PMOS)
`0.9um (LDD)
`180h
`Gate Oxide Thickness
`Junction Depth (NMOS)
`0.2um
`(PMOS)
`0.3um
`t
`Trench N (widthlspace) 1.0um / 0.7um
`LOCOS N+ (widthlspace) 2.0um / 1.5um
`1st Poly Si
`(width/space) 0.7um / 0.8um
`1.OMm / 1.Oum
`2nd Poly Si (width/space)
`3rd Poly Si (widthlspace) 1.0m / 1.Oum
`1st AI
`(widthlspace) 1.4um / 1.0pm
`2nd AI
`(width/space) 2 . 0 ~ m / 2.0ym
`0.8um x 0.8um
`Contact Hole
`Direct Contact Hole
`0.8um x 0.8um
`l.Oum x 1.0pm
`Via Hole
`-
`
`FOR x l FOR x 4
`
`FOR x 4 FOR x i
`vcc
`vcc
`
`vss
`
`vss
`
`Fig. 8. Pin configuration
`
`. . r7
`
`32Kb CELLARRAY
`
`SENSE AMP.
`WRITE DRIVER
` IJ! ! ! ! I
`
`
`
`
`1 1 1 1 1 !
`!
` !
`!
`READ DATA-BUS] I I I
`
`I , ,
`
`I
`
`1 1 ,
`
` I
`
`I
`
`I I I I
`
`DATA INPUT BUFFERS I
`I::
`
`CONTROLLER
`
`I’O
`
`corresponds to four sense amplifiers/wRITE drivers. Each
`sense amplifier is connected to the READ data bus. In the
`case of 256K wordx4 bit, the READ data-bus signals are
`transferred to the four data-output buffers. In the case of
`1M w o r d x l bit, one of the READ data-bus signals is
`transferred to the one data-output buffer according to the
`1/0 select signals (1OSi). The READ data selector circuit is
`composed of CMOS transmission gates. As the READ data-
`bus signals are used for both organizations, the route of
`the data flow is the same. Consequently, the variable
`bit-organization function preserves the same access time
`for both organizations. As the 1M wordxl-bit RAM is
`changed to 256K word X 4 bit, the testing time of the 1 M
`word x l-bit RAM is reduced while keeping the measure-
`ment accuracy of the access time. A short and precise test
`methodology has been realized,
`
`111. 0.7-pm CMOS PROCESS TECHNOLOGY
`
`In order to achieve a high-density and high-speed SRAM.
`a 0.7-pm CMOS process technology was developed. The
`SRAM was fabricated with a double-level aluminum and
`triple-level polysilicon
`(including polycide)
`twin-well
`CMOS technology. The key process parameters are sum-
`marized in Table I. Fig. 10 describes the cross-sectional
`view of the memory cell.
`In order to obtain the small-area memory cell, triple-level
`polysilicon and trench isolation technology is adopted as
`in the 128K X %bit l-Mbit SRAM [5]. The first polysilicon
`layer (WSi , /polysilicon) is used for the MOS transistor
`gate electrodes. The second polysilicon layer is used for V,,.
`lines and the third polysilicon is for the high-resistive
`loads. The first aluminum layer is utilized for the bit lines
`and the second layer is for the row-group select lines. Fig.
`11 shows a photograph of the memory cells and block row
`decoder. The second-level aluminum lines of the row-group
`
`Fig. 9. Circuit szhematic of the variable bit-organization function.
`
`test mode in DRAM’S is not suitable to measure precise
`access times, because plural memory cells are written with
`the same data and only the logical relation among the
`READ data of these memory cells is checked. This means
`that the route of the data flow in the test mode is different
`from that of thz normal READ operation. In high-speed
`SRAM’s, the precise evaluation of the access time is im-
`portant as well as the reduction of test time. The variable
`bit-organization function is newly applied to reduce the
`test time wlule k.eeping the measurement accuracy of the
`access time. Fig. 8 shows the pin configurations of the
`l-Mbit S U M . This RAM can be used for 1M word x l-bit
`organization or :!56K word X 4-bit organization. The inner
`pin names are used for the 256K wordx4-bit RAM and
`the outer for the 1M word X l-bit RAM. These organiza-
`tions are controlled by pin #21. Pins 12. 13, and 15-19
`control
`serve different functions according to the X 1/=
`signal. All other pins have the same function for both
`organizations. Fig. 9 shows the circuit schematic of the
`variable bit-organization function. The memory cell block
`
`Page 00004
`
`

`

`1064
`
`1
`
`IELL JOURNAL OF SOLID-STATE CIRCUITS, VOL 23, NO 5. OCTOBLR 1988
`
`2nd A I (Row Group Select Line)
`
`li3[ W / L = 510.7
`V d = 5 v
`
`P-Well
`
`N-Substrate
`
`Barrier Metal
`
`1
`
`Fig. 10. Cross-sectional view of memory cell.
`
`1
`i
`
`-0.4
`
`0
`
`0.4
`
`0.8 1.2
`
`Gate Voltage (V)
`Fig 12 Companson of subthreshold current of NMOSFET's (U'/L =
`5/0 7 pm x 10 000) i\olated by LOCOS and trench
`
`Fig. 11. Photograph of memory cell and block row decoder.
`
`select line cross the first-level aluminum bit lines every
`four memory cells. The intermediate insulator between the
`first and second aluminum is p-CVD oxide. In the periph-
`eral circuits, the second-level aluminum electrode is utilized
`for signal lines, V,,, and ground lines.
`The triple-level polysilicon process enables a smaller
`memory cell in comparison with the double-level polysili-
`con process, and the hgher resistive load can be obtained
`easily.
`One of the key process technologies in realizing a small
`memory cell is the bird's beak free isolation. Instead of the
`conventional LOCOS isolation, a shallow trench isolation
`technique is adopted. The narrowest isolation width is 0.7
`pm. After silicon etching and boron implantation for
`channel cut, the trench wall is slightly oxidized to reduce
`leakage current. Then a silicon dielectric oxide is buried in
`the trench, and a successive etching-back process for
`surface planarization is carried out. After the trench isola-
`tion process, the conventional LOCOS isolation process is
`employed for peripheral circuit formation. The most im-
`portant electrical characteristic for
`the
`trench-iso-
`lated memory cell is the subthreshold-current curve of
`NMOSFET's. If the level of the leakage current through
`the driver transistor is the same as or much larger than the
`
`Fig. 13. Output waveforms of RAM.
`
`current through the high-resistive load connected to the V,,
`line, the memory cell cannot hold data. Fig. 12 shows the
`subthreshold current of NMOSFET's ( W / L = 5/0.7 pm,
`10000 FET's are arranged in parallel) isolated by the
`conventional LOCOS and by the trench. An explicit dif-
`ference is not observed for the subthreshold slope and the
`junction leakage current level.
`In
`this RAM, 0.7-pm NMOSFET's and 0.9-pm
`PMOSFET's help to achieve the high-speed circuit oper-
`ation. Both NMOSFET's and PMOSFET's are formed
`with a lightly doped drain (LDD) structure. This transistor
`structure assures reliability against hot-carrier-induced de-
`gradation for NMOSFET's and prevents degradation
`caused by the offset phenomenon for PMOSFET's.
`
`IV. CHARACTERISTICS
`
`Fig. 13 shows oscillographs of the data-output wave-
`forms under typical conditions of V,, = 5 V and T, = 25°C.
`access times are 14 ns
`The address access time and the
`with a load capacitance of 30 pF. An active current of 100
`mA (40 MHz), a standby current of 20 mA (40 MHz), and
`a typical standby current at CMOS inputs of 2 pA have
`been obtained.
`Fig. 14 shows the die photomicrograph. The memory
`array is divided into 32 blocks to shorten the word-line
`length. There are 16 block decoders and a global row
`decoder. Each block has one redundant column (512 cells).
`
`Page 00005
`
`

`

`KOHNO et al.: CMOS SRAM WITH VARIABLE BIT ORGANIZATION
`
`1065
`
`[3] K. L. Wang et al., “A 21-11s 3 2 K x 8 CMOS static RAM with a
`selectively pumped p-well array, IEEE J . Solid-State Circuirs. vol.
`SC-22, pp. 704-711, Oct. 1987.
`[4] T. Komatsu et U [ . , “A 35-11s 1 2 8 K x 8 CMOS SRAM.” IEEE J .
`Solid-Stute Circuits, vol. SC-22, pp. 121-726, Oct. 1987.
`[5] T. Wada et al., “A 34-11s 1-Mbit CMOS SRAM using triple
`polysilicon,” IEEE J . Solid-State Circuits, vol. SC-22, pp. 727-732,
`Oct. 1987.
`M. Matsui et U / . , “A 25-11s 1-Mbit CMOS SRAM with loading-free
`bit lines,” IEEE J . Solid-State Circuits, vol. SC-22, pp. 733-740,
`Oct. 1987.
`0. Minato et al., “A 42 ns 1Mb CMOS SRAM.” in ISSCC Dig.
`Tech. Pupers, Feb. 1987, pp. 260-261.
`T. Wada et ul., “ A 14ns 1Mb CMOS SRAM with variable bit-
`organization,” in ISSCC Dig. Tech. Pupers, Feb. 1988, pp. 252-253.
`M. Yoshimoto et ul., “A divided word-line structure in the static
`RAM and its application to a 64K full CMOS RAM,” IEEE J .
`Solid-Stute Circuits. vol. SC-18. pp. 479-485, Oct. 1983.
`M. Kumanoya et ul., “A reliable 1-Mbit DRAM with a multi-bit-test
`mode,” IEEE J . Solid-Store Circuits, vol. SC-20, pp. 909-913. Oct.
`1985.
`
`[6]
`
`[7]
`
`18)
`
`[9]
`
`[lo]
`
`Yoshio Kohno was born in Gifu. JaDan. on Julv
`16, 1947 He receired the B S degrees in chem-
`istry from Osaka University. Osaka. Japan. in
`1973 and the M S degree in chemistq from the
`Umversitv of Tok\o. Tokvo. JaDan in 1975
`He joined the Semiconductor Re\earch and
`Development Dicision. Mtsubish Electric Cor-
`poration, Hyogo. Japan, in April 1975 Since
`1980 he has been engaged in the research and
`development of CMOS process technology
`Mr Kohno is a member of the Japan Society
`of Applied Phy\ics and the Chemical Societv of Japan
`
`1
`
`
`
`-
`
`Tomohisa Wada was born in Hiroshima, Japan,
`on December 2, 1959. He received the B.S. de-
`gree in electronic engineering from Osaka Uni-
`versity. Osaka, Japan, in 1983.
`In 1983 hejoined the LSI Research and Devcl-
`opment Laboratory. Mitsubish Electric Corpo-
`ration, Itami, Japan. Since then he has been
`engaged in the design of MOS static RAM’S. He
`is currently involved in the devclopment of
`high-density and high-speed CMOS static RAM.
`Mr. Wada is a member of
`the Institute of
`Electronics and Comm
`unication Engineers of Japan.
`
`5.51mm x 15.72mm
`Fig. 14. Chip photograph.
`
`TABLE I1
`SUMMARY OF RAM CHARACTERISTICS
`
`0RGANUATK)N
`
`CELLSUE
`CHP SUE
`ACCESS TME
`
`256Kx4 / l M x l (VARIABLE)
`x 5 . 2 ~
`
`8.-
`
`5 . 5 1 m x 1 5 . 7 2 m
`
`1-
`
`ACTlVEUBRENT
`
`10Qn*at4OW+z
`
`S T
`
`REDUSANCY
`
`PACKAGE
`
`
`
`~RRDCT 2 a n ~ at 4 0 ~ n r
`~ Y
`m
`32 C
`4oGnll. 28%. DP/soJ
`-
`
`~~
`
`~~
`
`~
`
`T h s RAM is mounted in a 400-mil 28-pin DIP or SOJ.
`The characteristics of the RAM are summarized in Table
`11.
`
`V. CONCLUSION
`
`A fast 1-Mbit CMOS SRAM organized as 1M X 1 bit or
`256Kx4 bit has been described. A double-metal layer,
`triple-polysilicon
`layer, 0.7-pm minimum design rule
`CMOS process with trench isolation technology has al-
`lowed a cell size of 8.0 X 5.2 pm2 and a die size of 5.51 X
`15.72 mm2. New circuit techniques were developed to
`achieve h g h performances in speed. The 32-block division,
`a modified divided-word-line structure, a highly sensitive
`amplifier, a gate-controlled data-bus driver, and a dual-
`level data-bus precharge technique have achieved a typical
`access time of 14 ns and 100-mA active current at 40 MHz.
`Finally, the variable bit-organization function reduces
`the testing time whle keeping the measurement accuracy
`of the access times.
`
`ACKNOWLEDGMENT
`
`The authors gratefully acknowledge Dr. K. Shibayama,
`Dr. T. Nakano, and Dr. T. Kat0 for their encouragement
`and helpful discussions throughout t h s work.
`
`REFERENCES
`
`[l] S. Kayano et al., “25-11s 256Kx1/64KX4 CMOS SRAM’s,” IEEE
`p 686-791, Oct. 1986.
`J . Solid-State Circuits, vol. SC-21,
`[2] M. Honda et al., “A 25ns 256K ZMOS SRAM.” in ISSCC Dig.
`Tech. Papers, Feb. 1986, pp. 250-251.
`
`Kenji Anami (M’88) mas born in Oita, Japan. on
`Augu\t 11, 1950 He received the R S and Ph D
`degrees in electromc engineering from Kvushu
`University. Fukuoka, Japan, in 1973 and 1986.
`respectivelv
`He joined the Semiconductor Research and
`Development Divi\ion, Mitsubishi Electric Cor-
`poration, Hyogo. Japan. in 1973 From 1973 to
`1977 he worked on DSA MOS (DMOS) memon
`and gate arravs Since 1978 he has been engaged
`in the design of NMOS. CMOS, and bipolar
`ECL static memories He is currently a member of the Static RAM VLSI
`Dc\ign Group in the LSI Research and Development Laboratorv. Hyogo,
`Japan
`Dr Anami is a member of the Institute of Electromcs and Commumca-
`tion Engineers of Japan
`
`Page 00006
`
`

`

`1066
`
`Yuji Kawai was born in Satama. Japan. on De-
`cember 11, 1958 He received the B S and M S
`degrees in instrumental engineering from Keio
`Umversity. Tokyo, Japan, in 1981 and 1983.
`respectively
`In 1983 he joined the LSI Research and Devel-
`opment Laboratory. Mitsubishi Electric Corpo-
`ration, Itami, Japan Since then he has been
`engaged in the process of MOS static RAM’s
`
`Kojiro Yuzuriha was born in Saga. Japan, on
`February 15,1960. He received the B.S. degree in
`physics
`from Kyushu University, Fukuoka.
`Japan, in 1985.
`He joined the LSI Research and Development
`Laboratory, Mitsubishi Electric Corporation.
`Itami, Japan, in April 1985. Since then he has
`been engaged in the development of high-density
`CMOS static RAM’s.
`
`ILLL JOURNAL OF SOIID-STATL C I R C I J I I S . \’OI 23. NO 5. ocrmm 1988
`
`Tahajuki Matsukana was born in Nara. Japan.
`in Januarq 1947 He received the B S , M S . and
`Ph D degrees in dpplied physics from Osaka
`Universit). Osaka. Japan, in 1969. 1971. and
`1974. respectively
`He joined M~tsubishi Electric Corporation.
`Tokyo. Japan, in 1974, and has been engaged in
`the research and development of MOS memon
`process technolog! He is currently working on
`the dekelopment of nonbolatile memories and
`adbanced VLSI process technolog\
`Dr Matsukdwd is rl member of the Japan Soclet\ of Applied Ph\\ic\
`
`Shimpei Kajano was born in Tokyo. Japan, on
`November 7. 1942. He received the B.S. degree
`in metallic engineering from Kyoto University.
`Kyoto. Japan. in 1965.
`He joined
`the Semiconductor Dirision.
`Mitsubishi Electric Corporation. Hlogo. Japan.
`in 1965. Hc has been cngaged in the develop-
`ment of CMOS devices. He is currently the
`Manager of the Static RAM Design Group in
`the LSI Research and De\elopment Laboraton.
`Hq ogo. Japan.
`Mr. Kayano is a member of the Institute of Electronics and Communi-
`cation Engineers of Japan.
`
`Page 00007
`
`