`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`MACRONIX INTERNATIONAL CO, LTD, MACRONIX ASIA LIMITED,
`
`MACRONIX (HONG KONG) CO., LTD., and MACRONIX AMERICA, INC.
`Petitioners
`
`V.
`
`SPANSION LLC
`
`Patent Owner
`
`Case: IPR2014-00108
`
`CORRECTED DECLARATION OF DHAVAL J. BRAHMBHATT
`
`Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`United States Patent and Trademark Office
`
`PO Box 1450
`
`Alexandria, Virginia 22313—1450
`Submitted Electronically via the Patent Review Processing System
`
`EXHIBIT 2002
`
`9323f“
`
`
`
` SPANS'ON
`
`EXHIBIT
`
`Macronix
`Corrected
`
`IPR2014-00893
`
`MX0027-1002
`
`Spansion Exhibit 2002
`MacroniX et al V S ansion
`' p
`IPR2014-00898
`
`Page 00001
`
`'PR2014‘00‘05
`Corrected Exhibit MX027—1002. p. 1
`
`Spansion Exhibit 2002
`Macronix et al v. Spansion
`IPR2014-00898
`Page 00001
`
`
`
`I. Dhaval J. Brahmbhatt, hereby declare as follows:
`
`I.
`
`Introduction and Qualifications
`
`I.
`
`I am the founder and am currently the president and CEO of
`
`PHYchip Corporation (“PHYchip”). Among other things, PHYchip provides
`
`eXpert services in the design of high-speed analog and mixed-signal integrated
`
`circuit (“1C”), a variety of memory devices, with a particular focus on non-
`
`volatile memory devices such as Flash memory modules.
`
`'7
`
`I have prepared this Declaration on behalf of Macronix International
`
`Co., Ltd., Macronix Asia Limited, Macronix (Hong Kong) Co., Ltd, and
`
`Macronix America, Inc. (collectively, “‘Macronix”) in connection with a petition
`
`for
`
`Inter Partes Review of US. Patent No. 7,151,027 (“the ”0227 Patent”)
`
`(MX027—1001).
`
`3.
`
`l have summarized in this section relevant aspects of my educational
`
`background and career history. My full resume is attached as Appendix A to this
`
`Declaration.
`
`Educational Background
`
`4.
`
`In 1977,
`
`I received a Master of Science Degree in Physics with a
`
`specialization in Solid State Electronics from Gujarat University in India.
`
`In
`
`1978,
`
`I received a second Master of Science Degree,
`
`this one in Electrical
`
`Engineering, from the University ofCincinnati in Ohio.
`
`I also hold certificates in
`
`lPR2014—00103
`Corrected Exhibit MX02?~1 002. p. 2
`
`Page 00002
`
`Page 00002
`
`
`
`management trainings from Stanford University Graduate School of Business, a
`
`certificate in marketing from University of London in Ontario, Canada and a
`
`certificate in nanotechnology from the California Institute ot‘Nanoteehnology.
`
`Career History
`
`5.
`
`I have over 30 years of substantive experience in the field of IC
`
`memory device design and manufacture.
`
`l began my career in 1978 at a Fairchild
`
`Semiconductor. working
`
`on
`
`the
`
`design and development of Erasable
`
`Programmable Read-Only Memory (“‘EPROM") products.
`
`I later worked on the
`
`design and production of
`
`single power
`
`supply Electronically Erasable
`
`Programmable Read-Only Memory (“EEPROM”) products for Syner’tek, which
`
`was a subsidiary of Honeywell international. Inc, and then I worked for National
`
`Semiconductor as a design manager for high density EEPROM memory devices.
`
`6.
`
`In 1996, I was named Vice President of Technology and Business
`
`Development for the Smart Modular Corporation.
`
`In that position, I oversaw the
`
`design. development, and marketing of advanced IC memory-based modules
`
`such as Flash memory cards
`
`for portable devices produced by major
`
`multinational technology companies.
`
`7.
`
`I later consulted in the Flash memory card industry and served as a
`
`“C” level officer in several start-up companies that developed IC devices prior to
`
`founding PHYchip Corporation in 2002.
`
`tPRZOH-Umflfl
`Corrected Exhibit NIXON—1002. p. 3
`
`Page 00003
`
`Page 00003
`
`
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`8.
`
`I am the sole inventor on ten patents and the lead inventor on all
`
`eleven patents listed under my name at the USPTO. Most of these patents relate
`
`to EPROM, EEPROM, and/or Flash memory [C design, memory cell design,
`
`memory array architecture, etc.
`
`II.
`
`Scope of Assignment
`
`9.
`
`I have been asked to provide my opinion on the validity of the '02?
`
`Patent.
`
`In particular,
`
`I have been asked to consider whether the inventions
`
`recited in claims 1—14 of the ’02? Patent are unpatentable over certain published
`
`prior art references. This Declaration sets forth my opinion on this topic.
`
`10.
`
`In my analysis, I considered the ‘02? Patent and its file history, as
`
`well as the prior art references and related documentation discussed below.
`
`I
`
`have considered these documents in light of the general knowledge in the art at
`
`the time of the alleged inventions.
`
`In formulating my opinion, I have relied upon
`
`my experience, education, and knowledge in the relevant art.
`
`I have also helped
`
`prepare and reviewed in detail the claim charts that are to be included with the
`
`petition for Inter Partes Review of the ’02? Patent, to which this Declaration
`
`relates.
`
`11. Additional information may become available which would further
`
`support or modify the conclusions that I have reached to date. Accordingly,
`
`I
`
`reserve the right to modify and/or enlarge this opinion or the bases thereof upon
`
`IPRZD‘I 4—001 08
`Corrected Exhibit MX027—1002. p. d
`
`Page 00004
`
`Page 00004
`
`
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`consideration of any further discovery. testimony. or other evidence, or based
`
`upon the interpretations of or conclusions about any claim term by the Patent
`
`Office different than those proposed in this declaration.
`
`"I. The ”027 Patent
`
`12.
`
`It appears from the face of the ’027 Patent that it issued from US.
`
`patent application number 10/859,369, which was filed on June 1, 2004.
`
`It does
`
`not appear the patent claims an earlier filing date.
`
`13.
`
`The ”027 Patent generally relates to a method for manufacturing a
`
`semiconductor memory device. More particularly, the “027 Patent is intended to
`
`reduce the interface area of a memory device, by forming an interface structure in
`
`the area between the memory core and the periphery.
`
`14.
`
`The ”02'? Patent discloses an embodiment of the steps required to
`
`form this
`
`interface structure in Figures 3A through 30, along with the
`
`accompanying text.
`
`In the following discussion, each of Figures 3A through 3G
`
`have been annotated to help distinguish the various layers.
`
`15.
`
`F irst. as shown in Figure 3A, a first layer of polysilicon, or “poly— l ,”
`
`(green) is formed over an isolation area (light blue) over a silicon substrate
`
`(darker blue). See MX027-1001 at 3:50—67.
`
`IPR2014-OO1US
`Corrected Exhibit MX027—1002, p. 5
`
`Page 00005
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`Page 00005
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`
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`coreI
`
`interface
`
`IPefipheW
`
` I
`
`Figgre 3A
`"
`16. Next, as shown in Figure 33, a dielectric material (red) is formed
`
`over the entire surface. The ’02? Patent describes an embodiment in which
`
`this dielectric consists of “ONO,” a well-known dielectric material that consists
`
`of layers of Silicon Oxide, Silicon Nitride, and Silicon Oxide. See MX027-1001
`
`at 4:1—9.
`
`I
`
`care
`
`|
`.
`we
`
`| 1‘5
`
` :
`
`Figure 33
`
`I
`
`I
`
`17. Next, as shown in Figure 3C, a known etching process is used to
`
`remove some of the dielectric and polysilicon layers.
`
`|PR2014-00108
`Corrected Exhibit MX02?-1002, p. 6
`
`Page 00006
`
`Page 00006
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`
`
`
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`18. Next, as shown in Figure 3D, a second poly silicon layer, or “poly-
`
`2,” (yellow) is formed over the entire structure. MX027-1001 at 3:10-21
`
`core
`
`98097190!
`[—9-
`
`315
`
`19. Next, a known etch process, such as a “stacked gate etch,” is used to
`
`etch the structure on the side nearest the memory core. This etch removes the
`
`poly-2 layer, the dielectric layer, and the poly-1 layer in the unmasked region.
`l
`
`The resulting structure is illustrated in Figure 3E. MX027-1001 at 4:27-37.
`
`care
`«4
`
`'he
`£2.29 6*
`
`
`
`|PR2014-00108
`Corrected Exhibit MX027—1002. p. 7
`
`Page 00007
`
`Page 00007
`
`
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`20. Next, a second etching process, such as a “second gate etch,” is used
`
`to etch the structure on the side nearest the periphery. This etch removes only the
`
`poly-2 layer (as that
`
`is the only layer in the unmasked region). After the
`
`completion of these two etch steps, the interface structure remains in the interface
`
`area between the memory core and periphery.
`
`The resulting structure is
`
`illustrated in Figure 3F. MX027-1001 at 4:38-49.
`
`core
`
`lnterlace
`
`periphery
`
`
`
`Fi
`
`r
`
`F
`
`21.
`
`Finally, as illustrated in Figure 3G, dielectric material (purple) is
`
`deposited on the entire structure, and selectively etched to form dielectric film
`
`345 over the top of the core, interface structure, and periphery. This dielectric
`
`deposit and etch process also creates spacers 350 on the side walls of the core,
`
`interface structure, and periphery. MX027-1001 at 4:55 — 5:4.
`
`IPR2014—00108
`Corrected Exhibit MX027—1002. p. 3
`
`Page 00008
`
`Page 00008
`
`
`
`
`
`I.
`
`Summary of My Opinions
`
`22.
`
`Based on my investigation and analysis, and for the reasons set forth
`
`below, it is my opinion that all of the elements recited in claims 1—14 of the ’02?
`
`Patent are disclosed in prior art references, and that those claims are anticipated
`
`by and/or rendered obvious in View of these references. In particular,
`
`I have
`
`reviewed the following prior art references:
`
`0
`
`I
`
`0
`
`U.S. Patent No. 6,458,655 to Yuzuriha, et a1. (“Yuzuriha”) (MX027-
`
`1003)
`
`U.S. Patent No. 6,258,648 to Lee (“Lee”) (MX027-1004)
`
`U.S. Patent No. 6,599,012 to Shukuri, er a1. (“Shukuri”) (MX027-
`
`1005)
`
`-
`
`U.S. Patent No. 6,359,304 to Nakagawa (“Nakagawa”) (MX027—
`
`1006)
`
`23.
`
`I have read and understood the claim charts attached to the Petition,
`
`and agree with the technical analysis set forth therein.
`
`IPR2014—00108
`Corrected Exhibit MX027—1002. p. 9
`
`Page 00009
`
`Page 00009
`
`
`
`ll.
`
`Background of Relevant Technology
`
`“Floating Gate" Memory Cells: EPROM and Flash
`
`24.
`
`The ‘02? Patent states that “[t]he present invention relates to the
`
`field of floating gate devices." MX027-1001 at 1:6-7. A “floating gate" is a
`
`well- known configuration that is used to create non-volatile memory, a class of
`
`semiconductor memory that retains storage of data even after a power supply is
`
`removed from the memory. Examples of technologies that can be implemented
`
`using a floating gate include EPROM, EEPROM. and Flash — all of which are
`
`types of non-volatile memory.
`
`25.
`
`The floating gate structure has been in use since at least 1972, when
`
`Dov Frohman of Intel was awarded US. Patent number 3,660,819.
`
`In this kind
`
`of device, each storage location consists of a single Field Effect Transistor (PET)
`
`that
`
`is different from other transistors because it also has over the transistor
`
`channel gate oxide, an additional gate which is called the “floating gate” because
`
`it is not connected to any node. Above the floating gate will be formed another
`
`insulating layer, over which a second conducting gate called “control gate" will
`
`be deposited. A cross section of a memory cell utilizing a floating gate can be
`
`illustrated as follows:
`
`IPR2014-00103
`Corrected Exhibit NIXON-1002. p. 10
`
`Page 00010
`
`Page 00010
`
`
`
`Control Gale
`
`
`
`Etching
`
`26.
`
`In semiconductor processing, “etching” generally refers to process
`
`of applying a temporary layer commonly known as a “photoresist,” patterning
`
`the photoresist into a “mask,” and then using chemicals to remove portions of the
`
`semiconductor structure not covered by the mask. Once the intended removal is
`
`complete, the photoresist is removed.
`
`27.
`
`Etching is one of the fimdamental
`
`techniques in semiconductor
`
`device manufacture; the manufacture of a semiconductor device will typically
`
`include many repetitions of the process of growing or depositing a layer of
`
`material, and selectively etching the material in areas uncovered by the mask for
`
`that
`
`layer. The “0227 Patent does not utilize any novel etch processes, but
`
`describes the use of known etch processes such as a “stacked gate etch.”
`
`See,
`
`e.g., MX027—1001 at 4:27-30.
`
`JPRZD14—DD108
`Corrected Exhibit NIXON-1002, p. 11
`
`Page 00011
`
`Page 00011
`
`
`
`Ill.
`
`Legal Principles Used in Analysis
`
`28.
`
`I am not a patent attorney, nor have 1 independently researched the
`
`law of patent validity. Attorneys have explained certain legal principles to me
`
`that l have relied on in forming my opinions set forth in this Declaration.
`
`Person of Ordinary Skill in the Art
`
`29.
`
`I understand that assessment of the validity of claims 1-14 of the
`
`‘027 Patent must be undertaken from the perspective of what would have been
`
`known or understood by someone of ordinary skill
`
`in the art as of the earliest
`
`claimed priority date of the ’02? Patent — June 1, 2004. From analyzing the ”027
`
`Patent and the prior art, it is my opinion that a person of ordinary skill in the art
`
`would have a bachelor’s degree in Electrical Engineering and 2-3 years of
`
`experience in design or fabrication of semiconductor memories. An individual
`
`with additional education or industry experience could also be one of ordinary
`
`skill in the art if that additional experience compensated for a deficit in the other
`
`aspect stated above. Unless otherwise stated, when I
`
`state that
`
`something
`
`would be known or understood by one skilled in the art, or having ordinary
`
`skill
`
`in the art,
`
`I am referring to a person with this level of education and
`
`experience.
`
`30.
`
`A person of ordinary skill
`
`in the art of semiconductor memory
`
`design and fabrication would have looked to various sources of available
`
`lPR2014—00108
`Corrected Exhibit MXDZT—tODE. p. 12
`
`Page 00012
`
`Page 00012
`
`
`
`information in order to address the. purported problem of the ”027 Patent —
`
`improving the fabrication of memory devices at the interface between memory
`
`array and periphery.
`
`Identification of this problem, along with various
`
`solutions, can be found in numerous references including Yuzuriha (MX027-
`
`1003 ).
`
`Prior Art
`
`31.
`
`I have been informed that the law provides certain categories of
`
`information (known as prior art) that may be used to anticipate or render obvious
`
`patent claims. I have been asked to presume that the reference materials I opine
`
`on below are prior art, and have not formed an opinion whether these references
`
`are, in fact, prior art as applied against the “027 Patent.
`
`Anticipation
`
`3:...
`
`l have been informed that a claim is not patentable when a single
`
`prior art reference describes every element of the claimi either expressly or
`
`inherently to a person of ordinary skill in the art.
`
`I understand that this is
`
`referred to as “anticipation."
`
`I have also been informed that, to anticipate a
`
`patent claim, the prior art. reference need not use the same words as the claim, but
`
`it must describe the requirements of the claim with sufficient clarity that a person
`
`of skill in the alt would be able to make and use the claimed invention based on
`
`the single prior art reference.
`
`lF’R2014-UO103
`Corrected Exhibit MX02?-10l]2, p. 13
`
`Page 00013
`
`Page 00013
`
`
`
`33.
`
`In addition. I was informed and understand that. in order to establish
`
`that an element of a claim is “inherent" in the disclosure of a prior art reference,
`
`it must be clear to one skilled in the art that the missing element is an inevitable
`
`part of what
`
`is explicitly described in the prior art, and that
`
`it would be
`
`recognized as necessarily present by a person of ordinary skill in the art.
`
`D.
`
`Obviousness
`
`34.
`
`l have been informed that. even if every element of a claim is not
`
`found explicitly or implicitly in a single prior art reference, the claim may still be
`
`unpatentable if the differences between the claimed elements and the prior art are
`
`such that the subject matter as a whole would have been obvious at the time the
`
`invention was made to a person of ordinary skill in the art. That is, the invention
`
`may be obvious to a person having ordinary skill in the art when seen in light of
`
`one or more prior art references. I understand that a patent is obvious when it is
`
`only a combination of old and known elements, with no change in their
`
`respective functions, and that these familiar elements are combined according to
`
`known methods to obtain predictable results.
`
`35.
`
`I have been informed that the following four factors are considered
`
`when determining whether a patent claim is obvious: (I) the scope and content of
`
`the prior art; ('2) the differences between the prior art and the claim; (3) the level
`
`of ordinary skill in the art; and (4) secondary considerations tending to prove
`
`FRESH-00108
`Corrected Exhibit MXOZT—TDDZ, p. 14
`
`Page 00014
`
`Page 00014
`
`
`
`obviousness or nonobviousness.
`
`I have also been informed that the courts have
`
`established a collection of secondary factors of nonobviousness, which include:
`
`unexpected, surprising, or unusual results; non-analogous art; teachings away
`
`from the invention; substantially superior
`
`results; synergistic results;
`
`long-
`
`standing need; commercial success; and copying by others.
`
`I have also been
`
`informed that there must be a connection between these secondary factors and
`
`the scope ofthe claim language.
`
`36.
`
`l have also been informed that some examples of rationales that may
`
`support a conclusion of obviousness include: (A) combining prior art elements
`
`according to known methods to yield predictable results; (B) simply substituting
`
`one known element for another to obtain predictable results; (C) using known
`
`techniques to improve similar devices (methods, or products) in the same way;
`
`(D) applying a known technique to a known device (method, or product) ready
`
`for improvement to yield predictable results; (E) choosing from a finite number
`
`of identified, predictable solutions, with a reasonable expectation of success—in
`
`other words, whether something is “obvious to try”; (F) using work in one field
`
`of endeavor to prompt variations of that work for use in either the. same field or a
`
`different one based on design incentives or other market forces if the variations
`
`are predictable to one of ordinary skill in the art; and (G) arriving at a claimed
`
`invention as a result of SOme teaching, suggestion, or motivation in the prior art
`
`IPR2014—00108
`Corrected Exhibit MX027—1002. p. 15
`
`Page 00015
`
`Page 00015
`
`
`
`that would have led one of ordinary skill to modify the prior art reference or to
`
`combine prior art reference teachings.
`
`37.
`
`l have also been informed that other
`
`rationales to support a
`
`conclusion of obviousness may be relied upon, for instance, that the common
`
`sense (where substantiated) of the person of skill in the art may be a reason to
`
`combine or modify prior art to achieve the claimed invention.
`
`IV. Claim Construction
`
`38.
`
`Attorney have provided me with constructions of various terms
`
`within the “027 Patent’s claims.
`
`I have not been asked to form, and I have not
`
`formed, an opinion regarding these claim constructions. Below is a list of the
`
`provided constructions, which [ applied when rendering the opinions set forth
`
`herein:
`
`
`
`Claim Term
`
`Broadest Reasonable
`
`Interpretation
`
`
`“interface between a memory
`
`an area between an may of
`
`
`
`
`
`
`
`
`etching step that etches at least a “stacked gate etch”
`
` “second gate etch"
`
`
`
`
`
`array and a periphery“
`
`memory cells and a periphery
`
`portion of a stacked gate structure
`
`etching step that etches at least a
`
`portion of a second gate
`
`lPR2014-DD1UB
`Corrected Exhibit NIXON-1002. p. 16
`
`Page 00016
`
`Page 00016
`
`
`
`
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`“such that step size is smoothed
`
`not a limitation
`
`out, reducing an occurrence of
`
`stringers from spacer etching"
`
`
`V.
`
`Invalidity Analysis
`
`A.
`
`Claims 1-4, 6, 8-10, and 13 are anticipated by
`
`Yuzuriha i. Description of the reference
`
`39.
`
`United States Patent 6,458,655 to Yuzuriha, et a1. (""Yuzuriha") is
`
`entitled “Method of Manufacturing Semiconductor Device and Flash Memory." [
`
`understand that Yuzuriha will be designated as Exhibit MX027-1003 to the
`
`Petition for Inter Partes Review. Based on the face of the patent. Yuzuriha was
`
`issued on October 1, 2002.
`
`40.
`
`Like
`
`the ’02? Patent, Yuzuriha is directed to a method for
`
`manufacturing a semiconductor memory that
`
`includes forming a structure
`
`between a memory array (referred to in Yuzuriha as
`
`a “memory cell
`
`region”) and a periphery (“peripheral circuit region”).
`
`41.
`
`As shown in Figure 5 of Yuzuriha, a structure composed ofpoly-l
`
`layer 10 (green), inter—layer dielectric 1 1 (red), poly—2 layer 13 (yellow), and top
`
`layer of oxide 16 is formed in the “dummy gate region” between the memory
`
`array and the periphely.
`
`lPR2014-00103
`Corrected Exhibit MX027~1DUZ p. 17
`
`Page 00017
`
`Page 00017
`
`
`
`DUMMY GATE PERIPHEFML
`messarcmeeas Resale»: __,,sm_cu_lrsr,aselo~
`:6 1 111311a10a
`=14
`-
`1./1
`
`number v
`
`.‘_ \
`'.
`
`I
`
`:
`
`'
`
`:
`
`‘
`'
`
`'
`
`.
`
`
`interface area
`
`'
`
`42.
`
`As discussed in more detail below, Yuzuriha discloses every
`
`element of claims 1-4, and 8-10 of the ’027 Patent.
`
`It is therefore my opinion
`
`that these claims are unpatentable as anticipated by Yuzuriha.
`
`ii. Application to the claims of the ’02"! Patent
`
`43.
`
`Claims 1, 2, and 8. Claim 1 of the ”027 Patent claims a method for
`
`fabricating a memory device, comprising forming a poly-2 layer above a
`
`substrate at an interface between a memory array and a periphery; etching the
`
`poly-2 layer proximate to the memory array, and etching the poly—2 layer
`
`proximate to the periphery, such that a portion of the poly-2 layer remains at the
`
`interface.
`
`44.
`
`Claim 2 depends from claim 1, and adds the limitations that a layer
`
`of poly-l is formed in the interface between the substrate and the poly-2, and that
`
`IPR2014—00108
`Corrected Exhibit MX027—1002, p. 18
`
`Page 00018
`
`Page 00018
`
`
`
`said poly-l layer is etched proximate to the memory array, and etched proximate
`
`to the periphery, so that a portion of poly-l remains at the interface.
`
`45.
`
`Independent claim 8 claims a method for
`
`fabricating a memory
`
`device, comprising forming a poly-l
`
`layer above a substrate at
`
`an interface
`
`between a memory array and a periphery; forming a poly-2 layer above the poly-
`
`1
`
`layer at
`
`the interface, etching the poly—l and poly-2 layers proximate to the
`
`memory array, and etching the poly-2 layer proximate to the periphery, such that
`
`a portion ofthe poly l and poly-2 layers remain at the interface.
`
`46. Yuzuriha discloses forming such a structure in its description of a
`
`tenth embodiment, which is illustrated in Figures 5—10. MX027-1003 at
`
`I 1:39-
`
`62. As described in Yuzuriha, Figure 5 is a cross section of a memory device,
`
`and Figures 6-10 are cross sections of the device at various stages of its
`
`manufacture. MX027—1003 at 8:4-10.
`
`47.
`
`Figure 5 of Yuzuriha shows that a “dummy gate region” is located
`
`between a “memory cell region" and a “peripheral circuit region.”
`
`IPR2014~DO1OB
`Corrected Exhibit NIXON—1002, p. 19
`
`Page 00019
`
`Page 00019
`
`
`
`DUMMY GATE PERIPHERAL
`
`FEE-M951: CEHLLrflgglgfl I _REGION -.n_;..jg_lfiEUlTH:J REGION
`I
`I
`
`:14
`gate
`
`
`
`
`’!
`
`
`i i i i
`
`16 1E111311a10a
`
`I
`
` peripher y
`
`poly-2
`
`substrate
`
`mteflace area
`
`48.
`
`This paragraph intentionally left blank.
`
`49.
`
`To a person of skill in the art, the “memory cell region” of Yuzuriha
`
`is the same as the “memory array” of the ’02? Patent. Similarly, the “peripheral
`
`circuit region” is the same as the “periphery” of the ”027 Patent. The “dummy
`
`gate region” of Yuzuriha is therefore the “interface between a memory array and
`
`a periphery” claimed in the ’02? Patent.
`
`50.
`
`As part of the process of forming the structure in the interface of
`
`Figure 5, Yuzuriha discloses that a “first polysilicon layer 10” is deposited across
`
`the surface of the memory array, the interface, and the periphery. On top of the
`
`polysilicon 10, a layer of dielectric, referred to as “poly-poly insulation film 11”
`
`is also formed. Finally, a layer of photoresist 15 is added and patterned, so that it
`
`is covering the memory cell region and part of the interface, which are not to be
`
`etched. Figure 6 shows the cross section of the device after these steps have been
`
`performed.
`
`IPR2014-00108
`Corrected Exhibit MXD27—1OBZ. p. 20
`
`Page 00020
`
`Page 00020
`
`
`
`
`
`51.
`
`It is common in the art to refer to layers of polysilicon by a number
`
`that
`
`indicates the position of the layer relative to the substrate (which will
`
`typically correspond to the order of manufacture). Because the “first polysilicon
`
`layer 10” of Figures 5-10 is the polysilicon layer closest to the substrate, one of
`
`skill in the art would refer to polysilicon layer 10 as “the poly-1 layer” (or more
`
`simply, “poly-1”).
`
`52.
`
`In the next step, Yuzuriha discloses etching the poly-1 layer
`
`proximate to the periphery (using the photoresist shown in Figure 6 as a mask),
`
`so that some of the poly—1 remains over the interface area. MX027-1003 at 12:6-
`
`13. Figure 7 shows the structure after the unmasked area of poly-l has been
`
`etched.
`
`IPR2014-00103
`Corrected Exhibit MX02?-1002. p. 21
`
`Page 00021
`
`Page 00021
`
`
`
`etching poly-1 pmidmate to
`the periphery
`
`1 1
`
`1O
`9
`
`
`- ________
`
`interface agree
`
`,
`
`
`i pegphay
`
`53. After removal of the photoresist, a second layer of polysilicon (13)
`
`is formed over the surface of the device, and a layer of oxide 16 is formed on top.
`
`MX027-1003 at
`
`12:28-30. Because this is the second layer of polysilicon
`
`deposited, a person of skill in the art would refer to this as the poly-2 layer.
`
`Figure 8 shows the structure after these steps have been performed.
`
`0 BA
`llll:
`'
`
`16 * :\\\\\\\_\\\\\“““
`
`I
`
`=
`
`FIGS
`
`memory array
`
`interface area
`
`periphery
`
`IPR2014-00108
`Corrected Exhibit MX027-1002. p. 22
`
`Page 00022
`
`Page 00022
`
`
`
`54. Although the text of Yuzuriha at column 12, lines 28 through 55
`
`makes reference to Figure 7, it is clear from the context that this text is actually
`
`describing Figure 8. First, Figure 7 was already described at lines 10 through 22.
`
`Second, the arrows A, B, and C that are described in this text appear only in
`
`Figure 8. A person of skill in the art would easily recognize this typographical
`
`error, and would understand that this description applies to Figure 8.
`
`55. After formation of the poly-2 layer and oxide 16, the oxide and
`
`poly—2 are etched, and “a memory cell’s control gate 13 and a peripheral
`
`circuitry’s transistor gate 13 are patterned.” MX027-1003 at 12:56-59. As can
`
`be seen from Figure 9, this involves etching the poly-2 in the interface structure
`
`proximate to memory, and etching the poly-2 proximate to the periphery. After
`
`these etch steps, a portion of poly—2 remains in the interface area.
`
`FIG- 9
`
`etching poly-2 pronmate l0
`”'19”th W3?
`
`919mg POW-2
`premiere to periphery
`
`16
`
`1316
`
`16
`
`13 11a10a 16
`
`14
`
`13 '
`
`-16
`
`memory 3'73?
`
`'
`
`interface area I
`
`12
`periphery
`
`lPR2014-00108
`Corrected Exhibit MX027~1002, p. 23
`
`Page 00023
`
`Page 00023
`
`
`
`56.
`
`Finally, Yuzuriha describes using the remaining oxide film 16 as an
`
`etching mask, and etching the poly-poly insulation mask 11 and the poly-1.
`
`MX027-1003 at 12:60—63. As such, the poly—1 in the interface area is etched
`
`proximate to the memory array. Figure 10 shows the result of this etch.
`
`FIG.1 0
`
`15
`
`Etching.poly-1 proximate
`to the memory array
`13 16
`
` 911910 9
`
`57. Accordingly, as discussed above, Yuzuriha discloses all elements of
`
`claims 1,2, and 8.
`
`58.
`
`Claims 3 and 9. Claims 3 and 9 of the ’02? Patent depend from
`
`claims 1 and 8, respectively, and add the limitation that etching the poly-2 layer
`
`proximate to the memory array is accomplished by performing a stacked gate
`
`etch.
`
`59. Yuzuriha discloses etching the poly—2,
`
`inter—poly film, and poly—1
`
`layer by using the oxide 16 as an etching mask. MX027-1003 at 12:56-59. As
`
`can be seen from Figure 10, these etching steps are used to form the stacked gate
`
`structure of the memory cells. See MX027-1003 at 43 -45.
`
`IPR2014—00103
`Corrected Exhibit MX027-1002. p. 24
`
`Page 00024
`
`Page 00024
`
`
`
`FIG. 10
`
`16
`
`131:6
`
`16101113113103
`I,
`
`f.
`
`1::
`
` 16~
`
`13
`u -
`10-
`
`.\—a .15
`‘I13
`
`12
`
`The etching of poly-2, poly-poly insulation, and poly-1 using patterned oxide 16
`
`is an example of a stacked gate etch.
`
`60.
`
`CZaims 4 and 10. Claims 4 and 10 depend from claims 1 and 8,
`
`reSpectively, and add the limitation that etching the poly—2 layer proximate the
`
`periphery is accomplished by performing a second gate etch.
`
`61.
`
`As shown in Figure 9, the poly-2 layer is etched proximate the
`
`periphery to form the gate of the peripheral circuit transistor, and to leave a
`
`portion of the poly-2 in the interface area. Because this etch forms the peripheral
`
`circuit transistor gate from poly-2, this is the “second gate etch” required by
`
`claims 4 and 10 of the ”027 Patent.
`
`B.
`
`Claims 1-6 and 8-13 are anticipated by
`
`Shukuri i. Description of the reference
`
`62. United States Patent 6,559,012 to Shukuri, et a1. (“Shukuri”) is
`
`entitled “Method for Manufacturing Semiconductor Integrated Circuit Device
`
`Having Floating Gate and Deposited Film.” I understand that Shukuri will be
`
`|PR2014-00108
`Corrected Exhibit MX027-1002, p. 25
`Page 00025
`
`Page 00025
`
`
`
`designated as Exhibit MX027-1005 to the Petition for Inter Partes Review.
`
`Based on the face of the patent, Shukuri was issued on May 6, 2003.
`
`63.
`
`Shukuri
`
`is directed to methods for manufacturing semiconductor
`
`devices using different process technologies on the same integrated circuit.
`
`Shukuri discloses the formation of multiple “element forming regions” that are
`
`used to form different types of transistors. The third embodiment of Shukuri
`
`discloses the manufacture of a microprocessor with a built in flash memory,
`
`in
`
`which one “element forming region” is used for non-volatile memory cells, and
`
`two other regions are used for logic transistors operating at different voltages.
`
`MX027-1005 at 17:13-17, FIG. 24.
`
`64.
`
`In this third embodiment, Shukuri discloses the formation of a
`
`structure at the interface between the first (or memory) element forming region
`
`and the second (logic transistor) element forming region. See id. at Fig. 24.
`
`[PR2014-00103
`Corrected Exhibit MX027-1002. p. 26
`
`Page 00026
`
`Page 00026
`
`
`
` 5:
`a?
`5:3 r4
`, a r
`—-
`'
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`
`
`
`
`JAMWW
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`
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`.9WII, W A
`
`
`
`
`
`5‘
`I
`interface 1 memory
`
`periphery
`
`l
`:
`
`
`
`
`
`
`65.
`
`As shown in Figure 24,
`
`the interface structure is formed above
`
`substrate 51 at the interface between the memory and the periphery, and is
`
`composed of a poly-1 layer (green), an inter-poly dielectric (red), and a poly-2
`
`layer (yellow).
`
`66.
`
`Shukuri also discloses the formation of sidewall spacers (orange)
`
`made of Silicon Nitride, in the periphery, in the interface, and in the memory
`
`core. MX027-1005 at 21:4-10. Shukuri discloses leaving the sidewall spacers in
`
`place as source and drain implants are performed. Id. at 21:11—19.
`
`ii. Application to the claims of the ’02? Patent
`
`67.
`
`Claims I, 2, and 8. Claim 1 of the ’027 Patent claims a method for
`
`fabricating a memory device, comprising forming a poly-2 layer above a
`
`substrate at an interface between a memory array and a periphery; etching the
`
`poly—2 layer proximate to the memory array, and etching the poly—2 layer
`
`IPR2014—00108
`Corrected Exhibit MX027—1002, p. 2?
`
`Page 00027
`
`Page 00027
`
`
`
`proximate to the periphery, such that a portion of the poly-2 layer remains at the
`
`interface.
`
`68.
`
`Claim 2 depends from claim 1‘ and adds the limitations that a layer
`
`of poly-l is formed in the interface between the substrate and the poly-2, and that
`
`said poly—1 layer is etched proximate to the memory array. and etched proximate
`
`to the periphely, so that a portion of poly-l remains at the interface.
`
`69.
`
`Independent claim 3 claims a method for fabricating a memory
`
`device,
`
`comprising forming a poly-l
`
`layer
`
`above
`
`a
`
`substrate
`
`at
`
`an
`
`interface between a memory array and a periphery; forming a poly-2 layer above
`
`the poly-l
`
`layer at
`
`the
`
`interface, etching the poly-l
`
`and poly-2 layers
`
`proximate to the memory array, and etching the poly-2 layer proximate to the
`
`periphery, such that a portion of the poly 1 and poly-2 layers remain at the
`
`interface.
`
`70.
`
`Shukuri discloses the
`
`formation of this
`
`structure in
`
`its
`
`third
`
`embodiment, which is illustrated in Figures 23-32. MX027-1005 at 16:57-61.
`
`Figure 24 of Shukuri
`
`is a cross section of an integrated circuit device and
`
`Figures 25-32 are cross sections at stages in the process of manufacture. Id. at
`
`5:28-50.
`
`71.
`
`Figure 24 of Shukuri
`
`illustrates that such a structure has been
`
`formed at the interface between a first element forming region (where non-
`
`lPR2C|14~DU1DB
`COFFECted Exhibit MX02?A1UDZ. p. 28
`
`Page 00028
`
`Page 00028
`
`
`
`volatile floating-gate memory cells are formed) and a second element forming
`
`region (where logic transistors are formed).
`
`
`
`
`Sfl
`
`
`
`
`
`
`
`
`Eiflmflfl
`IMm
`
`
`
`
`
`
`
`periphery
`
`
`51
`:
`interface : memory
`
`5
`
`72. Although Shukuri does not use the term “periphery”, a person of
`
`skill in the art would recognize that the logic transistor forming regions shown in
`
`Figure 24 form a portion of the periphery of the memory array. Accordingly, the
`
`structure is formed at the interface of the memory array and the periphery.
`
`73.
`
`In forming the
`
`interface s