`(12) Patent Application Publication (10) Pub. No.: US 2003/0042520 A1
`Tsukamoto et al.
`(43) Pub. Date:
`Mar. 6, 2003
`
`US 2003004252()A1
`
`(54) SEMICONDUCTOR INTEGRATED CIRCUIT
`DEVICE AND A METHOD OF
`MANUFACTURING THE SAME
`
`(30)
`
`Foreign Application Priority Data
`
`Aug. 31, 2001
`
`(JP) ...................................... 2001-263736
`
`(75)
`
`Inventors: Kelsuke Tsukamoto, Ome (JP);
`Yoshihiro Ikeda, Hamura (JP);
`“atom”
`Ome
`Daisuke
`okada, Kum'mcm(1p); Hjmsm
`Yanagita, Hamura (JP)
`Correspondence Address.
`MILES & STOCKBRIDGE PC
`1751 HNNACLE DRIVE
`SUITE 500
`MCLEAN, VA 221024833 (US)
`
`(73) Asgignae: Himchi, Lm_
`
`(21) App1_ No_;
`
`10/196,166
`
`(22) Filed:
`
`Jul. 17, 2002
`
`Pllblitfitloll Cl3SSifiC3ti0ll
`
`257/296
`
`Int. CL7 ..................................................
`(52) US. Cl.
`ABSTRACT
`(57)
`Defects in element forming regions on which memory cells
`of a non-volatile memory are formed are to be diminished to
`reduce leakage current. End portions of element forming
`regions with non-volatile memory cells formed thereon are
`extended a length D by utilizing the region which underlies
`a dummy conductive film, whereby a stress induced from an
`insulating film which surrounds the element forming regions
`is concentrated on the extended region. As a result, defects
`do not extend up to the regions where memory cells are
`formed and therefore it is possible to reduce leakage current
`in the memory cells.
`
`PERIPHERAL cuacun
`FOFIMWG REGION (PCFR)
`
`MEMORY CELL FOHMtNG REGlON (MCFR)
`
`
`
`
`
`EXHIBIT 2001
`
`SPANSION
`9/23/14
`
`I PR2o14-00393
`
`
`
`A
`
`EXHIBIT
`
`MACRONIX
`
`MX027||—1004
`
`Spansion Exhibit 2001
`
`Macronix et al v. Spansion
`IPR2014-00898
`
`Page 00001
`
`Spansion Exhibit 2001
`Macronix et al v. Spansion
`IPR2014-00898
`Page 00001
`
`
`
`
`
`
`
`
`
`FIG.1MEMORYCELLFORMINGREGION(MCFR)
`
`Patent Application Publication Mar. 6, 2003 Sheet 1 of 17
`
`US 2003/0042520 A1
`
`C}
`U‘)
`Q
`
`LO
`
`\/\
`
`
`(PCFR)
`
`REGIONPERIPHERALCIRCUITFORMING
`
`
`_1
`_I
`...J
`_l
`I
`ol
`I
`UI
`<53»/I2 mvJ5<*.a«I< mvJ<,
`IICDI
`I(DI
`3 I I
`I-
`.
`' .._,_........;..._..,_.__..........
`.
`;
`
`L)
`
`.1 .:o::
`
`IPR2014-00898
`Exhibit MXO27II-1004, p. 2
`
`Page 00002
`
`Page 00002
`
`
`
`Patent Application Publication Mar. 6, 2003 Sheet 2 of 17
`
`US 2003/0042520 A1
`
`-
`
`
`
`SBL
`
`24
`
`FIG. 2
`DC(P2) DC(P1)
` lgwmmg
`I?!’
`sigzv
`
`
`
`
`
`
`
`
`Y
`
`A
`
`Ki
`
`IA—’JTm
`
`8(LAc>
`
`6
`
`am
`
`c)
`
`
`
`1
`
`
`
`A
`
`'..v.4.¢Affl
`
`ax. -‘-5-.\\¢'—-‘='-fi}4.7'(
`'/
`
`1
`
`
`A I‘
`
`IVQIDZVJ
`
`6
`
`,‘
`
`Exhibit MX
`
`014-00898
`-1004, p. 3
`
`Page 00003
`
`Page 00003
`
`
`
`Patent Application Publication Mar. 6, 2003 Sheet 3 of 17
`
`US 2003/0042520 A1
`
`f:7(E3.
`
`41
`
`MEMORY CEU.ARRAY(MCAR)
`
`STRESS
`
`992
`
`§
`
`
`
`STRESS
`
`STRESS
`
`f:7(E3.
`
`53
`092
`
`STRESS
`
`T"“'X use
`Y
`
`5
`3
`
`
`
`STRESS
`
`STRESS
`
`MEMORY CELL ARRAY (MCAR)
`
`IPRZO14-00898
`Exhibit MXO27||-1004, p. 4
`
`Page 00004
`
`Page 00004
`
`
`
`Patent Application Publication Mar. 6, 2003 Sheet 4 of 17
`
`US 2003/0042520 A1
`
`FIG. 6
`
`Exhibit M
`
`P 2014-00898
`||—1004, p. 5
`
`Page 00005
`
`Page 00005
`
`
`
`Patent Application Publication Mar. 6, 2003 Sheet 5 of 17
`
`US 2003/0042520 A1
`
`
`
`IQ.’/Ffii
`
`
`AimIIInllnulnillniulullllninu
`
`7n-1004, p. 6
`
`Page00006
`
`Page 00006
`
`
`
`Patent Application Publication Mar. 6, 2003 Sheet 6 of 17
`
`US 2003/0042520 A1
`
`fl
`
`D
`
`7'
`
`D
`
`|PR2
`Exhibit MX027||-
`
`-0
`4.
`
`.
`
`Page 00007
`
`Page 00007
`
`
`
`Patent Application Publication Mar. 6, 2003 Sheet 7 of 17
`
`US 2003/0042520 A1
`
`FIG. 12
`
`M1(40)
`
`\\\\\\\\\\\
`
`V
`
`
`
`
`
`
`
`
`
`
`
`Page 00008
`
`
`
`Patent Application Publication
`
`Mar. 6, 2003 Sheet 8 of 17
`
`US 2003/0042520 A1
`
`
`
`
`
` .502zoawmoz_2m8:3Eosm:Eu_on:205mmoz__2
`
`
`
`
`
`
`
`
`
`W.»1Emma._<mm_.§
`
`o<._
`
`IPRZO14-0
`Exhibit MXO27||-1004,
`
`.
`
`Page 00009
`
`Page 00009
`
`
`
`Y
`
`De1
`
`:
`
`:
`
`AC2*‘“\_ : -
`
`STRESS
`
`j
`I
`
`Patent Application Publication Mar. 6, 2003 Sheet 9 of 17
`
`US 2003/0042520 A1
`
`FIG. 14
`
`,.._,.X
`
`> Die
`
`STRESS
`
`D92
`
`MEMORY CELL
`
`ARRAv\(McAR)
`
`_w_
`
`:
`
`}
`
`i
`:
`
`:
`1
`'
`
`'
`:
`
`‘
`:
`
`Ac1
`
`Ac1
`
`Ac1
`
`AC1
`AC1
`
`E
`
`E
`5
`
`D82
`
`A01
`
`STRESS
`
`IPRZO14-00898
`Exhibit MX027||-1004, p. 10
`
`Page 00010
`
`Page 00010
`
`
`
`Patent Application Publication
`
`Mar. 6, 2003 Sheet 10 of 17
`
`US 2003/0042520 A1
`
`
`
`
`
`8§_.§oo.8§.E5o.8
`
`
`
`E33zoammozzéou.30E05:2GE
`
`
`
`E9:298$
`
`was
`
`same.2
`5.:
`
`$538$.59§_E.oo
`
`IPR
`Exhibit MX027lI-
`
`4—DO898
`4, p. 11
`
`Page 00011
`
`Page 00011
`
`
`
`Patent Application Publication
`
`Mar. 6, 2003 Sheet 11 of 17
`
`M0
`
`Q8
`
`
`
`EOEzoammozsmeSoEosmz
`
`.9GE
`
`._._:
`
`3523%..
`
` .mu_§
`
`zoawmoz:
`
`W.axioma.:.§§_a§W5_mm,‘
`
`
`,2I}._...E.____.u__.H2......
`
` 0__..u.._a..._4-»...TEjZ;Z......
`
`o<._
`
`lPR2014~00898
`Exhibit MX027||-1004, p. 12
`
`Page 00012
`
`Page 00012
`
`
`
`Patent Application Publication Mar. 6, 2003 Sheet 12 of 17
`
`US 2003/0042520 A1
`
`FIG. 17
`
`.._..x
`i
`
`MEMORY CELL
`ARRAY (MCAR)
`
`
`
`STRESS
`
`IPRZO14-00898
`Exhibit MX027H—1004, p. 13
`
`Page 00013
`
`Page 00013
`
`
`
`Patent Application Publication
`
`Mar. 6, 2003 Sheet 13 of 17
`
`US 2003/0042520 A1
`
`
`
`
`
` EH55:zoammoz_:m8duoE052Eu_o.:zo_om_moz_2mou_
`
`
`
`
`
`
`
`
`
`,2GE
`
`
`
`cams._<$:.__$n_
`
`IPRZO14-00898
`Exhibit MXO27I|-1004, p. 14
`
`Page 00014
`
`Page 00014
`
`
`
`Patent Application Publication Mar. 6, 2003 Sheet 14 of 17
`
`US 2003/0042520 A1
`
`FIG. 19
`
`SBL
`D0(P2) DC(P1)
`
`
`jllllzflfl
`in-G—
`V V
`
`
`Wflfiwat
`at! A?-9:.“ 4-'1 ~
`
`
`
`
`'9
`
`
`
`
`
`
`.4.-M-2.‘-5|
`
`.'.-‘..=
`\}k\‘
`F’
`
`—l':TA—Q-
`A
`1
`A
`
`3(|-AC)
`
`5
`
`8(Ac
`
`)
`
`A
`
`Exhibit MX
`
`2014-O
`-1004,
`
`.
`
`Page 00015
`
`Page 00015
`
`
`
`Patent Application Publication Mar. 6, 2003 Sheet 15 of 17
`
`US 2003/0042520 A1
`
`EGE
`
`o<ommomwmmhm
`
`M_o<_u<_Am<oz.><¢m<W0H.:mo
`>mo2m2\x:/z+\.<_W.o<_
`
`
`
`“.HHsuHH....oumumMHMHMHHHMHMMHHMHHHMHMammo........-HM........H...._
`
`
`
`o<o«mo
`
`mmwmpw
`
`mmmmhm
`
`.mo
`
`mo<
`
`IPRZO14-00898
`Exhibit MX027|l-1004, p. 16
`
`Page 00016
`
`Page 00016
`
`
`
`Patent Application Publication Mar. 6, 2003 Sheet 16 of 17
`
`US 2003/0042520 A1
`
`.....
`
`.|
`
`-|lJl:
`
`._
`
`.
`
` I1....._..._l_._.M_oo..0D01...
`
`own)..."._.__
`
`Ii--
`
`8
`
`8
`
`..fin.
`5......m;i.....
`
`_._
`
`o_
`
`Exhibit MXO
`
`P
`
`014-00898
`I-1004, p. 17
`
`Page 00017
`
`Page 00017
`
`
`
`Patent Application Publication Mar. 6, 2003 Sheet 17 of 17
`
`US 2003/0042520 A1
`
`FIG. 23
`
`SB
`
`
`
` I/O DEVICES
`
`HOST CPU
`
`232
`
`SBI
`
`
`
`
`
`MEMORY CARD
`
`234
`
`IPRZD14-00898
`Exhibit MX027Il—1004, p. 18
`
`Page 00018
`
`Page 00018
`
`
`
`US 2003/0042520 A1
`
`Mar. 6, 2003
`
`SEMICONDUCTOR INTEGRATED CIRCUIT
`DEVICE AND A METHOD OF MANUFACTURING
`THE SAME
`
`BACKGROUND OF THE INVENTION
`
`[0001] The present invention relates to a semiconductor
`integrated circuit device and a method of manufacturing the
`same. Particularly, the present invention is concerned with a
`technique applicable eflectively to a semiconductor inte-
`grated circuit device in which elongated element forming
`regions are formed side by side.
`
`[0002] A semiconductor integrated circuit device com-
`prises elements and wiring lines formed on main surfaces of
`element forming regions (active) each defined by an insu-
`lating film. For example, the element forming regions are
`isolated from each other by an element isolation region. The
`element
`isolation region is formed for example by an
`element isolating film. For example, the element isolating
`film is formed with use of STI (Shallow Trench Isolation)
`technique. According to this STI technique, an insulating
`film such as silicon oxide film is deposited on a trench
`formed in a semiconductor substrate, then the silicon oxide
`film present outside the trench is removed, for example, by
`(‘MP (Chemical Mechanical Polishing), allowing the silicon
`oxide film to be buried in the interior of the trench, and the
`trench with the silicon oxide film thus buried therein is used
`for the isolation between elements.
`
`For example, a memory LS! (Large Scale Inte-
`[0003]
`grated Circuit) such as an Electrically Erasable Program-
`mable Read Only Memory (EEPROM) is formed on each of
`elongated element forming regions arranged side by side at
`a certain pitch.
`
`[0004] With microstructurization and high integration of
`memory cell, there is a tendency that such element forming
`regions become smaller in width and are arranged at a
`narrower pitch.
`
`[0005] As to a flash memory of NOR type with a drain
`contact formed using what is called SAC (Self-Aligned
`Contact) technique for coping with the tendency to micro-
`structurization of memory cell, it is described, for example,
`in IEDM (International Electron Devices Meeting), 1998,
`pp.979-982, “A Novel 4.6F2NOR Cell Technology With
`Lightly Doped Source (LDS) Junction For High Density
`Flash Memories.”
`
`SUMMARY OF THE INVENTION
`
`[0006] Having made studies about semiconductor memo-
`rics, especially such a non-volatile memory as mentioned
`above, the present inventors found out the following prob-
`lem not publicly known.
`
`[0007] Defects of memory cells increase with miniatur-
`ization of elements. Through our studies about the cause of
`such an increase of defects we suspect that a crystal defect
`which occurs at an end portion of an element forming region
`may be the cause.
`
`[0008] More particularly, in an outer periphery portion of
`memory cell forming regions within a semiconductor inte-
`grated circuit device there cxists a peripheral circuit forming
`region in which are formed a logic circuit, etc. (“peripheral
`circuits” hereinafter) necessary for driving memory cells.
`
`Thus, elongated element forming regions with memory cells
`formed thereon are arranged at a narrow pitch, and around
`those regions is disposed another element forming region
`With peripheral circuits formed thereon. These element
`forming regions are isolated using a wide insulating film.
`
`in
`[0009] Therefore, as will be fully described later
`embodiments of the invention, more easily occur stress
`concentration and crystal defects at end portions of elon-
`gated element forming regions with memory cells formed
`thereon.
`
`leakage current
`[0010] Once such a defect occurs,
`increases between a drain region of each memory cell and a
`semiconductor substrate and also between source and drain
`regions. Moreover, when the leakage current increases larger
`than the operating current of a sense amplifier, a defect
`results.
`
`[0011] Further, as noted earlier, since plural memory cells
`are formed on an elongated element forming region, the
`occurrence of a defect even in one memory cell will lead to
`defect of all memory cells connected to the same data line
`as that of the defective memory cell.
`
`It is an object of the present invention to diminish
`[0012]
`defects of a semiconductor substrate in element forming
`regions.
`
`is another object of the present invention to
`It
`[0013]
`diminish defects of a semiconductor substrate in element
`forming regions and thereby diminish leakage current.
`
`It is a further object of the present invention to
`[0014]
`diminish leakage current and thereby improve product yield
`and reliability.
`
`[0015] The above and other objects and novel features of
`the present invention will become apparent from the fol-
`lowing description and the accompanying drawings.
`
`[0016] Typical inventions disclosed herein will be out-
`lined below.
`
`(1) Asemioondnctor integrated circuit device
`[0017]
`comprising two or more element forming regions
`each having memory cells formed thereon and
`defined by an insulating film, the element forming
`regions each extending in a first direction and being
`arranged in a second direction perpendicular to t the
`first direction, end portions of the element forming
`regions being extended up to below a conductive
`film which is formed so as to surround the memory
`cells.
`
`(2) A semiconductor integrated circuit device
`[0018]
`comprising two or more element forming regions
`each defined by an insulating film and extending in
`a fil'S1 direction, the element forming regions being
`arranged in a second direction perpendicular to the
`first direction, end portions of the element forming
`regions being connected by a connecting portion
`which extends in the second direction.
`
`(3) A semiconductor integrated circuit device
`[0019]
`comprising plural element forming regions each hav-
`ing memory cells formed thereon and defined by an
`insulating film, the element forming regions extend-
`ing in a first direction and being arranged in a second
`direction perpendicular to the first direction, wherein
`
`IPRZO14-00898
`Exhibit MX027Il-1004, p. 19
`
`Page 00019
`
`Page 00019
`
`
`
`US 2003/0042520 Al
`
`Mar. 6, 2003
`
`the width in the second direction of an outmost
`element forming region out of the plural element
`forming regions is made larger than the width of each
`of the other element forming region(s).
`
`(4) A semiconductor integrated circuit device
`[0020]
`comprising plural element forming regions each hav-
`ing memory cells formed thereon and defined by an
`insulating film, the element forming regions extend-
`ing in a first direction and being arranged in a second
`direction perpendicular to the first direction, wherein
`no cell functioning as a memory cell is formed on an
`outermost element forming region out of the plural
`element forming regions.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0021] FIG. 1 is a plan View of a principal portion of a
`substrate, showing a semiconductor integrated circuit device
`according to a first embodiment of the present invention;
`
`[0022] FIG. 2 is a sectional View of a principal portion of
`the substrate in the semiconductor integrated circuit device
`of the first embodiment;
`
`[M23] FIG. 3 is a sectional View of a principal portion of
`the substrate in the semiconductor integrated circuit device
`of the first embodiment;
`
`[0024] FIG. 4 is a plan view of a principal portion of the
`substrate in the semiconductor integrated circuit device of
`the first embodiment;
`
`[0025]
`
`FIG. 5 is a plan view of the principal portion;
`
`[M26] FIG. 6 is a sectional view of a principal portion of
`the substrate, showing a method of manufacturing the semi-
`conductor integrated circuit device of the first embodiment;
`
`[0027] FIG. 7 is a sectional View of the substrate principal
`portion in the manufacturing method;
`
`[0028] FIG. 8 is a sectional view of the substrate principal
`portion in the manufacturing method;
`
`[0029] FIG. 9 is a sectional view of the substrate principal
`portion in the manufacturing method;
`
`[0030] FIG. 10 is a sectional view of the substrate prin-
`cipal portion in the manufacturing method;
`
`[0031] FIG. 11 is a sectional view of the substrate prin-
`cipal portion in the manufacturing method;
`
`[0032] FIG. 12 is a sectional view of the substrate prin-
`cipal portion in the manufacturing method;
`
`[(133] FIG. 13 is a plan view of a principal portion of a
`substrate, showing a semiconductor integrated circuit device
`according to a second embodiment of the present invention;
`
`[0034] FIG. 14 is a plan view of a principal portion of the
`substrate in the semiconductor integrated circuit device of
`the second embodiment;
`
`[0035] FIG. 15 is a plan view of a principal portion of the
`substrate in the semiconductor integrated circuit device of
`the second embodiment;
`
`[0036] FIG. 16 is a plan view of a principal portion of a
`substrate, showing a semiconductor integrated circuit device
`according to a third embodiment of the present invention;
`
`[0037] FIG. 17 is a plan view of a principal portion of the
`substrate in the semiconductor integrated circuit device of
`the third embodiment;
`
`[0038] FIG. 18 is a plan view of a principal portion of a
`substrate, showing a semiconductor integrated circuit device
`according to a fourth embodiment of the present invention;
`
`[0039] FIG. 19 is a sectional view of a principal portion
`of the substrate in the semiconductor integrated circuit
`device of the fourth embodiment;
`
`[0040] FIG. 20 is a sectional view of a principal portion
`of the substrate in the semiconductor integrated circuit
`device of the fourth embodiment;
`
`[0041] FIG. 21 is a plan view of a principal portion of the
`substrate in the semiconductor integrated circuit device of
`the fourth embodiment;
`
`[0042] FIG. 22 is a circuit diagram corresponding to the
`semiconductor
`integrated circuit device of
`the
`fourth
`embodiment; and
`
`[0043] FIG. 23 is a diagram showing a computer system
`using a semiconductor integrated circuit device according to
`the present invention.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`invention will be
`[0044] Embodiments of the present
`described in detail hereinunder with reference to the accom-
`panying drawings. In all of the drawings for illustrating the
`embodiments, portions which exhibit the same functions are
`identified by the same reference numerals and repeated
`explanations thereof will be omitted.
`
`First Embodiment
`
`[0045] FIG. 1 is a plan view of a principal portion of a
`semiconductor integrated circuit device according to a first
`embodiment of the present invention. In the same figure, the
`right-hand portion represents a memory cell forming region
`MCFR and the left-hand portion represents a peripheral
`circuit forming region PCFR. In the memory cell forming
`region MCFR, non-volatile memory cells of NOR type are
`arranged in the form of an array MCAR, while in the
`peripheral circuit forming region there are formed MISFETS
`S for selection as an example of peripheral circuits. FIG. 2
`is a schematic sectional View taken on line A-A in FIG. 1
`and FIG. 3 is a schematic sectional view taken on line B-B
`in FIG. 1.
`
`[0046] As shown in FIG. 1, in the memory cell forming
`region, element forming regions (active) Ac each extending
`in X direction are arranged at predetermined certain pitches
`in Y direction. The element fonning regions Ac are each
`defined by an insulating film 6, e.g., silicon oxide film. That
`is, adjacent element forming regions Ac are isolated from
`each other through the insulating film 6 which is an element
`isolating film. For example, as shown in FIGS. 2 and 3, the
`insulating film 6 is formed by STI structure buried in a
`trench formed in a semiconductor substrate. In the element
`
`forming regions Ac, p-type wells 8 are exposed to a surface
`of a semiconductor substrate 1.
`
`[0047] The width W in Y direction of each element
`forming region is about 0.3 ,urn for example, the spacing SW
`
`lPR2014—O0898
`Exhibit MX027I|-1004, p. 20
`
`Page 00020
`
`Page 00020
`
`
`
`US 2003/0042520 A1
`
`Mar. 6, 2003
`
`between adjacent element forming regions Ac is about 0.4
`,u.m for example, and the length (width in X direction) of
`each element forming region is about 80 ,um in correspon-
`dence to, for example, a 128-bit memory cell MC. In each
`element forming region there are formed plural memory
`cells MC in X direction.
`
`are
`forming regions Ac
`the element
`[0048] Above
`arranged control gates (second electrodes) CG at predeter-
`mined ccnairt pitches, the control gates CG extending in Y
`direction. The width L in X direction of each control gate CG
`is about 0.3 ,urn for example and the spacing LS between
`adjacent control gates CG is about 0.35 pm for example. The
`control gates CG are formed integrally with control gates
`CG of memory cells MC arranged in Y direction and serve
`as word lines WL extending in Y direction.
`
`[0049] Between the control gates CG and the element
`forming regions Ac, as shown in FIGS. 2 and 3, are formed
`an insulating film comprising a laminate film (“ONO film”
`hereinafter) 21 of silicon oxide film, silicon nitride film and
`silicon oxide film laminated in this order, floating gates (lirst
`electrodes) PG, and a gate insulating film 9 formed by a
`thermal oxide film. The floating gates FG are each formed
`independently for each memory cell (see FIG. 3).
`
`In each of the element forming regions Ac located
`[0050]
`at both ends of the control gates CG there are formed n"'—type
`semiconductor regions 17 (source and drain regions). On the
`drain region 17 is formed a plug (drain contact) DC (P1),
`while on the source region 17 is formed a plug (source
`contact) SC (P1). The plug DC (P1) is formed independently
`for each memory cell, while the plug SC (P1) is connected
`electrically to each of source regions 17 of memory cells MC
`connected to one and same word line and constitutes a
`source line SL extending in Y direction. That is, the plug
`(source contact) SC (P1) is a wiring line extending in Y
`direction and constitutes a source line SL. As will be
`described later, the plugs DC (P1) and SC (P1) are formed
`in the same manufacturing step.
`
`[0051] On the drain region 17 is formed a two-layer
`structure comprising plugs DC (P1) and DC (P2). On the
`plug DC (P2) is formed a sub bit line SBL which extends in
`X direction.
`
`[0052] As shown in FIG. 1, the plug SC (P1) is connected
`to a common source line CSL through the plug SC (P2). The
`common source line CSL also extends in X direction and is
`formed by the same wiring layer as the sub bit line SBL. The
`plugs DC (P2) and SC (P2) are formed in the same manu-
`facturing step.
`
`[0053] Thus, each memory cell MC is composed princi-
`pally of a pair of n*-type semiconductor regions 17 which
`are source and drain regions, a channel forming region
`(p-type well)8 (Ac) formed between those semiconductor
`regions, a gate insulating film 9 formed on the channel
`forming region, a floating gate FG formed on the gate
`insulating film 9, an insulating film 21 formed on the floating
`gate FG, and a control gate CG formed on the insulating film
`21. The source and drain regions 17 of memory cells MC
`adjacent to each other in Y direction are isolated by the
`insulating film 6 and the control gates CG of memory cells
`MC arranged in Y direction are formed integrally with the
`word lines WL. The drain regions 17 of memory cells MC
`arranged in Y direction are electrically connected to different
`
`sub bit lines SBL, and the source regions 17 of memory cells
`MC arranged in Y direction are electrically connected
`together through source lines SL. The drain regions of
`memory cells MC adjacent in X direction are constituted in
`common and are electrically connected to sub bit lines SBL.
`Likewise,
`the source regions 17 of memory cells MC
`adjacent in X direction are constituted in common and are
`electrically connected to source lines Sl...
`
`[0054] The following description is now provided about
`write, read and erasing operations for each memory cell.
`
`[0055] Reference will first be made to a write operation.
`For writing data to a memory cell, a voltage of 9V for
`example is applied to the control gate CG (word line WL) of
`the memory cell, a voltage of 4V for example is applied to
`the drain region (sub bit line SBL) of the memory cell, a
`voltage of 3V for example is applied to the element forming
`region Ac (p-type well 8), and the source region (source line
`SL) of the memory cell is maintained at, for example, OV
`(earth potential). As a result, not electrons are generated in
`a channel region (source-to-drain region) of the memory cell
`and are injected into the floating gate FG.
`
`[0056] Next, a description will be given of a read opera-
`tion. For reading data from the memory cell, a voltage of
`2.7V for example is applied to the control gate CG (word
`line WL) of the memory cell, a voltage of 0.8V for example
`is applied to the drain region (sub bit line SBL) of the
`memory cell, and the element forming region Ac (p-type
`well 8) and the source region (source line SL) of the memory
`cell are maintained at 0V for example. At this time, data (“1"
`or “0”) of the memory cell is read out in accordance with
`whether an electric current flows or not between the source
`and drain regions of the memory cell. If the answer is
`aflirmative, it is seen that electrons are not injected into the
`floating gate FG of the memory cell (the voltage level is
`below a threshold voltage) and that, for example, “0” data
`has been stored. On the other hand, if no current flows, it is
`seen that electrons are injected into the floating gate FG of
`the memory cell (the voltage level is above the threshold
`voltage) and that, for example, “1” data has been stored.
`
`[0057] A description will not be directed to an erasing
`operation. For erasing data stored in the memory cell, a
`voltage of l0.5V for example is applied to the control gate
`CG (word line WL) of the memory cell, a voltage of 10.5V
`for example is applied to the element forming region Ac
`(p-type well 8) and the drain region (sub bit line SBL) of the
`memory cell, and the source region (source line SL) of the
`memory cell is maintained in a floating state (open state). As
`a result, by FN (Fowler-Nordheim) tunneling, electrons are
`released from the control gate CG to the channel region
`(source-to-drain region) of the memory cell.
`
`[0058] A dummy conductive film DSG is formed in an
`outer periphery portion of the memory cell array by the same
`layer as the control gates CG. The dummy conductive film
`DSG is formed for diminishing the influence of dust par-
`ticles developed during the formation of memory cells and
`for eliminating the diiference in height between the memory
`cell forming region and the peripheral circuit
`forming
`region.
`
`[0059] The dummy conductive film DSG is also formed
`on the element forming regions (p-type wells 8), and also
`between the dummy conductive film DSG and each element
`
`|F’R20l 4-00898
`Exhibit MX027l|-1004, p. 21
`
`Page 00021
`
`Page 00021
`
`
`
`US 2003/0042520 A1
`
`Mar. 6, 2003
`
`forming region Ac are formed an insulating film, e.g., ONO
`film 21, a floating gate (first electrode) FG, and a gate
`insulating film 9, e.g., a thermal oxide film, (see FIGS. 2
`and 3).
`
`[0060] Also in the peripheral circuit forming region are
`formed element forming regions LAC for peripheral circuits.
`On the element forming regions I.Ac is formed a conductive
`film which constitutes gate electrodes G in MlSFE'l‘s S for
`selection. As shown in FIG. 2, the gate electrodes G are
`formed by the same layer as the control gates CG and a gate
`insulating film 9b is formed under the gate electrodes G. In
`the element forming region LAC at both ends of each gate G
`are formed n‘-type semiconductor regions 27 (source and
`drain regions).
`
`[0061] As shown in FIG. 1, the element forming regions
`Ac in the memory cell forming region each extend a length
`D in X direction from the drain region end of the memory
`cell located at an endrnost position. In the length D, the
`distance dl is a distance taking into account a displacement
`of a mask which is used in forming the element forming
`region Ac, while the distance d2 is a distance taking into
`account a crystal defect developing region. In this embodi-
`ment, dl is about 0.2 pm and d2 is about 0.3 pm. This
`magnitude of d2 was set on the basis of the fact that the
`length of a crystal defect developed in an element forming
`region Ac during formation of memory cells in accordance
`with the foregoing rule was about 0.3 nm.
`
`[0062] Thus, in this embodiment, since an end portion of
`each element forming region Ac is extended, it is possible to
`avoid the influence of a crystal defect developed in the
`element forming region Ac. Consequently, it is possible to
`diminish the generation of leakage current and hence pos-
`sible to decrease the rate of occurrence of memory cell
`defects.
`
`[0063] More particularly, as shown in FIG. 4, the insu-
`lating film 6 is present between adjacent element forming
`regions Ac and a stress induced by the insulating film 6
`present along the outer peripheries of element forming
`regions Ac is imposed on the regions Ac. Particularly, since
`the insulating film 6 is formed over a wide range in the outer
`periphery portion of the memory cell forming region for the
`purpose of isolation form the peripheral circuit, there occurs
`a stress concentration at end portions of the element forming
`regions Ac. With such a large stress, there occur defects
`(Del, De2) such as dislocation within crystals which con-
`stitute the element forming regions Ac. Leakage current
`occurs through the defects, and if the leakage current
`becomes larger than the operating current of the sense
`amplifier, a defect results as noted earlier.
`
`In this embodiment, however, since end portions of
`[0064]
`the element fonning regions Ac are extended, the defect Del
`does not extend to the region (memory cell array MCAR)
`where substantial memory cells are formed, so that it is
`possible to diminish the leakage current in each memory
`cell.
`
`[0065] On the extended portion of each element forming
`region Ac is formed a dummy conductive film DSG, and
`below the DSG are formed an insulating film, e.g., ONO fihn
`21, a floating gate (first electrode) FG, and a gate insulating
`film 9, e.g., thermal oxide film. Thus, this structure is a
`pseudo memory cell structure, provided a source region is
`
`not present. However, the dummy conductive film DSG is
`not applied with any potential and is in a floating state, so
`that no channel is formed, with no generation of leakage
`current.
`
`In this embodiment, since each element forming
`[0066]
`region Ac is extended by utilizing the space which underlies
`the dummy conductive film DSG, it is possible to take the
`measure against defects without enlarging the memory cell
`forming region.
`
`[0067] Next, an example of a method for manufacturing
`the semiconductor integrated circuit device of this embodi-
`ment will be described below. FIGS. 6 to 12 are sectional
`views of a principal portion of a substrate, showing how to
`manufacture the semiconductor integrated circuit device of
`this embodiment, of which FIGS. 6 to 8 correspond to C-C
`section in FIG. 1 and FIGS. 9 to 12 correspond to D—D
`section in FIG. 1.
`
`[0068] First, as shown in FIG. 6, a semiconductor sub-
`strate 1, which is formed by a p-type single crystal silicon
`having a resistivity of 1 to 10 Qcm or so,
`is thermally
`oxidized to form a pad oxide film (not shown) on the surface
`of the semiconductor substrate 1. Next, an insulating film,
`e.g., silicon nitride film (not shown), is deposited on the pad
`oxide film, and the silicon nitride fihn present on an element
`isolation region is removed using a photoresist film (simply
`“resist film" hereinafter) as mask.
`
`[0069] Next, the resist film is removed and the semicon-
`ductor substrate 1 is etched using the silicon nitride film as
`mask to form element isolation trenches 4 having a depth of
`about 250 nm.
`
`[0070] Thereafter, the semiconductor substrate 1 is sub-
`jected to dry oxidation at about 1150° C. to form a thermal
`oxide film such as a silicon oxide film 5 having a thickness
`of about 30 nm on inner walls of the trenches. The silicon
`oxide film 5 is formed for remedying damages caused by dry
`etching on the inner walls of the trenches and for relieving
`stress induced at the interface between a silicon oxide film
`6 to be buried within the trenches in the next step and the
`semiconductor substrate 1.
`
`[0071] Next, an insulating film constituted by a silicon
`oxide film 6 having a thickness of about 600 nm for example
`is deposited on the semiconductor substrate 1 including the
`interiors of the element isolation trenches 4 by CVD, fol-
`lowed by heat-treatment (annealing) at 1150" C. for 60
`minutes to densify the silicon oxide film 6. Then, the silicon
`oxide film 6 present on the trenches is polished by CMP to
`flatten the film surface and thereafter the silicon nitride film
`is removed. At this time, the surface of the silicon oxide film
`6 projects from the surface of the semiconductor substrate 1
`by an amount corresponding to the thickness of the silicon
`nitride film, but the surface of the silicon oxide film 6 will
`retract gradually by subsequent washing step for the semi-
`conductor substrate 1 and surface oxidation and oxide film
`removing step.
`
`[0072] Through the above steps there is formed an element
`isolation region with silicon oxide film 6 buried within the
`element isolation trenches 4.
`
`the surface of the
`[0073] Next, as shown in FIG. 7,
`semiconductor substrate 1 is subjected to wet washing and
`thereafter the semiconductor substrate 1 is thermally oxi-
`
`lPR2014-00898
`Exhibit MX027l|-1004, p. 22
`
`Page 00022
`
`Page 00022
`
`
`
`US 2003/0042520 Al
`
`Mar. 6, 2003
`
`dized for example to form an insulating film such as a
`through oxide film (not shown). Then, a p-type impurity
`(boron for example) is ion-implanted into the semiconductor
`substrate 1, followed by heat treatment to diffuse the impu-
`rity, thereby forming p-type Wells 8 in the memory cell
`forming region. The regions where the p-type wells 8 are
`exposed to the surface of the semiconductor substrate 1
`serve as element forming regions Ac. Also in the peripheral
`circuit forming region is formed an element forming region
`I.Ac in the same manner.
`
`[0074] Next, a thermal oxide film having a thickness of
`about 8 nm for example is formed on the surface of each
`p-type well 8 by thermal oxidation (pre-oxidation), thereaf-
`ter the thermal oxide film is removed and the surface of the
`semiconductor substrate 1 (p-type wells 8) is made clean,
`followed by heat treatment to form a thermal oxide film
`having a thickness of about 10.5 nm for example. This
`thermal oxide film constitutes a gate insulating film of a
`non-volatile memory cell.
`
`[0075] Next, a conductive film such as a phosphorus-
`doped polycrystalline silicon film 10 having a thickness of
`about 100 nm for example is deposited on the gate insulating
`film