IPR2014-00898
`U.S. Patent No. 7,151,027
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`Attorney Docket No
`110900-0004-657
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`___________________________________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`___________________________________
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`MACRONIX INTERNATIONAL CO., LTD., MACRONIX ASIA LIMITED,
`MACRONIX (HONG KONG) CO., LTD. and MACRONIX AMERICA, INC.
`Petitioners
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`v.
`
`SPANSION LLC
`Patent Owner
`
`___________________________________
`
`Case No. IPR2014-00898
`Patent Number 7,151,027
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`Before the Honorable HOWARD B. BLANKENSHIP, DEBRA K. STEPHENS,
`KRISTEN L. DROESCH, JUSTIN T. ARBES, and RICHARD E. RICE,
`Administrative Patent Judges.
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`PATENT OWNER’S PRELIMINARY RESPONSE
`UNDER 37 C.F.R. § 42.107
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`U.S. Patent No. 7,151,027
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`Attorney Docket No
`110900-0004-657
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`___________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`___________________________________
`
`MACRONIX INTERNATIONAL CO., LTD., MACRONIX ASIA LIMITED,
`MACRONIX (HONG KONG) CO., LTD. and MACRONIX AMERICA, INC.
`Petitioners
`
`v.
`
`SPANSION LLC
`Patent Owner
`
`___________________________________
`
`Case No. IPR2014-00898
`Patent Number 7,151,027
`
`Before the Honorable HOWARD B. BLANKENSHIP, DEBRA K. STEPHENS,
`KRISTEN L. DROESCH, JUSTIN T. ARBES, and RICHARD E. RICE,
`Administrative Patent Judges.
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`PATENT OWNER’S PRELIMINARY RESPONSE
`UNDER 37 C.F.R. § 42.107
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`IPR2014-00898
`U.S. Patent No. 7,151,027
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`Attorney Docket No
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`TABLE OF CONTENTS
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`Introduction .................................................................................................................... 1
`I.
`Summary of the ’027 Patent ......................................................................................... 5
`II.
`III. Claim Construction ....................................................................................................... 8
`A.
`“etching said poly-1 layer and said poly-2 layer proximate to said
`memory array” (claim 8) ................................................................................. 10
`IV. There Is No Reasonable Likelihood Petitioner Would Prevail on Its
`Contention that Yuzuriha, in View of Tsukamoto and Lin, Discloses the
`Recited “Same Height” Limitations of Claims 7 and 14 ....................................... 14
`A.
`Petitioner Has Failed to Demonstrate Motivation to Apply Yuzuriha’s
`Teachings That Are Directly Contrary to the ‘027 Patent’s Stated
`Purpose .............................................................................................................. 14
`Petitioner Has Failed to Demonstrate Motivation to Apply Tsukamoto’s
`Teachings Directed to a Structure That Is Not Located at the Required
`“Interface” ............................................................................................................ 20
`Tsukamoto Fails to Disclose the Required “Same Height” Limitation of
`Claims 7 and 14 ................................................................................................ 24
`Petitioner Has Failed To Demonstrate Motivation To Combine
`Tsukamoto and Lin with Yuzuriha ............................................................... 28
`Conclusion .................................................................................................................... 32
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`V.
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`B.
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`C.
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`D.
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`IPR2014-00898
`U.S. Patent No. 7,151,027
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`Attorney Docket No
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`Pursuant to 37 C.F.R. § 42.107, 1 Patent Owner Spansion LLC submits this
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`Preliminary Response to the above-captioned Petition for Inter Partes Review of U.S.
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`Patent No. 7,151,027 (“Pet.,” Paper 2).
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`I.
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`Introduction
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`On its face, Petitioner’s2 submission, like its prior petition attempting review of
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`these claims, fails to provide the Board with basic evidence required to institute an
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`inter partes review of claims 7 and 14 of the ‘027 Patent. If the Board nonetheless
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`institutes trial on either of the challenged claims, Patent Owner will address in detail
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`in its § 42.120 Response the numerous substantive errors and shortcomings that
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`underlie each of Petitioner’s arguments and its purported evidence. In this paper,
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`however, where Patent Owner is not permitted to submit expert testimony (Rule
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`§ 42.107(c)), Patent Owner addresses only the meaning of certain of the challenged
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`claims’ pertinent terms, and some fundamental shortcomings of the Petition under
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`Rule § 42.107: in particular, Petitioner’s failure to demonstrate, as to either of the
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`challenged claims, a reasonable likelihood of success on any asserted ground of
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`1 All emphasis herein is added, and all statutory and regulatory citations are to either
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`35 U.S.C. or 37 C.F.R., as the context indicates, unless otherwise stated.
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`2 Macronix International Co., Ltd., Macronix Asia Limited, Macronix (Hong Kong)
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`Co., Ltd., and Macronix America, Inc. are collectively referred to herein as “Petitioner.”
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`invalidity. Because of this clear threshold failure, as before, the Petition should be
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`denied and no inter partes review should be instituted under 35 U.S.C. § 314.
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`The challenged patent, U.S. Patent No. 7,151,027 (“the ’027 Patent”), relates to
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`methods for reducing the area of the interface between the memory array and
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`periphery in memory devices, which also increases manufacturing yield by reducing
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`the risk of potentially damaging stringer spacers during the fabrication process. See
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`MX027II-1001 at 1:7-9; 1:66-2:12. The ’027 Patent has two independent claims and
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`twelve dependent claims. Petitioner has separately challenged various of these claims
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`in a separate proceeding, IPR2014-00108, in which the Board instituted trial on
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`certain claims but denied them as to claims 7 and 14, which Petitioner tries again to
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`challenge here. Independent claims 1 and 8 are directed to methods of fabricating a
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`memory device including steps to fabricate a polysilicon structure at the interface
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`between a memory array and a periphery. The challenged claims—dependent claims 7
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`and 14, which depend on claims 1 and 8 respectively—require that the structure at the
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`interface must be the same height as the memory array proximate to the memory
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`array and the same height as the periphery proximate to the periphery, such that step
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`size is smoothed out, reducing the occurrence of stringers from spacer etching.
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`To justify institution of an inter partes review, Petitioner’s papers must make a
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`prima facie showing that, as a factual and legal matter for its single asserted ground, it
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`has a reasonable likelihood of proving at least one challenged claim unpatentable. See,
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`2
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`e.g., 37 C.F.R. § 42.108(c); 35 U.S.C. § 314; 77 Fed. Reg. 48680, 48694 (Aug. 14, 2012).
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`But it is apparent even from Petitioner’s own arguments and evidence that it cannot
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`meet that burden.
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`Petitioner’s sole contention in its latest Petition is that a triple combination of
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`Yuzuriha (US 6,458,655), Tsukamoto (US 2003/0042520) and Lin (C.-F. Lin, et al., A
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`ULSI shallow trench isolation process through the integration of multilayered dielectric process and
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`chemical-mechanical planarization) renders obvious dependent claims 7 and 14. This
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`Board has already concluded in its Institution Decision (“ID”) in IPR2014-00108
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`(Paper 16) that Yuzuriha in view of additional prior art urged by Petitioner fails to
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`render obvious at least the “same height” limitations of claims 7 and 14. ID at 27-29.
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`And as addressed in more detail below, the addition of Tsukamoto and Lin simply
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`does not cure this deficiency. In particular, Petitioner attempts to add to Yuzuriha
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`Tsukamoto’s disclosure of a structure located in the memory array—i.e., not at the
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`required “interface between a memory array and a periphery of [the] memory device”—to disclose
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`the “same height” limitation, but provides no evidence or explanation to show why a
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`person of ordinary skill in the art would have been motivated to apply this teaching to
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`Yuzuriha’s structure located outside the memory array when the stated purpose of
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`Tsukamoto’s structure is to diminish defects in the memory array. Moreover,
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`Tsukamoto in fact fails to disclose that the asserted structure is the “same height” as
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`the memory array proximate to the memory array and the “same height” as the
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`periphery proximate to the periphery. Quite to the contrary, Tsukamoto discloses
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`that the height of the asserted structure is different, at least with respect to the
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`“periphery proximate to said periphery,” and thus—even as Petitioner imagines it—
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`the proposed combination fails to meet the requirements of the challenged claims.
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`Finally, Petitioner and its expert fail to establish that a person of ordinary skill in the
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`art would have been motivated to substitute the teachings of Tsukamoto and Lin,
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`both directed to types of Shallow Trench Isolation (STI) technologies, for the
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`“standard” LOCOS isolation technology already used in Yuzuriha (Pet. 22),
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`particularly as—according to Petitioner’s own references—the use of LOCOS
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`isolation has “persisted” in the art because of certain disadvantages (e.g., increased
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`processing and complexities) known to be associated with STI. Petitioner’s effort to
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`stitch together disparate fragments of the prior art—like words torn from newspapers
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`for a ransom note—to mimic the invention of the ‘027 patent, using the ‘027 as a
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`hindsight roadmap, clearly fails. See Kinetic Concepts, Inc. v. Smith & Nephew, Inc., 688
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`F.3d 1342, 1368 (Fed. Cir. 2012) (“[W]e must still be careful not to allow hindsight
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`reconstruction of references to reach the claimed invention without any explanation
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`as to how or why the references would be combined to produce the claimed
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`invention.”) (internal citation omitted). Petitioner cannot meet its basic burden for
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`institution.
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`4
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`The very purpose of the § 314 threshold is to avoid the empty, wasteful
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`exercise Petitioner asks this Board to commence, now for the second time in seven
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`months, and Petitioner should be denied trial on these unsupported grounds because
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`the Petition on its face fails to show a reasonable likelihood of success.
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`II.
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`Summary of the ’027 Patent
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`As discussed in the ’027 Patent, “[o]ne important goal of the semiconductor
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`industry is to reduce the size of memory devices. In reducing the size of operational
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`components (e.g., a memory array) and periphery components, an important
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`consideration is the interface between the operational components and periphery
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`components.” MX027II-1001 at 1:18-23. This arrangement is illustrated in Figure 2
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`of the ’027 patent, where a memory device 200 includes the periphery components,
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`labeled 210, the memory array, labeled 220, and a portion of the interface, labeled 230.
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`MX027II-1001 at FIG 2.
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`Memory devices contain millions of components made up of complex
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`structures fabricated by the repeated deposition of layers on a silicon substrate, or
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`wafer. MX027II-1001 at 1:13-18. Typical fabrication methods common in
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`semiconductor fabrication prior to the invention of the ’027 Patent for forming
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`memory devices typically formed the operational components and periphery
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`components separately. Id. at 1:25-26. In other words, when the periphery
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`components were formed, only the periphery was etched (i.e., the memory was
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`masked, or protected from being etched), and when the memory array was formed,
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`only the memory array was etched (i.e., the periphery was masked, or protected from
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`being etched). For various reasons, by using these different processes, a number of
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`steps having different heights at the interface were created. Id. at 1:24-31. Figure 1 in
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`the ’027 Patent depicts what a step at the interface may look like using these prior art
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`methods. Id. at FIG 1.
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`Figure 1 shows interface 100 and substrate 110 etched leaving structures 115
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`and 120. Notably, structure 120 is higher than structure 115—a difference that is
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`difficult to control because of the different processes being used. MX027II-1001 at
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`1:34-42.
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`As the ’027 Patent further describes, a common occurrence during the
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`formation of sidewall spacers was the formation of potentially damaging stringer
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`spacers at these steps. Id. at 1:47-51. These stringer spacers 130 may be easily peeled
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`from the device and displaced to other locations on the device, resulting in yield loss
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`of performance by the memory array. Id. at 1:45-53; FIG 1.
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`The successful invention described and claimed in the ’027 Patent provides a
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`solution to this problem by providing methods for forming a polysilicon structure at
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`the interface between the memory array and the periphery where steps with different
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`heights may be formed. See id. at 2:57-3:2. In so doing, the methods of the ’027
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`Patent reduce the formation of stringer spacers and allow for a reduction in the
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`number of processing steps, cycle time, cost and yield loss. See id. In particular, the
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`interface structure is the same height as the memory array proximate to the memory
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`array and the same height as the periphery proximate to the periphery, such that step
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`size is smoothed out, reducing the occurrence of stringers from spacer etching. See id.
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`at 5:30-35.
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`III. Claim Construction
`Petitioner concedes, as it must, that for purposes of inter partes review “[a] claim
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`in an unexpired patent shall be given its broadest reasonable construction in light of
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`8
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`the specification of the patent in which it appears.”3 37 C.F.R. § 42.100(b); see Pet. 4.
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`While claim terms “are generally given their ordinary and customary meaning,” which
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`is “the meaning that the term would have to a person of ordinary skill in the art in
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`question at the time of the invention,” see, e.g., Phillips v. AWH Corp., 415 F.3d 1303,
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`1312-13 (Fed. Cir. 2005); Pet. 4, the construction must also be consistent with the
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`specification, and the claim language should be read in light of the specification as it
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`would be interpreted by one of ordinary skill in the art. See, e.g., In re Suitco Surface, Inc.,
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`603 F.3d 1255, 1260 (Fed. Cir. 2010).
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`The Board has already construed certain terms in the claims of the ‘027 Patent
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`that Petitioner acknowledges “are not germane to this petition.” Pet. 4, fn. 1. The
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`Board agreed with Patent Owner that “poly-2 layer” (claims 1 and 8) should be
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`construed to mean “a polysilicon layer deposited later in time than a first polysilicon
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`layer.” ID at 8; MX027II-1001 at 5:11-20. And the term “poly-1 layer” (claims 2, 6
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`and 8) was construed to mean “a first polysilicon layer.” ID at 9.
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`However, Petitioner improperly (a) injects claim construction arguments
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`regarding a claim term—“stacked gate etch” of claim 9—that is not at issue in this
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`proceeding (Pet. 5), and (b) rehashes the same claim construction arguments it made
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`in the prior ‘027 Petition regarding the claim term “such that step size is smoothed
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`3 Petitioner further acknowledges that a different standard is applicable to other
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`proceedings. (Pet. 4).
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`9
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`out reducing an occurrence of stringers from spacer etching” (Pet. 5-6; IPR2014-
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`00108 Pet. at 5-6), despite the Board’s conclusion that “no other terms in the
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`challenged claims need[ed] to be construed” for purposes of institution. ID at 12.
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`While reserving further discussion of claim construction as may be appropriate
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`for its § 42.120 Patent Owner Response4 if any trial is instituted, or as may arise in
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`another proceeding for claim terms that are not at issue in this proceeding, Patent
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`Owner notes here as a preliminary matter some of Petitioner’s more egregious
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`violations of these basic principles of claim construction.
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`A.
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`“etching said poly-1 layer and said poly-2 layer proximate to said
`memory array” (claim 8)
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`Petitioner argues that the claim term “etching said poly-1 layer and said poly-2
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`layer proximate to said memory array” recited in claim 8 does not require a single
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`etching step because it was “common practice to perform etching steps…using
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`multiple process steps and multiple etching gases.” Pet. 5. While in its Institution
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`Decision in IPR2014-00108 the Board reached a preliminary view of this term similar
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`to Petitioner’s, this was on an incomplete record, and without the benefit of Patent
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`Owner’s expert testimony about how this term would be understood by a person of
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`ordinary skill in the art (testimony which Patent Owner will provide in its § 42.120
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`4 Again, unlike this preliminary response, Patent Owner’s § 42.120 response may
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`present supporting expert testimony. Cf., e.g., 37 C.F.R. §42.107(c).
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`10
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`response in IPR2014-00108, and, if instituted, in this proceeding). Moreover, Patent
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`Owner respectfully submits this is incorrect from a reading of the specification itself.
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`As Patent Owner noted in its Preliminary Response in the IPR2014-00108 Case,
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`the plain language of the claims require that both the “said poly-1 layer and said poly-
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`2 layer” are etched in a single “etching” step. IPR2014-00108, Prelim. Resp. (Paper
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`14) at 15. Indeed, Patent Owner further notes, as a preliminary matter, that claim 8’s
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`explicit recitation of “etching said poly-1 layer and said poly-2 layer proximate to
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`said memory array” as a single “etching” step of the claimed method, stands in
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`contrast to the ‘027 Patent’s separate recitation, in various other claims, of multiple
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`distinct “etching” steps. See, e.g., Claims 2, 3, 8. For example, claim 1 does not recite
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`“etching said poly-2 layer proximate to said memory array and proximate to said
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`periphery...” Instead, it recites “etching said poly-2 layer proximate to said memory
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`array; and etching said poly-2 layer proximate to said periphery...” Moreover, claim
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`8’s recitation of a single “etching” step for both “said poly-1 layer and said poly-2
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`layer proximate to said memory array” stands in direct contrast to claims 1 and 2, which
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`recite the etching of poly-1 layer and the etching of the poly-2 layer as two separate
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`steps: “etching said poly-2 layer proximate to said memory array” in claim 1 and,
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`subsequently, in claim 2, “etching said poly-1 layer proximate to said memory array.”
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`See CAE Screenplates, Inc. v. Heinrich Fiedler GmbH & Co., 224 F.3d 1308, 1317 (Fed. Cir.
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`2000) (“In the absence of any evidence to the contrary, we must presume that the use
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`of…different terms in the claims connotes different meanings.”).
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`Moreover, contrary to Petitioner’s distortion of the ‘027 Patent’s claimed
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`process (Pet. 5, 7-9), the ‘027 Patent explicitly describes the etching of the poly-1 layer and poly-
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`2 layer proximate to the memory array as a single etching “step” (“step 440”) in its process.
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`This is clearly illustrated in, for example, the ‘027 Patent’s Figure 4. See, e.g.,
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`MX027II-1001 at Fig. 4 (highlights in orange):
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`And it is confirmed in the text of the ‘027 Patent, which states: “At step 440, the
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`poly-1 layer and the poly-2 layer are etched proximate to the memory array. In one
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`embodiment, the etching is accomplished by performing a stacked gate etch.”
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`MX027II-1001 at 5:21-24.
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`The ‘027 Patent further states: “With reference next to FIG. 3E, in the present
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`embodiment, a known process (such as a stacked gate etch) is used to etch a
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`portion of poly-1 310 a, dielectric material 315, and poly-2 320 proximate to the
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`memory array.” Id at 4:27-30, Fig. 3D & 3E:
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`Thus, the ‘027 Patent makes clear that claim term “etching said poly-1 layer
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`13
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`and poly 2 layer proximate to said memory array” in claim 8 means what it says: these
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`two layers are etched in a single etching step.
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`IV. There Is No Reasonable Likelihood Petitioner Would Prevail
`on Its Contention that Yuzuriha, in View of Tsukamoto and Lin,
`Discloses the Recited “Same Height” Limitations of Claims 7 and 14
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`Petitioner advances Yuzuriha as the base reference in its sole asserted ground.
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`Pet. 3. But a person of ordinary skill would not have applied Yuzuriha’s teachings to
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`arrive at the invention of the challenged ‘027 Patent claims because, inter alia, the type
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`of isolation and structure it teaches at the alleged interface in Yuzuriha increases the
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`height and area of the interface and is designed, by Petitioner’s own description, to
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`“result in ‘a gentle step’” (Pet. 17)—and thus Yuzuriha leads to the very problems the ‘027
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`patent seeks to avoid. Moreover, as with Petitioner’s prior attempt to combine Yuzuriha
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`with other prior art (see, e.g., ID at 22-29 (rejecting combination with Nakagawa)),
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`Yuzuriha even in view of additional prior art—including the Tsukamoto and Lin
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`references now urged by Petitioner—fails to disclose or render obvious at least the
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`“same height” limitations of Claims 7 and 14, and this is fatal to Petitioner’s
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`arguments.
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`A.
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`Petitioner Has Failed to Demonstrate Motivation to Apply
`Yuzuriha’s Teachings That Are Directly Contrary to the ‘027
`Patent’s Stated Purpose
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`As Petitioner and its own witness acknowledge, “the ’027 Patent is intended
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`to reduce the interface area of a memory device...” MX027II-1002 at ¶ 13;
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`IPR2014-00108, Pet. 7; MX027II-1001 2:57-59. For example, the ‘027 Patent is
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`14
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`entitled “Method and device for reducing interface area of a memory device,” and
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`describes forming a polysilicon structure at the interface between the memory array
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`and the periphery of a memory device that is “operable to smooth out any steps
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`caused by etching” and eliminate the creation of “stringer spacers.” MX027II-1001 at
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`2:62-66. In particular, the ‘027 Patent states that an intended goal is to avoid the use of
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`methods that would require “additional area of the interface,” such as the use of a
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`salicide block, that would “considerably limit[] the ability to reduce the size of the
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`interface area.” Id. at 1:54-62; 2:66-3:2.
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`Yuzuriha, on the other hand, is directed to “prevent[ing] an altered surface
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`layer of a resist from being removed” during a “dry-etch and wet-etch.” MX027II-
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`1003 at Abstract. The “Tenth Embodiment” of Yuzuriha relied upon by Petitioner
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`describes that the “process performed to prevent removal of the altered surface layer
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`of the resist” allows a poly-poly insulation film (11) to recede “closer to the memory
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`cell region” than a conventional process. Id. at 12:30-37, Figs. 7-8:
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`As a result, instead of an “abrupt” step variation, a “gentle” step results when a
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`“dummy gate 14” is subsequently formed. Id. at 37-52, Fig. 9:
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`Importantly, Yuzuriha’s explicit goal of “resulting in a gentle step” at the
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`alleged interface area, is directly contrary to the “intended result of the claimed [‘027]
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`process” acknowledged by Petitioner (Pet. 5), which as expressly recited in claims 7
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`and 14, is achieving the “same height” at the interface area, “such that step size is
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`smoothed out reducing an occurrence of stringers from spacer etching.”
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`Moreover, unlike the ‘027 Patent, which describes forming the interface
`
`structure on, e.g., a “shallow trenched” isolation area that results in the structure
`
`having the “same height” as the periphery and memory array (MX027II-1001 at 3:51-
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`52; 4:49-54; 5:30-35), Yuzuriha describes, in contrast, forming the asserted “dummy
`
`gate” on an “isolating oxide film 8” that, as disclosed in, e.g., Figs. 5-10 of Yuzuriha, is
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`raised above the silicon substrate surface as compared to the structures in the alleged
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`memory array and periphery. MX027II-1003 at 11:52-54; Fig. 5:
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`
`
`17
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`
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`IPR2014-00898
`U.S. Patent No. 7,151,027
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`Attorney Docket No
`110900-0004-657
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`
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`Indeed, as the Board noted, Petitioner’s witness concedes that “[a]ny difference
`
`in height in the dummy gate of [Yuzuriha’s] Figure 5 result from the fact that the dummy
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`gate is shown on top of ‘isolating oxide film 8…’” ID at 27 (citing MX027-1002 at ¶ 129);
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`MX027II-1002 at ¶ 57. Petitioner and its witness further acknowledge that the
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`resulting “gentle step” in the dummy gate region would “suggest[] to a person of
`
`ordinary skill in the art” that “the ‘isolating oxide film 8,’ may be formed using a
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`process such as ‘local oxidation of silicon,’ or LOCOS.” Pet. 17 (citing MX027II-1002,
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`¶¶ 58 (“Fig. 5 shows the dummy gate region on the thick isolation oxide based on the
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`then prevalent LOCOS technology”), 59).
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`As depicted in Figure 5 of Yuzuriha, the raised “isolating oxide film 8” not only
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`contributes to Yuzuriha’s goal of a “resulting…gentle step” but also increases the
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`height of the “dummy gate 14” as compared to the memory cell and peripheral
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`
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`18
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`IPR2014-00898
`U.S. Patent No. 7,151,027
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`circuitry regions (cf. Pet. 12, 17), and increases the area of the alleged interface area (i.e.,
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`Attorney Docket No
`110900-0004-657
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`the “dummy gate region”) (see, e.g., MX027II-1007 at 468 (left column, discussing
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`“problems with LOCOS,” including “lateral encroachment of field oxide,” as “set[ting]
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`the limitations for the utilization of this technology” in terms of size))—the very
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`problems the ‘027 Patent seeks to avoid. Thus, Petitioner and its witness have simply
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`failed to demonstrate that a person of ordinary skill in the art would have been
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`motivated to apply Yuzuriha to address the problems to which the ‘027 Patent is
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`directed, particularly in light of the ‘027 Patent’s expressly stated goals to “smooth out
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`any steps” and avoid the use of methods that would require “additional area of the
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`interface” and “limit[] the ability to reduce the size of the interface area.” MX027II-
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`1001 at 5:45-46; 1:54-62; 2:66-3:2.
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`Recognizing that Yuzuriha would have been recognized by a person of
`
`ordinary skill in the art as fundamentally inapposite to the problem addressed by the
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`‘027 patent, Petitioner sets out to rewrite it, making at least two fundamental changes
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`to Yuzuriha: “(1) [to] use a planarized oxide isolation area such as a shallow trench
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`isolation area to isolate the memory array and the periphery [instead of LOCOS], and
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`(2) to include a dummy gate structure that eliminates ‘the difference in height between
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`the memory cell forming region and the peripheral circuit forming region.’” Pet. 21.
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`However, as discussed further below, these asserted modifications are incompatible
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`with, and indeed directly undermine, the stated purpose of Yuzuriha, and a person of
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`19
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`IPR2014-00898
`U.S. Patent No. 7,151,027
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`ordinary skill in the art would not have been motivated or found it obvious to remake
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`Attorney Docket No
`110900-0004-657
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`Yuzuriha as Petitioner contends.
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`B.
`
`Petitioner Has Failed to Demonstrate Motivation to Apply
`Tsukamoto’s Teachings Directed to a Structure That Is Not
`Located at the Required “Interface”
`
`In an attempt to paper over Yuzuriha’s deficiencies, Petitioner relies on
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`Tsukamoto’s disclosure of a structure formed at the “outer periphery portion of the
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`memory cell array” in an attempt to satisfy the “same height” requirements of claims
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`7 and 14. Pet. 19. As described in Tsukamoto, this structure is a “pseudo memory
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`cell structure” that comprises (1) a “dummy conductive film DSG,” (2) an “ONO
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`film 21,” (3) a “floating gate FG,” and (4) a “gate insulating film 9.” MX027II-1004 at
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`¶ [0065]. Petitioner further contends that this structure is “analogous” to the
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`“dummy gate region” of Yuzuriha. Pet. 21.
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`To begin with, a person of ordinary skill in the art reading Yuzuriha would
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`have found no reason to modify it to achieve the “same height” requirements of
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`claims 7 and 14 of the ‘027 Patent because, as discussed above, and as Petitioner itself
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`asserts, Yuzuriha taught as its goal not achieving the same height but, to the contrary,
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`achieving a “gentle step” at the interface. See, e.g., Pet. 17 (“Yuzuriha discloses…that
`
`the interface structure is designed to result in ‘a gentle step’ resulting in improvements
`
`in further photolithographic steps.”), 23 (“Yuzuriha…alludes to such advantages by
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`the formation of a ‘gentle step’ which improves subsequent processing steps.”).
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`20
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`IPR2014-00898
`U.S. Patent No. 7,151,027
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`Moreover, even if a person of ordinary skill were—contrary to Yuzuriha’s basic
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`Attorney Docket No
`110900-0004-657
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`teachings—to look beyond Yuzuriha to Tsukamoto for teachings about heights of
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`structures in the claimed interface region, Tsukamoto would not supply the teachings
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`that Petitioner argues: Petitioner’s reliance on Tsukamoto’s “pseudo memory cell
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`structure” is misplaced because this structure is not located at the “interface between a
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`memory array and a periphery of [the] memory device” as required by claims 7 and 14.5 To the
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`contrary, Tsukamoto discloses that the “pseudo memory structure” including the
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`“DSG” film is formed in the “memory
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