_
`
`United States Patent [19]
`Bergemont
`
`USOO5371030A
`
`[11] Patent Number:
`[45] Date of Patent:
`
`5,371,030
`* Dec. 6, 1994
`
`[54] METHOD OF FABRICATING FIELD OXIDE
`ISOLATION FOR A coNTAcrLEss FLASH
`EPROM CELL ARRAY
`
`-
`,
`J
`M. B
`A1
`f.
`1
`t
`I
`75
`be"
`ergemont’ San ose Call
`nven or
`[
`1
`[73] Assignee: National Semiconductor Corporation,
`S ta 1
`, Cal'f.
`an C an
`1
`The portion of the term of this patent
`Subsequent to Aug 31, 2010 has been
`disclaime¢
`
`[ *] Notice:
`
`[21] Appl. No.: 9,330
`
`[22] Filed:
`
`Jan. 26, 1993
`
`Related US Application Data
`
`[62]
`
`_
`_
`‘
`Dlvlslon of Sen NO- 687,105, Apr- 13, 1991, aban'
`doned'
`
`3; ac‘: """"""""""""""""""""
`. .
`. ...................................... ..
`.
`[58] Field of Search ............................ .. 437/43, 48, 52
`-
`References cued
`U.S. PATENT DOCUMENTS
`
`, 437/48,
`
`[56]
`
`FOREIGN PATENT DOCUMENTS
`0152673 1/1989 Japan ................................... .. 437/43
`
`Prz'ma Ex'aminer—Tom Thomas
`,
`W
`Attorney, Agent, or Firm-Limbach & Limbach
`[57]
`ABSTRACT
`A method of forming a contactless EPROM cell inl
`C9965 an initial SteR of forming an N+ source line in a
`SlllCOl'l substrate. Flrst and second N+ drain 111168 are
`then formed in parallel with and spaced-apart from the
`source line on opposite sides of the source line. First and
`second ?eld oxide strips are formed in parallel with, but
`spaced-apart from the ?rst and second drain lines, re
`spectively, such that the source line/drain line structure
`is bounded on both sides by the ?rst and second ?eld
`oxide strips to separate the structure from adjacent
`source/drain line structures. First and second poly l
`lines overly the channel regions between the ?rst drain
`line and the source line and the second drain line and the
`source line respectively, and are separated therefrom by
`' a ?rst layer of dielectric material. A plurality of spaced
`apart’ p a1, an 81 Poly 2 word lines overly and run perpem
`dicular to the ?rst and second poly 1 lines and are
`Spaced_apart therefrom by a Second dielectric mat e ri a1.
`Thus, the method results in an EPROM array having
`cells that are de?ned at each crossing of the poly 1 lines
`and the poly 2 word 1ines_
`
`5,081,056 l/ 1992 Mazzali et al. ...................... .. 437/43
`5,100,819 3/1992 Gill et a]. ............................ .. 437/43
`
`3 Claims, 6 Drawing Sheets
`
`INTERPOLY OXIDE
`
`POLY 2 WORD UNE
`
`POLY 1
`
`IPR2014-00898
`Exhibit MX027II-1010, p. 1
`
`

`
`I U.S. Patent
`
`Dec. 6, 1994
`
`Sheet 1 of 6
`
`5,371,030 _
`
`
`
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`-IE’/AZIEZQIV/ZZZIEEIZ
`
`PRIOR ART
`
`FIG.
`
`1
`
`|PR2014—00898
`Exhibit MX027||—1010, p. 2
`
`.
`
`IPR2014-00898
`Exhibit MX027II-1010, p. 2
`
`

`
`US. Patent
`
`Dec. 6, 1994
`
`Sheet 2 of 6
`
`5,371,030
`
`POLYI
`
`1s
`
`18
`
`POLY 2 WORD LINE
`
`METAL BIT UNE
`
`POLY 1
`
`POLY 2 WORD UNE
`
`III"8 [:I
`yN-III \N+) \N-I-KII
`ru
`12 \__J
`12
`20 DRAIN
`DRAIN
`
`THIN OXIDE
`
`PRIOR ART
`FIG. 3
`
`IPR2014-00898
`Exhibit MX027II-1010, p. 3
`
`

`
`US. Patent
`
`v Dec. 6, 1994
`
`Sheet 3 of 6
`
`5,371,030
`
`Vpp
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`T
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`/
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`DRAIN
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`FIG. 4A
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`SOURCE
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`DRAIN 20
`
`12
`
`IPR2014-00898
`Exhibit MX027II-1010, p. 4
`
`

`
`U.S. Patent
`
`Dec. 6, 1994
`
`Sheet 4 of 6
`
`5,371,030
`
`'fi
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`|PR2014—00898
`Exhibit MX027||—1010, p. 5
`
`IPR2014-00898
`Exhibit MX027II-1010, p. 5
`
`

`
`US. Patent
`
`Dec. 6, 1994
`
`Sheet 5 0f 6
`
`5,371,030
`
`INTERPOLY OXIDE
`
`POLY WORD NE
`2
`u l POLY 1
`
`POLY 1
`
`#8“;
`
`Sic)2
`
`POLY 1
`INTERPOLY OXIDE
`
`SiOz
`
`FIG. 8
`
`POLY 2 WORD LINE M
`
`IPR2014-00898
`Exhibit MX027II-1010, p. 6
`
`

`
`US. Patent
`
`Dec. 6, 1994
`
`Sheet 6 of 6
`
`5,371,030
`
`./ FOX
`
`W
`'> / POLY 1 \
`
`POLY 2
`WORD
`
`Ll/NE
`
`FIG. 9
`
`IPR2014-00898
`Exhibit MX027II-1010, p. 7
`
`

`
`1
`
`METHOD OF FABRICATING FIELD OXIDE
`ISOLATION FOR A CONTACI‘LESS FLASH
`EPROM CELL ARRAY
`
`5,371,030
`2
`regions 14 to prevent disturbances due to band-to-band
`tunneling in the erase mode.
`As shown in FIG. 4A, the ETOX ?ash cell 10 is
`written in the conventional EPROM manner. That is,
`hot electrons are injected from the source region 14 into
`the polysilicon (poly 1) ?oating gate 18 when the poly
`2 word line 16 and the N+ bit line 20 are both high.
`As shown in FIG. 4B, erasing the ETOX cell 10 is
`performed by tunneling electrons from the ?oating gate
`18 through the thin oxide 12 close to the source region
`14 when the source region 14 is high, the drain 20 is
`?oating and the word line 16 is low.
`
`10
`
`This is a divisional of application Ser. No. 687/105,
`?led Apr. 18, 1991.
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The present invention relates to electrically program
`mable read only memory (EPROM) devices and, in
`particular, to a contactless EPROM cell array structure
`which utilizes a ?eld oxide bit line isolation scheme that
`eliminates the requirement for the complex virtual
`ground row decoders normally associated with ?ash
`EPROM arrays.
`2. Discussion of the Prior Art
`An electrically programmable read only memory
`(EPROM) device is a non-volatile memory integrated
`circuit which is used to store binary data. Power can be
`removed from an EPROM without loss of data. That is,
`upon reapplying power, the originally-stored binary
`data is retained.
`In addition to its data retention capability, an
`EPROM can also be programmed to store new binary
`data. Reprogramming is accomplished by ?rst exposing
`the EPROM to an ultra-violet (UV) light source in
`order to erase the old binary data. A UV-transparent lid
`on the packaged EPROM chip allows this erasure to
`occur. Following erasure, the new binary data is writ
`ten into the EPROM by deactivating the chip select line
`in order to switch the EPROM’s data outputs to inputs.
`The EPROM address inputs are then set to a starting
`value, the desired data is connected to the data inputs
`and the data is written into the data storage register
`identi?ed by the address inputs. The address inputs are
`then incremented and the cycle is repeated for each data
`storage register in the EPROM array.
`In an EPROM read operation, the binary data stored
`in the data storage register identi?ed at the address
`inputs is connected to the chip’s data output buffers. If
`the EPROM’s chip select signal is activated, then the
`binary data from the selected storage register is pro
`vided to the databus.
`An electrically erasable programmable read only
`memory (EEPROM) is a variation of the EPROM
`design wherein binary data is read, written and erased
`electrically. A single operation erases the selected data
`storage register. In the case of the so-called “?ash”
`EPROM device, all data storage registers in the mem
`ory array ar electrically erased in a single operation.
`The state of the art of ?ash EPROM cells is repre
`sented by the Intel ETOX cell, which is illustrated in
`FIGS. 1-3. FIG. 1 shows a portion of a typical T
`shaped layout of an ETOX cell array with one drain
`contact 22a sharing two cells. FIG. 2 shows a cross-sec
`tion of an ETOX cell which is taken along line A—A,
`i.e. along a polysilicon (poly 2) word line 16 in the
`portion of the ETOX array illustrated in FIG. 1. FIG. 3
`shows a cross-section of an ETOX cell taken along line
`B—B, i.e. along a N+ bit line in the portion of the
`ETOX array illustrated in FIG. 1.
`As shown in the FIG. 1 layout, and as stated above,
`the ETOX array is based on the standard “T-shaped”
`EPROM cell. As shown in FIGS. 2 and 3, it is im
`plementated utilizing a very thin gate oxide 12 (about
`100A) and graded N+/N— implants in the source
`
`SUMMARY OF THE INVENTION
`A method of forming the above-described contactless
`EPROM cell array comprises the following steps. First,
`parallel, spaced-apart strips of ?eld oxide are formed in
`the silicon substrate. Next, a layer of dielectric material
`is formed on the silicon substrate between the ?eld
`oxide strips. A layer of ?rst polysilicon (poly l) is then
`formed over the layer of ?rst dielectric material. A
`second layer of dielectric material is then formed over
`the poly 1 layer. Next, the sandwich structure compris
`ing the poly 1 and overlying second dielectric material
`is masked and patterned to de?ne ?rst and second poly
`1 lines that are spaced-apart from one another and from
`the adjacent ?eld oxide strips and are separated from
`the substrate by the ?rst dielectric material and have the
`second dielectric material formed thereon. Next, an
`N+ source region is formed in the substrate between
`the ?rst and second poly 1 lines and, simultaneously,
`?rst and second N+ drain regions are formed in the
`substrate between the ?rst poly 1 line and its adjacent
`?eld oxide strip and the second poly 1 line and its adja
`cent ?eld oxide strip, respectively. Next, a differential
`oxide step is performed to grow additional dielectric
`material on the second dielectric material overlying the
`?rst and second poly 1 lines and, simultaneously to
`grow oxide material over the N+ source line and the
`?rst and second N+ drain lines. Next, a plurality of
`spaced-apart parallel-running poly 2 word lines are
`formed overlying and running perpendicular to the ?rst
`and second poly 1 lines and spaced-apart therefrom by
`the second dielectric material and additional dielectric
`material. Finally, a stacked etch step is performed utiliz
`ing the poly 2 word lines to de?ne the ?rst and second
`poly 1 lines as the poly l ?oating gates of the EPROM
`cells of the array. Thus, the oxide formed over the N+
`source lines and the ?rst and second N+ drain lines
`during the differential oxide step protects the N+ sour
`ce/drain lines during the stacked etch step from sub
`strate “digging.” The individual EPROM cells of the
`array are de?ned at the crossing of the poly 2 word lines
`with the underlying poly i ?oating gates.
`A better understanding of the features and advan
`tages of the present invention will be obtained by refer
`ence to the following Detailed Description of the In
`vention and accompanying drawings which set forth an
`illustrative embodiment in which the principles of the
`invention are utilized.
`
`DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a layout drawing illustrating a conventional
`flash EPROM cell, the Intel ETOX cell, with one
`contact to the drain sharing two cells.
`FIG. 2 is a cross-sectional view taken along line
`A—A in FIG. 1.
`
`25
`
`35
`
`45
`
`65
`
`IPR2014-00898
`Exhibit MX027II-1010, p. 8
`
`

`
`5
`
`20
`
`25
`
`30
`
`5,371,030
`4
`3
`interpoly ONO is grown to a thickness of about 300A.
`FIG. 3 is a cross-sectional view taken along line B—B
`The ?rst layer of polysilicon is then masked using pho
`in FIG. 1.
`toresist and the ONO/poly 1 sandwich is etched. The
`FIG. 4A is a cross-sectional view illustrating opera
`photoresist mask is then stripped and the N+ bit lines
`tional voltages for the write mode of the ?ash EPROM
`are implanted, usually utilizing a conventional arsenic
`cell shown in FIGS. 1-3. FIG. 4B is a cross-sectional
`view illustrating operational voltages for the erase
`implant. Following formation of the N+ bit lines, a
`mode of the ?ash EPROM cell shown in FIGS. 1-3.
`differential oxide is grown to a thickness of approxi
`FIG. 5 is a layout illustrating a contactless ?ash
`mately 1000A on the N+ bit lines and to a thickness of
`EPROM cell using a standard row decoder in accor
`approximately 300A on the poly 1. Next, a second layer
`dance with the present invention.
`of polysilicon (poly 2) is deposited and doped in the
`FIG. 6 is a layout of an EPROM array utilizing a
`conventional manner. This poly 2 layer is then masked
`contactless ?ash EPROM cell in accordance with the
`and etched. The ONO is then etched, resulting in the
`present invention.
`thickness of the oxide over the buried N+ bit line drop
`FIG. 7 is a cross-sectional view taken along line
`ping to about 700A. Next, the poly l is etched in a
`A—-A in FIG. 5.
`15
`stacked etch step that utilizes the poly 2 word line to
`FIG. 8 is a cross-sectional view taken along line B—B
`give ?nal de?nition to the poly l ?oating gates. Since
`in FIG. 5.
`the selectivity between poly and silicon dioxide is high
`FIG. 9 is a layout illustrating a “?eld-less” array.
`during the poly l etch, no etching of silicon is possible
`over regions A, B and C in FIG. 9, which regions are
`de?ned between the poly 1 lines and the poly 2 lines.
`Thus, the contactless ?ash EPROM cell of the pres
`ent invention may be arranged in an EPROM array
`which provides for higher packing density than the
`conventional T-shaped ?ash EPROM cell.
`Alternatively, the contactless ?ash EPROM cell con
`cepts described above may be used to form a so-called
`“?eld-less” array, as shown in FIG. 9. A comparison of
`the FIG. 5 array layout and the FIG. 9 ?eld-less layout
`will show that the only difference between the two is
`that, in the FIG. 9 layout, ?eld oxide is not present in
`the cell area. However, the FIG. 6 schematic represen
`tation still applies. That is, the FIG. 9 layout shares a
`graded N+/N — source region with two adjacent
`N+bit lines, these three regions being separated on
`both sides from adjacent similar structures by ?eld ox
`ide. As in the FIG. 5 layout, two poly l ?oating gates
`run perpendicular to the poly 2 word lines that cross the
`separating ?eld oxide regions. Also, again as shown in
`the FIG. 5 array layout, and in accordance with the
`present invention, the differential oxide step described
`above is necessary in fabricating the FIG. 9 layout to
`avoid digging those areas of the N+ lines not protected
`by either poly 1 or poly 2.
`It should be understood that various alternatives to
`the embodiments in the invention described herein may
`be employed in practicing the invention- It is intended
`that the following claims de?ne the scope of the inven
`tion and that within the scope of these claims and their
`equivalents be covered thereby.
`What is claimed is:
`1. A method of forming a contactless EPROM cell
`array structure in a silicon substrate of P-type conduc
`tivity such that the EPROM cell array structure in
`cludes a plurality of shared-source cell segments, the
`method comprising the steps of:
`forming a plurality of parallel, spaced-apart segment
`?eld oxide strips in the silicon substrate such that a
`P-type EPROM cell segment substrate region is
`de?ned between adjacent pairs of segment ?eld
`oxide strips;
`forming a layer of ?rst silicon dioxide on the sell
`segment substrate regions between the segment
`?eld oxide strips;
`forming a layer of ?rst polysilicon (poly 1) over the
`layer of ?rst silicon dioxide;
`forming a layer of oxide-nitride-oxide (ONO) over
`the poly 1 layer;
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`FIGS. 5 and 6 illustrate the layout of a portion of a
`contactless ?ash EPROM cell array 100 in accordance
`with the present invention. As shown in FIG. 5, an
`EPROM cell within the array 100 does not share one
`contact with two cells, as is the case in conventional
`?ash EPROM arrays. Rather, the ?ash EPROM array
`bit lines are contacted every 32, 48 or 64 cells (a so
`called “contactless” array structure).
`As shown in FIGS. 5 and 6, two adjacent cells within
`the array 100 share the same source line S and are sepa
`rated from other cells in the array 100 along the same
`poly 2 word line (not shown in FIG. 6) by ?eld oxide
`(Fox). That is, as best shown in FIG. 6, the separate
`drains D1 and D2 of adjacent cells share a common
`35
`source. Each column of shared-source cells is separated
`from adjacent shared-source cells (e.g., D1’/Dz'-S’ and
`D1"/Dz"-S" in FIG. 6) along the same word line by
`?eld oxide.
`Thus, there is no need for a complex virtual ground
`40
`row decoder which consumes large die area.
`The cell structure shown in FIGS. 5 and 6 uses the
`same write and erase mode operating voltages as the
`ETOX cell illustrated in FIGS. 4A and 4B. Similarly,
`the common source of the cell is twice implanted to
`provide a graded junction to sustain the erasing voltage,
`as shown in FIG. 7.
`As further shown in FIG. 7, a layer of ?rst polysili
`con (poly 1) is maintained over the array ?eld oxide
`separating two adjacent drain regions. This poly 1 layer
`reduces the voltage over the ?eld oxide when the word
`line is at high potential through poly 1 to poly 2 capaci
`tive coupling. This helps to reduce bit line loading by
`decreasing the dopant concentration under the ?eld
`oxide.
`Referring back to FIG. 5, in order to realize a stacked
`etch EPROM cell con?guration utilizing the concepts
`of the present invention described above, the oxide over
`the buried N+ bit lines must be thick enough to avoid
`digging the substrate silicon in regions A, B and C when
`60
`etching the remaining oxide-nitride-oxide (ONO)/poly
`l combination.
`To avoid this digging, in accordance with the present
`invention, and as described below, a module for forma
`tion of a differential oxide over the N+ bit lines is pro
`vided in the process ?ow.
`First, a ?rst layer of polysilicon (poly l) is deposited
`and doped in the conventional manner. Next, a layer of
`
`45
`
`55
`
`65
`
`IPR2014-00898
`Exhibit MX027II-1010, p. 9
`
`

`
`5,371,030
`6
`5
`masking the structure formed in the preceding steps
`of each EPROM cell in said cell segment substrate
`region
`and patterning said structure to de?ne between
`each pair of adjacent segment ?led oxide strips,
`whereby the silicon dioxide over the N+ shared
`?rst and second poly 1 lines that run parallel to and
`source line and the ?rst and second N+ drain lines
`spaced-apart from one another and the adjacent
`in each cell segment substrate region protects said
`segment ?eld oxide stirps and that are separated
`N+ drain lines in each cell segment substrate re
`from the underlying cell segment substrate region
`gion protects said N+ lines during the stacked etch
`by ?rst silicon dioxide and that have ONO formed
`step; and
`thereon;
`whereby EPROM cells are de?ned at each crossing
`in each cell segment substrate region, simultaneously 10
`of a poly 2 word line and an underlying poly l
`forming both an N+ shared-source line in said
`?oating gate.
`substrate region between the ?rst and second poly
`2. A method as in claim 1 and further including the
`1 lines and ?rst and second N+ drain lines in said
`step of, prior to the formation of the layer of ?rst
`substrate region between the ?rst poly 1 line and its
`polysilicon, in each cell segment substrate region, form
`adjacent segment ?eld oxide strip and between the
`ing a plurality of spaced-apart array ?eld oxide regions
`second poly 1 line and its adjacent segment ?eld
`in the silicon substrate, the poly l ?oating gates of each
`oxide strip, respectively;
`EPROM cell and said cell segments substrate region
`performing a differential oxidation step to simulta
`being de?ned to extend between a corresponding pair of
`neously form, in each cell segment substrate re
`said array ?eld oxide regions.
`gion, additional silicon dioxide on the ONO formed
`20
`3. A method as in claim 1 and including the steps of,
`on the ?rst and second poly 1 strips and over the
`in each cell segment substrate region, forming a polysili
`N+ shared-source line and the ?rst and second
`con strip on the adjacent pairs of segment ?eld oxide
`N+ drain lines;
`strips de?ning said cell segment substrate region, the
`in each cell segment substrate region, forming a plu
`poly 2 word lines in said cell segment substrate region
`rality of parallel, spaced-apart word lines of second
`being formed to extend over said polysilicon strips and
`polysilicon (poly 2) overlying and running perpen
`to be separated therefrom by a layer of dielectric mate
`dicular to the ?rst and second poly 1 lines and
`rial;
`separated therefrom by the ONO and the addi~
`whereby capacitive coupling between the polysilicon
`tional silicon dioxide; and
`strips and the word lines reduces voltage over the
`performing a stacked etch step wherein the poly 2
`segment ?eld oxide strips when the word line is at
`word lines are utilized as a self-aligned mask do, in
`a high potential.
`each segment substrate region, pattern the ?rst and
`second poly 1 lines to de?ne a poly 1 ?oating gate
`
`15
`
`25
`
`****
`
`35
`
`45
`
`55
`
`65
`
`IPR2014-00898
`Exhibit MX027II-1010, p. 10