`
`
`
`
`
`In the Matter of
`
`UNITED STATES INTERNATIONAL TRADE COMMISSION
`WASHINGTON, D.C.
`
`Before The Honorable E. James Gildea
`Administrative Law Judge
`
`
`Investigation No. 337-TA-893
`
`CERTAIN FLASH MEMORY CHIPS
`AND PRODUCTS CONTAINING SAME
`
`
`
`SECOND JOINT SUBMISSION REGARDING
`PROPOSED CONSTRUCTION OF DISPUTED CLAIM TERMS
`
`
`
`Complainant Spansion LLC ("Spansion"), Respondents Macronix International Co., Ltd.,
`
`Macronix America, Inc., Macronix Asia Limited, Macronix (Hong Kong) Co., Ltd., Acer Inc.,
`
`Acer America Corporation, ASUSTek Computer Inc., Asus Computer International, Belkin
`
`International, Inc., D-Link Corporation, D-Link Systems, Inc., Nintendo Co., Ltd., Nintendo of
`
`America, Inc. and Netgear Inc. (collectively, "Respondents"), and the Commission Investigative
`
`Staff Attorney ("Staff") (collectively, "the parties") have continued to streamline the issues
`
`regarding claim construction. The parties submit the attached revised joint list showing each
`
`party's proposed construction of the remaining disputed claim terms. The parties have also
`
`expanded the list of agreed-upon constructions, which are set forth in a separate table at the end
`
`of this document.
`
`
`
`
`
`
`
`1
`
`IPR2014-00898
`Exhibit MX027II-1006, p. 1
`
`

`

`
`
`Dated: February 12, 2014
`
`/s/ Paul M. Bartkowski
`Tom M. Schaumberg
`Paul M. Bartkowski
`ADDUCI, MASTRIANI & SCHAUMBERG, LLP
`1133 Connecticut Avenue, N.W.
`Washington, DC 20036
`Telephone: 202.467.6300
`Facsimile: 202.466.2006
`
`Andrew N. Thomases
`Mark D. Rowland
`ROPES & GRAY LLP
`1900 University Avenue, 6th Floor
`East Palo Alto, California 94303
`Telephone: 650.617.4712
`Facsimile: 650.566.4275
`
`Dalila Argaez Wendlandt
`ROPES & GRAY LLP
`800 Boylston Street
`Boston, Massachusetts 02199
`Telephone: 617.951.7884
`Facsimile: 617.235.0551
`
`Counsel for Complainant Spansion LLC
`
`
`
`
`
`SPAN701414.docx
`
`Respectfully submitted,
`
`
`
`
`
`/s/ Thomas L. Jarvis
`Thomas L. Jarvis, Esq.
`WINSTON & STRAWN LLP
`1700 K Street, N.W.
`Washington, DC 20006-3817
`Telephone: 202.282.5000
`Facsimile: 202.282.5100
`
`Counsel for Respondents Macronix
`International Co., Ltd., Macronix America,
`Inc., Macronix Asia Limited, Macronix
`(Hong Kong) Co., Ltd., Acer Inc., Acer
`America Corporation, ASUSTek Computer
`Inc., Asus Computer International, Belkin
`International, Inc., D-Link Corporation,
`D-Link Systems, Inc., Nintendo Co., Ltd.,
`Nintendo of America, Inc. and Netgear Inc.
`
`
`/s/ Monica Bhattacharyya
`Monica Bhattacharyya
`OFFICE OF UNFAIR IMPORT INVESTIGATIONS
`U.S. International Trade Commission
`500 E Street SW, Suite 401
`Washington, DC 20436
`Telephone: 202.205.1848
`Facsimile: 202.205.2158
`
`
`2
`
`IPR2014-00898
`Exhibit MX027II-1006, p. 2
`
`

`

`
`
`
`PROPOSED CONSTRUCTIONS OF DISPUTED CLAIM TERMS
`
`Term (Claim)
`Preambles:
`"A method of forming a contact
`in a flash memory device that
`improves the depth of focus
`(DOF) margin and the overlay
`margin between a plurality
`stacked gate layers and the
`respective contact"
`('124 claim 1) ('922 claim 1)
`
`U.S. Patent Nos. 6,900,124 & 7,018,922
`Complainant's Construction
`Respondents' Construction
`Preamble is not limiting; no
`Preamble is a limitation.
`construction necessary.
`
`If a construction is required, the
`Respondents' proposed
`terms are addressed below and
`construction is as follows, with
`in the table of agreed-upon
`additional terms addressed
`constructions.
`below and in the table of
`agreed-upon constructions:
`"a method of forming a contact
`for a flash memory device
`where the shape of the contact
`results in improved depth of
`focus of the contact and
`improved overlay margin
`between the contact and the
`stacked gate layers thus
`allowing a reduction in distance
`between stacked gate layers"
`
`Staff's Construction
`Preamble is not limiting; no
`construction is necessary.
`If a construction is required, the
`terms are addressed below and
`in the table of agreed-upon
`constructions.
`
`"flash memory device"
`('124 claims 1, 6) ('922 claim 1)
`
`Preamble is not limiting; no
`construction necessary.
`If construction is required: "a
`type of erasable electronic
`memory media that can be
`rewritten and can hold its
`content without power."
`
`erasable and rewritable
`electronic memory media that
`can hold its content without
`power
`
`Preamble is not limiting; no
`construction necessary.
`If construction is required: "a
`type of erasable electronic
`memory media that can be
`rewritten and can hold its
`content without power."
`
`1
`
`IPR2014-00898
`Exhibit MX027II-1006, p. 3
`
`

`

`
`
`Term (Claim)
`"stacked gate layer(s)"
`('124 claims 1-3, 5-8)
`('922 claims 1-3, 5)
`
`"major axis"
`('124 claims 1, 2, 5, 7, 10)
`('922 claims 1, 2, 5)
`
`"minor axis"
`('124 claims 1, 3, 5, 8, 10)
`('922 claims 1, 3, 5)
`
`"DOF limit"
`('124 claim 1) ('922 claims 1)
`
`U.S. Patent Nos. 6,900,124 & 7,018,922
`Complainant's Construction
`Respondents' Construction
`structure(s) made up of
`a structure of a flash memory
`multiple stacked layers that
`device that includes a floating
`include a gate
`gate and a control gate in a
`stacked configuration
`
`the longest axis of an elongated
`shape
`
`the shortest axis of an
`elongated shape
`
`longest diameter of the contact
`hole and is substantially
`parallel to the stacked gate
`layers
`
`the shortest diameter of the
`contact hole and is substantially
`perpendicular to the stacked
`gate layers
`
`Staff's Construction
`a structure of a flash memory
`device that includes a floating
`gate and a control gate in a
`stacked configuration
`
`the longest axis of an elongated
`shape
`
`the shortest axis of an
`elongated shape
`
`a threshold past which the three
`dimensional region of the
`portion of the photoresist to be
`exposed is no longer within
`specifications
`
`the smallest DOF that can be
`tolerated in manufacturing to
`achieve an adequate result
`
`the smallest DOF that can be
`tolerated in manufacturing to
`achieve an adequate result
`
`2
`
`IPR2014-00898
`Exhibit MX027II-1006, p. 4
`
`

`

`
`
`Term (Claim)
`"the contact hole is
`dimensioned along the major
`axis so as to maintain focus of
`an image of the contact hole as
`the minor axis is reduced in
`size towards a DOF limit."
`('124 claim 1, '922 claim 1)
`
`
`
`
`
`U.S. Patent Nos. 6,900,124 & 7,018,922
`Complainant's Construction
`Respondents' Construction
`the contact hole is shaped so
`the contact hole is shaped so
`that the major axis of the
`that the major axis of the
`contact hole is sized to
`contact hole is sized to
`maintain focus of an image of
`maintain focus of an image of
`the contact hole while the
`the contact hole while the
`minor axis is sized such that the
`minor axis is shorter than the
`patterning capability
`diameter of a circular contact
`approaches or is close to a DOF
`hole whose feature size is at the
`limit
`DOF limit
`
`Staff's Construction
`the contact hole is shaped so
`that the major axis of the
`contact hole is sized to
`maintain focus of an image of
`the contact hole while the
`minor axis is shorter than the
`diameter of a circular contact
`hole whose feature size is at the
`DOF limit
`
`
`
`
`
`3
`
`IPR2014-00898
`Exhibit MX027II-1006, p. 5
`
`

`

`U.S. Patent No. 6,369,416
`Complainant's Construction
`Respondents' Construction
`stacked structures that each
`semiconductor structures each
`include a gate
`having a floating gate and a
`control gate in a stacked
`configuration
`
`Staff's Construction
`semiconductor structures each
`having a floating gate and a
`control gate in a stacked
`configuration
`
`"a side defining a sloped
`profile":
`
`"a side defining a sloped
`profile":
`
`"a side defining a sloped
`profile":
`
` a
`
` side of the contact, between
`the base of the contact and the
`top of the contact, having a
`sloped profile
`
`"an angle between the side of
`the at least on[e] contact and a
`surface of a substrate":
`
`an angle formed by two lines
`corresponding to the sloped
`profile of the side of the contact
`and to a surface of a substrate
`
` a
`
` side of the contact, between
`the base of the contact and the
`top of the contact, having a
`profile such that no point on the
`profile has a vertical slope
`relative to the surface of the
`substrate
`
`"an angle between the side of
`the at least on[e] contact and a
`surface of a substrate":
`
`an angle formed by two lines
`corresponding to (1) a line
`taken along the side of the
`contact from the top of the
`contact to the bottom of the
`contact, and (2) a line taken
`along the surface of a substrate
`
` a
`
` side of the contact that is
`sloped near the substrate
`
`"an angle between the side of
`the at least on[e] contact and a
`surface of a substrate":
`
`an angle formed by two lines
`corresponding to the sloped
`profile of the side of the contact
`and to a surface of a substrate
`
`4
`
`
`
`Term (Claim)
`"gate stacks" (claim 1)
`
`"the at least one contact having
`a side defining a sloped profile
`including an angle between the
`side of the at least on[e]
`contact and a surface of a
`substrate" (claim 1)
`
`IPR2014-00898
`Exhibit MX027II-1006, p. 6
`
`

`

`Staff's Construction
`"a second side defining a
`sloped profile":
`
` a
`
` second side of the contact,
`between the base of the contact
`and the top of the contact,
`having a sloped profile
`
`"a second angle between the
`second side of the contact and a
`surface of a substrate":
`
` a
`
` second angle formed by two
`lines corresponding to the
`sloped profile of the second
`side of the contact and to the
`surface of a substrate
`
`U.S. Patent No. 6,369,416
`Complainant's Construction
`Respondents' Construction
`"a second side defining a
`"a second side defining a
`sloped profile":
`sloped profile":
`
` a
`
` second side of the contact,
`between the base of the contact
`and the top of the contact,
`having a profile such that no
`point on the profile has a
`vertical slope relative to the
`surface of the substrate
`
`"a second angle between the
`second side of the contact and
`the surface of a substrate":
`
`an angle formed by two lines
`corresponding to (1) a line
`taken along a second side of the
`contact from the top of the
`contact to the bottom of the
`contact, and (2) a line taken
`along the surface of a substrate
`
` a
`
` second side of the contact that
`is sloped near the substrate
`
`"a second angle between the
`second side of the contact and
`the surface of a substrate":
`
` a
`
` second angle formed by two
`lines corresponding to the
`sloped profile of the second
`side of the contact and to the
`surface of a substrate
`
`
`
`Term (Claim)
`"the at least one contact hole
`having a second side defining a
`sloped profile including a
`second angle between the
`second side of the contact and
`the surface of a substrate"
`(claim 2)
`
`
`
`
`
`
`5
`
`IPR2014-00898
`Exhibit MX027II-1006, p. 7
`
`

`

`Staff's Construction
`"a memory array"
`
`an area of a memory device
`including operational
`components used in the process
`of storing data
`
`"a periphery"
`
`an area of a memory device
`outside of the memory array in
`which periphery components
`are formed
`
`U.S. Patent 7,151,027
`Complainant's Construction Respondents' Construction
`"a memory array":
`"a memory array":
`
`an area of a memory device
`including operational
`components used in the
`process of storing data
`
`"a periphery":
`
`an area of a memory device
`outside of the memory array
`in which periphery
`components are formed
`
` repeating pattern of
`transistors forming operational
`components used in the process
`of storing data
`
`"a periphery":
`
`an area of a memory device
`outside the memory array that
`includes logic circuits
`
` a
`
`
`
`Term (Claim)
`"at an interface between a
`memory array and a periphery of
`said memory device" (claims 1,
`8)
`
`"proximate to said memory
`array" (claims 1-3, 5, 7-9, 11,
`14)
`
`"proximate to said periphery"
`(claims 1, 2, 4, 5, 7, 8, 10, 11,
`14)
`
`at the side of the interface
`closer to the memory array
`
`proximate (i.e., close) to said
`memory array
`
`proximate (i.e., close) to said
`memory array
`
`at the side of the interface
`closer to the periphery
`
`proximate (i.e., close) to said
`periphery
`
`proximate (i.e., close) to said
`periphery
`
`6
`
`IPR2014-00898
`Exhibit MX027II-1006, p. 8
`
`

`

`
`
`Term (Claim)
`"stacked gate etch" (claims 3, 9)
`
`U.S. Patent 7,151,027
`Complainant's Construction Respondents' Construction
`a type of process that etches
`an etching step that etches at
`poly-1 and poly-2 layers, used
`least a portion of a stacked gate
`to form individual transistor
`structures from the polysilicon
`layers
`
`Staff's Construction
`a type of process that etches
`poly-1 and poly-2 layers, used
`to form individual transistor
`structures from the polysilicon
`layers
`
`"second gate etch" (claims 4, 10)
`
`a process that etches poly-2
`layer
`
`an etching step that etches at
`least a portion of a second gate
`
`a process that etches poly-2
`layer
`
`
`
`
`
`7
`
`IPR2014-00898
`Exhibit MX027II-1006, p. 9
`
`

`

`U.S. Patent 6,459,625
`Complainant's Construction
`Respondents' Construction
`Preambles are limiting such
`Preambles are not limiting.
`that the claims are directed to
`methods or system relating to
`the periphery area in a flash
`memory.
`
`For claim 1, the limiting
`language is "a periphery area in
`a flash memory."
`
`For claim 6, the limiting
`language is "a flash memory."
`
`For claim 10, the limiting
`language is "a periphery area of
`a memory device."
`a type of erasable electronic
`memory that can be rewritten
`and can hold its content without
`power
`
`Preambles are not limiting; no
`construction necessary. If
`construction is required, the
`term should be construed
`consistent with other asserted
`patents.
`an area outside the core
`memory area that includes logic
`circuits
`
`
`
`Term (Claim)
`Preambles (claims 1, 6, 10)
`
`"flash memory" (claims 1, 6)
`
`"periphery area" (claims 1, 6,
`10)
`
`a section of a flash memory
`device outside the core cell area
`
`8
`
`Staff's Construction
`Preambles are not limiting.
`
`Preamble is not limiting; no
`construction necessary. If
`construction is required, the
`term should be construed
`consistent with other asserted
`patents.
`a section of a flash memory
`device outside the core cell area
`
`IPR2014-00898
`Exhibit MX027II-1006, p. 10
`
`

`

`
`
`Term (Claim)
`"sub-circuit" (claims 1, 6, 10)
`
`"completing the electrical
`interconnection of said circuit
`components in each respective
`sub-circuit with a second metal
`interconnect layer" (claim 1)
`"complete the electrical
`interconnection of said
`respective transistors within
`said sub-circuits" (claim 6)
`"complete the electrical
`connection of said circuit
`components of said electric
`circuits" (claim 10)
`
`"the minimum source/drain
`spacing rule" (claims 5, 9, 14)
`
`the rule that governs the
`minimum distance between
`adjacent source/drain areas
`
`
`
`
`
`9
`
`U.S. Patent 6,459,625
`Complainant's Construction
`Respondents' Construction
`a collection of one or more
`circuit in the periphery area that
`integrated electric circuits in
`includes all of the components
`the periphery area of a flash
`necessary to perform a
`memory that generally
`particular logic function that
`performs one or more logic
`assists in memory operations
`related functions
`completing electrical
`connections between or among
`the circuit components within
`the sub-circuits using a second
`metal interconnect layer
`complete electrical connections
`between or among the
`transistors within the sub-
`circuits
`complete electrical connections
`between or among the circuit
`components of the electric
`circuits
`
`completing the electrical
`connections between or among
`all of the circuit components in
`each sub-circuit using a second
`metal interconnect layer
`complete the electrical
`connections between or among
`all the transistors within the
`sub-circuits
`complete the electrical
`connections between or among
`all of the circuit components of
`the electric circuits within each
`sub-circuit
`the minimum distance between
`the source and the drain in a
`transistor to minimize the
`probability of device
`malfunction
`
`Staff's Construction
`circuit in the periphery area that
`performs a logic-related
`function that assists in memory
`operations
`
`completing the electrical
`connections between or among
`all of the circuit components in
`each sub-circuit using a second
`metal interconnect layer
`complete the electrical
`connections between or among
`all the transistors within the
`sub-circuits
`complete the electrical
`connections between or among
`all of the circuit components of
`the electric circuits within each
`sub-circuit
`the minimum distance between
`the source and the drain in a
`transistor to minimize the
`probability of device
`malfunction
`
`IPR2014-00898
`Exhibit MX027II-1006, p. 11
`
`

`

`
`
`Term (Claim)
`Preambles (claims 1, 20)
`
`Staff's Construction
`Preambles are limiting with
`respect to the term "Flash
`memory."
`
`U.S. Patent No. 6,731,536
`Complainant's Construction
`Respondents' Construction
`The preambles of claims 1 and
`Preambles are not limiting.
`20 limit the claims.
`Claim 1: "protecting Flash
`memory against alterations"
`means "providing the capability
`to prevent alterations of data in
`a Flash memory."
`Claim 20: "having multiple
`degrees of protection" means
`"having a variety of levels for
`preventing alterations of data in
`the memory."
`
`"providing different degrees of
`protection" (claim 1)
`
`"persistently locking a sector
`for preventing modification of
`the sector" (claim 1)
`
`making available a variety of
`levels of preventing alterations
`to data in the memory
`
`the degree of protection that
`has the capability of locking a
`sector to prevent alteration of
`data in that sector in a way that
`retains its locked state across
`power cycles until unlocked
`
`"persistent[ly]" (claim 1, 20)
`
`retains its state across power
`cycles
`
`locking a memory by carrying
`out different types of protection
`
`setting a bit that prevents
`changes to the contents of the
`memory such that the only way
`to change the contents is to
`clear the bit, the bit being more
`difficult to clear than a bit that
`is dynamically locked
`
`not easily switchable back and
`forth between protected and
`unprotected conditions
`
`making available a variety of
`levels of preventing alterations
`to data in the memory
`
`the degree of protection that
`has the capability of locking a
`sector to prevent alteration of
`data in that sector in a way that
`retains its locked state across
`power cycles until unlocked
`
`retains its state across power
`cycles
`
`10
`
`IPR2014-00898
`Exhibit MX027II-1006, p. 12
`
`

`

`
`
`Term (Claim)
`"dynamically locking a sector
`which prevents modification of
`the sector without first resetting
`a protection bit" (claim 1)
`
`U.S. Patent No. 6,731,536
`Complainant's Construction
`Respondents' Construction
`the degree of protection that
`setting a bit that prevents
`has the capability of locking a
`changes to the contents of the
`sector to prevent alteration of
`memory such that the only way
`data in the sector until a
`to change the contents is to
`protection bit is reset through a
`clear the bit, the bit being less
`write command, a hardware
`difficult to clear than a bit that
`reset, or a power cycle
`is persistently locked
`
`Staff's Construction
`the degree of protection that
`has the capability of locking a
`sector to prevent alteration of
`data in the sector until a
`protection bit is reset through a
`write command, a hardware
`reset, or a power cycle
`
`"dynamic[ally]" (claims 1, 20)
`
`changeable through a write
`command, a hardware reset, or
`a power cycle
`
`easily switchable back and
`forth between protected and
`unprotected conditions
`
`changeable through a write
`command, a hardware reset, or
`a power cycle
`
`"at least one Persistent
`Protection Bit (PPB) which has
`to be cleared in order to change
`the contents of the memory"
`(claim 20)
`
`at least one non-volatile bit that
`corresponds to at least a sector
`in the memory, retains its state
`across power cycles, and has to
`be cleared to modify data
`stored in the memory
`
`"A method of claim 20"
`(claim 21)
`
`A memory of claim 20
`
`"A method of claim 21"
`(claims 22 and 23)
`
`A memory of claim 21
`
`a bit that, when set, prevents
`changes to the contents of the
`memory such that the only way
`to change the contents is to
`clear the bit, the PPB being
`more difficult to clear than the
`DPB
`
`No construction necessary.
`Alternatively, "method" means
`"process."
`
`No construction necessary.
`Alternatively, "method" means
`"process."
`
`at least one non-volatile bit that
`corresponds to at least a sector
`in the memory, retains its state
`across power cycles, and, when
`set, has to be cleared to modify
`data stored in the memory
`
`A memory of claim 20
`
`A memory of claim 21
`
`
`
`11
`
`IPR2014-00898
`Exhibit MX027II-1006, p. 13
`
`

`

`
`
`
`
`
`AGREED-UPON CONSTRUCTIONS
`
`U.S. Patent Nos. 6,900,124 & 7,018,922
`Term (Claim)
`Agreed-Upon Construction
`"depth of focus (DOF)"
`the range of lens-wafer distances over
`('124 claim 1) ('922 claim 1)
`which exposed photoresist will generate
`line widths within specifications and
`
`adequate resist profiles
`
`"depth of focus margin"
`('124 claim 1) ('922 claim 1)
`
`"overlay margin"
`('124 claim 1) ('922 claim 1)
`
`"an elliptical shape"
`('124 claims 1, 6)
`
`If the preamble is limiting and
`construction is required, the parties have
`agreed upon the following construction:
`"the amount of depth of focus."
`
`If the preamble is limiting and
`construction is required, the parties have
`agreed upon the following construction:
`"the tolerance to errors in the lateral
`positioning between features that were
`patterned on different lithographic
`layers."
`
`a shape close to an ellipse having a major
`axis and a minor axis where the major
`axis is greater than the minor axis
`
`12
`
`IPR2014-00898
`Exhibit MX027II-1006, p. 14
`
`

`

`
`
`
`
`Term (Claim)
`"poly-2 layer" (claims 1 and 8)
`
`U.S. Patent No. 7,151,027
`Agreed-Upon Construction
`a polysilicon layer deposited later in time
`than a first polysilicon layer
`
`"such that step size is smoothed out
`reducing an occurrence of stringers from
`spacer etching" (claims 7, 14)
`
`This is an intended result of the process,
`but not a limitation on the claim.
`
`Term (Claim)
`"password mode"
`(claims 9, 12, 14, 15)
`
`U.S. Patent No. 6,731,536
`Agreed-Upon Construction
`a mode of operation that requires the use
`of a password
`
`13
`
`IPR2014-00898
`Exhibit MX027II-1006, p. 15
`
`

`

`CERTIFICATE OF SERVICE
`
`
`I hereby certify that a copy of the foregoing SECOND JOINT SUBMISSION
`
`REGARDING PROPOSED CONSTRUCTION OF DISPUTED CLAIM TERMS was
`served to the parties, in the manner indicated below, this 12th day of February 2014:
`
`
` VIA HAND DELIVERY – 2 Copies
`
`
` VIA HAND DELIVERY
` VIA ELECTRONIC MAIL
`
`(monica.bhattacharyya@usitc.gov)
`
`
`The Honorable E. James Gildea
`Administrative Law Judge
`U.S. INTERNATIONAL TRADE COMMISSION
`500 E Street, S.W., Room 317-E
`Washington, DC 20436
`
`Monica Bhattacharyya, Esq.
`Office of Unfair Import Investigations
`U.S. INTERNATIONAL TRADE COMMISSION
`500 E Street, SW, Room 401-G
`Washington, DC 20436
`
`COUNSEL FOR RESPONDENTS MACRONIX INTERNATIONAL CO., LTD.,
`MACRONIX AMERICA, INC., MACRONIX ASIA LIMITED, MACRONIX
`(HONG KONG) CO., LTD., ACER INC., ACER AMERICA CORPORATION,
`ASUSTEK COMPUTER INC., ASUS COMPUTER INTERNATIONAL,
`BELKIN INTERNATIONAL, INC., D-LINK CORPORATION, D-LINK SYSTEMS, INC.,
`NINTENDO CO., LTD., NINTENDO OF AMERICA, INC. AND NETGEAR INC.
`
` VIA FIRST CLASS MAIL
`Thomas L. Jarvis, Esq.
` VIA OVERNIGHT DELIVERY
`WINSTON & STRAWN LLP
` VIA ELECTRONIC MAIL
`1700 K Street, N W
`
`(ITC893Winstoncourtesy@winston.com)
`Washington, DC 20006-3817
`
`
`
`
`
`/s/ Kelsey R. Curtis, Paralegal
`ADDUCI, MASTRIANI & SCHAUMBERG, L.L.P.
`
`
`
`
`SPAN100013 E-filing.docx
`
`IPR2014-00898
`Exhibit MX027II-1006, p. 16
`
`