Trials@uspto.gov
`571-272-7822
`
`
`Paper 16
`Entered: May 8, 2014
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`MACRONIX INTERNATIONAL CO., LTD.,
`MACRONIX ASIA LIMITED, MACRONIX (HONG KONG) CO., LTD.,
`and MACRONIX AMERICA, INC.
`Petitioner
`
`v.
`
`SPANSION LLC
`Patent Owner
`____________
`
`Case IPR2014-00108
`Patent 7,151,027 B1
`
`
`
`Before DEBRA K. STEPHENS, JUSTIN T. ARBES, and
`RICHARD E. RICE, Administrative Patent Judges.
`
`RICE, Administrative Patent Judge.
`
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`IPR2014-00898
`Exhibit MX027II-1005, p. 1
`
`

`

`Case IPR2014-00108
`Patent 7,151,027 B1
`
`
` Macronix International Co., Ltd., Macronix Asia Limited, Macronix
`
`(Hong Kong) Co., Ltd., and Macronix America, Inc. (collectively
`
`“Petitioner”) filed a Petition (Paper 1, “Pet.”) to institute an inter partes
`
`review of claims 1-14 of U.S. Patent No. 7,151,027 B1 (Ex. 1001, “the ’027
`
`patent”) pursuant to 35 U.S.C. §§ 311-319. Pet. 3. Patent Owner
`
`Spansion LLC (“Patent Owner”) filed a Preliminary Response (Paper 14,
`
`“Prelim. Resp.”) to the Petition. We have jurisdiction under 35 U.S.C.
`
`§ 314. For the reasons that follow, the Board has determined to institute an
`
`inter partes review.
`
`
`
`I. BACKGROUND
`
`The standard for instituting an inter partes review is set forth in
`
`35 U.S.C. § 314(a):
`
`THRESHOLD—The Director may not authorize an inter partes
`review to be instituted unless the Director determines that the
`information presented in the petition filed under section 311
`and any response filed under section 313 shows that there is a
`reasonable likelihood that the petitioner would prevail with
`respect to at least 1 of the claims challenged in the petition.
`
`Petitioner challenges claims 1-14 as unpatentable under 35 U.S.C.
`
`§§ 102(b) and 103(a). Pet. 3-4. We grant the Petition as to claims 1-6 and
`
`8-13 on certain grounds, but not as to claims 7 and 14, as discussed below.
`
`
`
`A. Related Proceedings
`
`Petitioner discloses that the ’027 patent is asserted in: (1) Spansion
`
`LLC v. Macronix International Co., Ltd., Civ. No. 3:13-cv-03566 (N.D.
`
`Cal.); and (2) In re Flash Memory Chips and Products Containing Same,
`
`Inv. No. 337-TA-893 (U.S. Int’l Trade Comm’n). Pet. 1.
`
`
`
`2
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`IPR2014-00898
`Exhibit MX027II-1005, p. 2
`
`

`

`Case IPR2014-00108
`Patent 7,151,027 B1
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`B. The ’027 Patent (Ex. 1001)
`
`The ’027 patent, titled “Method and Device for Reducing Interface
`
`Area of a Memory Device,” issued on December 19, 2006. According to the
`
`’027 patent, the operational and peripheral components of a memory device
`
`conventionally are fabricated using separate processes, resulting in “steps”
`
`between structures in the interface area. Ex. 1001, 1:24-40; fig. 1. Further,
`
`“stringer spacers,” i.e., small components that easily are peeled or removed
`
`from the memory device, are formed in the interface area at the steps. Id. at
`
`1:45-48; fig. 1. Conventionally, the risk of damage to the memory device
`
`from stringer spacer debris is eliminated by fabricating a salicide block
`
`(layer) over the interface area. Id. at 1:54-57; fig. 1.
`
`The ’027 patent, by smoothing out any steps caused by etching in the
`
`interface area, addresses the problem of stringer spacers and eliminates the
`
`need for a salicide layer. Id. at 2:57-3:2. In one embodiment, a polysilicon
`
`interface structure, the height of which is easy to control, is used to smooth
`
`out any such steps. Id. at 2:59-65.
`
`Figures 3A-3G of the ’027 patent illustrate steps in a process for
`
`forming interface structure 360. Id. at 3:18-22.
`
`At the step illustrated in Figure 3D of the ’027 patent, which is
`
`reproduced below, “second polysilicon layer (poly-2) 320” is deposited
`
`above dialectric material 315 and substrate 300. Id. at 4:22-24.
`
`
`
`
`
`3
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`IPR2014-00898
`Exhibit MX027II-1005, p. 3
`
`

`

`Case IPR2014-00108
`Patent 7,151,027 B1
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`
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`
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`A vertical dashed line on the left of Figure 3D denotes the
`
`approximate border between a memory array (“core”) and the interface area,
`
`and a vertical dashed line on the right of the figure denotes the approximate
`
`border between the interface area and the periphery. Id. at 3:54-57. As
`
`depicted in Figure 3D, first polysilicon layer 310a, referred to as “gate
`
`polysilicon (‘poly-1’) 310a” in the ’027 patent, is disposed beneath dielectric
`
`material 315. Id. at 3:50-53. Figure 3D also depicts isolation area 305. Id.
`
`at 3:51-52.
`
`
`
` Figure 3E of the ’027 patent, which is reproduced below, depicts the
`
`step of etching a portion of poly-1 layer 310a, dielectric material layer 315,
`
`and poly-2 layer 320, proximate to the memory array. Id. at 4:27-30.
`
`The ’027 patent discloses that “a known process (such as a stacked gate
`
`etch)” is used for the etching step in Figure 3E. Id.
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`
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`
`
`4
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`IPR2014-00898
`Exhibit MX027II-1005, p. 4
`
`

`

`Case IPR2014-00108
`Patent 7,151,027 B1
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`
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`Figure 3F of the ’027 patent, which is reproduced below, depicts the
`
`step of etching a portion of poly-2 layer 320 proximate to the periphery. Id.
`
`at 4:38-40. As described in the ’027 patent, “a known process (such as a
`
`second gate etch)” is used for the etching step depicted in Figure 3F. Id.
`
`The etching step is used to form interface structure 360, which is illustrated
`
`in Figure 3F. Id. at 4:41.
`
`
`
`
`
`As depicted in Figure 3F and described in the ’027 patent, “interface
`
`structure 360 is the same height as the memory array proximate to the
`
`memory array and the same height as the periphery proximate to the
`
`periphery, such that step size is smoothed out reducing the occurrence of
`
`stringers from spacer etching.” Id. at 4:49-54.
`
`
`
`C. Illustrative Claims
`
`Claims 1 and 8 are independent. Claims 2-7 depend directly or
`
`indirectly from claim 1, and claims 9-14 depend, directly or indirectly, from
`
`claim 8. Claims 8 and 14, which are reproduced below, are illustrative:
`
`A method for fabricating a memory
`8.
`device, said method comprising:
`forming a poly-1 layer above a substrate at
`an interface between a memory array and a
`periphery of said memory device;
`forming a poly-2 layer above said poly-1
`layer at said interface;
`
`
`
`5
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`IPR2014-00898
`Exhibit MX027II-1005, p. 5
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`

`

`Case IPR2014-00108
`Patent 7,151,027 B1
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`
`etching said poly-1 layer and said poly-2
`layer proximate to said memory array; and
`etching said poly-2 layer proximate to said
`periphery,
`such
`that an
`interface
`structure
`including a portion of said poly-1 layer and a
`portion of said poly-2 layer remains at said
`interface.
`
`14. The method as recited in claim 8
`wherein said interface structure is a same height as
`said memory array proximate to said memory
`array and a same height as said periphery
`proximate to said periphery, such that step size is
`smoothed out reducing an occurrence of stringers
`from spacer etching.
`
`Id. at 6:2-11, 7:5-8:4.
`
`
`D. The Prior Art
`
`Petitioner relies upon the following prior art references (Pet. 3-4):
`
`
`Yuzuriha US 6,458,655 B1 Oct. 1, 2002
`
`Shukuri
`
`US 6,559,012 B2 May 6, 2003
`
`Ex. 1003
`
`Ex. 1005
`
`Nakagawa US 6,359,304 B2 Mar. 19, 2002
`
`Ex. 1006
`
`
`
`Petitioner contends that Yuzuriha, Shukuri, and Nakagawa are prior
`
`art to the claims of the ’027 patent under 35 U.S.C. § 102(b). Id. at 9, 19-20,
`
`22.
`
`
`E. The Asserted Grounds
`
`Petitioner challenges claims 1-14 of the ’027 patent on the following
`
`grounds (id. at 3-4):
`
`
`
`
`
`6
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`IPR2014-00898
`Exhibit MX027II-1005, p. 6
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`

`

`Case IPR2014-00108
`Patent 7,151,027 B1
`
`
` Reference(s)
`
`Yuzuriha
`
`Yuzuriha and Shukuri
`
`Yuzuriha and Nakagawa
`
`Shukuri
`
`Shukuri and Nakagawa
`
`Nakagawa
`
`Nakagawa and Shukuri
`
`
`
` Basis
`
`§ 102(b)
`
`§ 103(a)
`
`§ 103(a)
`
`§ 102(b)
`
`§ 103(a)
`
`§ 103(a)
`
`§ 103(a)
`
`Claims Challenged
`
`1-4 and 8-10
`
`5, 11, and 12
`
`6, 7, 13, and 14
`
`1-6 and 8-13
`
`7 and 14
`
`1-4, 6-10, 13, and 14
`
`5, 11, and 12
`
`F. Claim Interpretation
`
`Consistent with the statute and legislative history of the Leahy-Smith
`
`America Invents Act, Pub. L. No. 112-29, 125 Stat. 284 (2011) (“AIA”), the
`
`Board interprets claims using the “broadest reasonable construction in light
`
`of the specification of the patent in which [they] appear[].” 37 C.F.R.
`
`§ 42.100(b); see Office Patent Trial Practice Guide, 77 Fed. Reg. 48,756,
`
`48,766 (Aug. 14, 2012). There is a “heavy presumption” that a claim term
`
`carries its ordinary and customary meaning. CCS Fitness, Inc. v. Brunswick
`
`Corp., 288 F.3d 1359, 1366 (Fed. Cir. 2002). However, a “claim term will
`
`not receive its ordinary meaning if the patentee acted as his own
`
`lexicographer and clearly set forth a definition of the disputed claim term in
`
`either the specification or prosecution history.” Id. “Although an inventor is
`
`indeed free to define the specific terms used to describe his or her invention,
`
`this must be done with reasonable clarity, deliberateness, and precision.” In
`
`re Paulsen, 30 F.3d 1475, 1480 (Fed. Cir. 1994). Also, we must be careful
`
`not to read a particular embodiment appearing in the written description into
`
`the claim if the claim language is broader than the embodiment. See In re
`
`
`
`7
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`IPR2014-00898
`Exhibit MX027II-1005, p. 7
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`Case IPR2014-00108
`Patent 7,151,027 B1
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`Van Geuns, 988 F.2d 1181, 1184 (Fed. Cir. 1993) (“[L]imitations are not to
`
`be read into the claims from the specification.”).
`
`For purposes of this decision, we construe certain claim limitations as
`
`follows.
`
`
`
`1. “poly-2 layer” (claims 1 and 8); and
`“poly-1 layer” (claims 2, 6, and 8)
`
`Patent Owner contends the term “poly-2 layer” should be construed,
`
`consistent with the specification, to mean “a polysilicon layer deposited later
`
`in time than a first polysilicon layer.” Prelim. Resp. 9-10 (citing Ex. 1001,
`
`5:11-12 (“At step 410, a first polysilicon layer (e.g., poly-1) is formed
`
`. . . .”); id. at 5:17-18 (“At step 430, a second polysilicon layer (e.g., poly-2)
`
`is formed . . . .”)). Patent Owner represents that in the co-pending ITC
`
`proceeding involving the same patent and parties, both parties have agreed
`
`to that construction. Id. (citing Ex. 2001, 13). Indeed, Petitioner and
`
`Petitioner’s declarant, Mr. Brahmbhatt, have applied that construction in this
`
`proceeding. E.g., Pet. 11 (referring to “[a] second polysilicon layer” as
`
`“poly-2”); Ex. 1002 (Corrected Decl. of Dhaval J. Brahmbhatt) ¶ 53
`
`(“Because this is the second layer of polysilicon deposited, a person of skill
`
`in the art would refer to this as the poly-2 layer.”). Patent Owner’s proposed
`
`construction is consistent with the specification, which describes depositing
`
`the poly-2 layer later in time than the poly-1 layer. See, e.g., Ex. 1001, 5:11-
`
`18.
`
`Applying the broadest reasonable interpretation of the claims in light
`
`of the specification, we interpret “poly-2 layer” (claims 1 and 8) to mean “a
`
`polysilicon layer deposited later in time than a first polysilicon layer.”
`
`
`
`8
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`IPR2014-00898
`Exhibit MX027II-1005, p. 8
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`

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`Case IPR2014-00108
`Patent 7,151,027 B1
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`Neither party proposed a construction of “poly-1 layer.” Similar to
`
`“poly-2 layer,” we interpret “poly-1 layer” (claims 2, 6, and 8) to mean “a
`
`first polysilicon layer.”
`
`
`
`2. “etching said poly-1 layer and said poly-2 layer
`proximate to said memory array” (claim 8)
`
`Patent Owner contends “[t]he plain language” of claim 8 “requires
`
`that both the ‘poly-1 layer and [] poly-2 layer’ are etched in one step.”
`
`Prelim. Resp. 15. Claim 8 recites “etching said poly-1 layer and said poly-2
`
`layer proximate to said memory array,” but does not recite specifically how
`
`the etching of the two structures is accomplished. The specification
`
`pertinently states “a known process (such as a stacked gate etch) is used to
`
`etch a portion of poly-1 310a, dialectric material 315 and poly-2 320
`
`proximate to the memory array.” Ex. 1001, 4:28-30 (emphasis added). As
`
`such, the specification describes using a “process” to etch the two recited
`
`structures. Patent Owner does not explain sufficiently why “etching” in
`
`claim 8 requires the recited structures to be etched in “one step” rather than
`
`by a process that involves multiple steps, for example, sequentially etching
`
`one structure and then the other, in separate steps. Based on the current
`
`record, therefore, we do not agree with Patent Owner that “etching said
`
`poly-1 layer and said poly-2 layer proximate to said memory” requires a
`
`single etching “step.”
`
`
`
`3. “stacked gate etch” (claims 3 and 9); and
`“second gate etch” (claims 4 and 10)
`
`Petitioner contends “the broadest reasonable interpretation of the term
`
`‘stacked gate etch’ . . . in light of the specification includes an ‘etching step
`
`
`
`9
`
`IPR2014-00898
`Exhibit MX027II-1005, p. 9
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`Case IPR2014-00108
`Patent 7,151,027 B1
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`that etches at least a portion of a stacked gate.’” Pet. 5 (emphasis added).
`
`Similarly, Petitioner contends “the term ‘second gate etch’ includes an
`
`‘etching step that etches at least a portion of a second gate.’” Id. (citing
`
`Ex. 1001, 4:38-40) (emphasis added).
`
`In response, Patent Owner contends that “stacked gate etch” should be
`
`construed to mean “a type of process that etches poly-1 and poly-2 layers,
`
`used to form individual transistor structures from the polysilicon layers.”
`
`Prelim. Resp. 10. Patent Owner contends that “second gate etch” should be
`
`construed to mean “a process that etches [the] poly-2 layer.” Id. at 14.
`
`The specification describes “stacked gate etch” as a known process
`
`that is used to etch poly-1 and poly-2 layers and, thereby, to form individual
`
`transistor structures from the layers. Ex. 1001, 4:27-31; see Prelim. Resp.
`
`10. Patent Owner persuasively argues:
`
`The ’027 specification states, for example, that a “stacked gate
`etch” is a process that etches poly-1 and poly-2 layers: “At step
`440, the poly-1 layer and the poly-2 layer are etched proximate
`to the memory array. In one embodiment, the etching is
`accomplished by performing a stacked gate etch.” MX027-
`1001 at 5:22-25. Elsewhere, the ’027 specification states, that
`“a known process (such as a stacked gate etch) is used to etch a
`portion of poly-1 310a, dielectric material 315, and poly-2 320.”
`MX027-1001 at 4:27-30. The specification further describes
`that “[t]his etch is used to form individual transistors of from
`[sic] the polysilicon layers.” Id. at 4:30-31.
`
`Prelim. Resp. 10. Patent Owner further argues:
`
`a person of ordinary skill in the art would understand that the
`invention as described and claimed in the ’027 Patent is one in
`which the stacked gate etch would etch at least poly-2 and
`poly-1 layers thereby enabling the formation of a stacked gate
`(i.e., the etch would be “used to form individual transistor
`structures from the polysilicon layers”).
`
`
`
`10
`
`IPR2014-00898
`Exhibit MX027II-1005, p. 10
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`Case IPR2014-00108
`Patent 7,151,027 B1
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`Id. at 11.
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`Similarly, the specification describes “second gate etch” as “a process
`
`that etches [a] poly-2 layer.” Ex. 1001, 4:38-41; see Prelim. Resp. 13. As
`
`Patent Owner argues, the specification states “a known process (such as a
`
`second gate etch) is used to etch a portion of poly-2 320.” Prelim. Resp. 13
`
`(citing Ex. 1001, 4:39-41).
`
`Patent Owner directs our attention to the co-pending ITC proceeding,
`
`in which the ITC Commission Investigative Staff Attorney proposed that
`
`(1) “stacked gate etch” be construed as “a type of process that etches poly-1
`
`and poly-2 layers, used to form individual transistor structures from the
`
`polysilicon layers”; and (2) “second gate etch” be construed as “a process
`
`that etches [the] poly-2 layer.” Id. at 12, 14 (citing Ex. 2001, 7).
`
`We agree with Patent Owner that Petitioner’s proposed
`
`interpretations, which each encompasses etching any portion of the specified
`
`gate structure, are inconsistent with the specification. See id. at 11-12, 13-
`
`14. Patent Owner has not explained sufficiently, however, why “stacked
`
`gate etch” should be construed as “a type of process,” rather than simply as a
`
`“process.” Nor has Patent Owner explained sufficiently why the broadest
`
`reasonable interpretation of “stacked gate etch” should be limited by the
`
`words “used to form individual transistor structures from the polysilicon
`
`layers,” as it proposes. See id. at 10.
`
`Applying the broadest reasonable interpretation of the claims in light
`
`of the specification, we interpret “stacked gate etch” to mean “a process that
`
`etches poly-1 and poly-2 layers.”
`
`Patent Owner additionally argues that “like Claim 8, Claims 3 and 9
`
`require that both the poly-1 and poly-2 layer be etched in one step.” Id. at
`
`
`
`11
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`IPR2014-00898
`Exhibit MX027II-1005, p. 11
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`Case IPR2014-00108
`Patent 7,151,027 B1
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`15 (footnotes omitted). Similar to our analysis above regarding the recited
`
`“etching” in claim 8, we are not persuaded by Patent Owner’s arguments
`
`that the recited “stacked gate etch” in claims 3 and 9 must be accomplished
`
`in a single step.
`
`Similar to “stacked gate etch,” we interpret “second gate etch” to
`
`mean “a process that etches a poly-2 layer.”
`
`
`
`4. Other Terms
`
`No other terms in the challenged claims need be construed expressly
`
`for purposes of this decision.
`
`
`
`II. DISCUSSION
`
`We turn now to Petitioner’s asserted grounds of unpatentability and
`
`Patent Owner’s arguments in its Preliminary Response to determine whether
`
`Petitioner has met the threshold standard of 35 U.S.C. § 314(a).
`
`
`
`A. Claims 1-4 and 8-10—Asserted Anticipation—Yuzuriha
`
`Petitioner contends Yuzuriha anticipates claims 1-4 and 8-10 under
`
`35 U.S.C. § 102(b). Pet. 13-19. To support its assertions, Petitioner
`
`provides a claim chart (id.) and a declaration of Dhaval J. Brahmbhatt
`
`(Exhibit 1002). We are persuaded that Petitioner has established a
`
`reasonable likelihood of prevailing on its assertion that Yuzuriha anticipates
`
`claims 1-4 and 8-10 for the reasons explained below.
`
`
`
`1. Yuzuriha
`
`
`
`Yuzuriha discloses “a flash memory manufacturing method using a
`
`2-layer-stacked polysilicon film to form a cell.” Ex. 1003, 11:43-45. Figure
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`
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`12
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`IPR2014-00898
`Exhibit MX027II-1005, p. 12
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`5 of Yuzuriha, reproduced below, is a cross section of a flash memory
`
`manufactured according to the disclosed method. Id. at 11:46-52.
`
`Figure 5 illustrates a “dummy gate region”
`sandwiched between a “memory cell region”
`and a “peripheral circuitry region.”
`
`The dummy gate region illustrated in Figure 5 includes dummy
`
`
`
`gate 14, which in turn includes isolating oxide film 8 formed on substrate 1,
`
`first conductive (polysilicon) layer 10 provided on isolating oxide film 8,
`
`poly-poly insulation layer 11 provided on first conductive layer 10, and
`
`second conductive (polysilicon) layer 13 provided on insulation layer 11. Id.
`
`at 11:52-12:6, 12:28-30.
`
`As shown in Figure 5, “the memory cell requires a floating gate and a
`
`poly-poly insulation film while the peripheral circuitry does not require such
`
`films.” Id. at 11:63-65. Each memory cell in the memory cell region
`
`includes tunnel oxide film 9 formed on substrate 1, first polysilicon layer 10
`
`(serving as a floating gate) formed on tunnel oxide film 9, poly-poly
`
`insulation film 11 formed on floating gate 10, second polysilicon layer 13
`
`(serving as a control gate) formed on poly-poly insulation film 11, and oxide
`
`
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`13
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`IPR2014-00898
`Exhibit MX027II-1005, p. 13
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`Case IPR2014-00108
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`film 16 formed on second polysilicon layer 13. Id. at 12:1-6, 28-30, 56-59.
`
`The peripheral circuitry, which has a different structure, includes gate oxide
`
`film 12, second polysilicon layer 13 (serving as a transistor gate), and oxide
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`film 16. Id. at 12:26-30.
`
`
`
`Figures 6-10 of Yuzuriha illustrate cross sections of a semiconductor
`
`device as manufactured using a method of making the Figure 5 flash
`
`memory. Id. at 11:66-12:63. We discuss Figures 9 and 10 below.
`
`
`
`
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`2. Anticipation Analysis
`
`As stated above, we are persuaded on this record that Petitioner has
`
`established a reasonable likelihood of prevailing on its assertion that
`
`Yuzuriha anticipates claims 1-4 and 8-10. See Pet. 13-19. We are not
`
`persuaded by Patent Owner’s arguments that Yuzuriha does not disclose
`
`certain of the etching limitations in claims 3, 8, and 9. See Prelim. Resp. 15-
`
`19.
`
`a. Claim 8
`
`
`
`As to the limitation in claim 8 requiring “etching said poly-1 layer and
`
`said poly-2 layer proximate to said memory array,” Petitioner relies on
`
`Yuzuriha’s disclosed flash-memory-manufacturing method as depicted in
`
`Figures 8, 9, and 10, and Mr. Brahmbhatt’s testimony regarding the same.
`
`Pet. 17-18 (citing Ex. 1003, 12:56-63, figs. 8-10; Ex. 1002 ¶¶ 55, 56). Mr.
`
`Brahmbhatt’s annotated version of Figure 9 of Yuzuriha is reproduced
`
`below.
`
`
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`14
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`IPR2014-00898
`Exhibit MX027II-1005, p. 14
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`Case IPR2014-00108
`Patent 7,151,027 B1
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`Mr. Brahmbhatt’s annotated version of Figure 9 of Yuzuriha
`
`
`
`Ex. 1002, 23. As marked by an arrow and labeled in Mr. Brahmbhatt’s
`
`annotated version of Figure 9, Yuzuriha discloses “etching poly-2 proximate
`
`to [the] memory array.” Id. Mr. Brahmbhatt’s annotated version of Figure
`
`10 of Yuzuriha is reproduced below.
`
`Mr. Brahmbhatt’s annotated version of Figure 10 of Yuzuriha
`
`
`
`Id. at 24. As marked by an arrow and labeled in Mr. Brahmbhatt’s annotated
`
`version of Figure 10, Yuzuriha also discloses “[e]tching poly-1 proximate to
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`the memory array.” Id.
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`In response, Patent Owner contends that “[t]he plain language” of
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`claim 8 “requires that both the ‘poly-1 layer and [] poly-2 layer’ are etched
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`15
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`in one step.” Prelim. Resp. 15. Patent Owner argues that Yuzuriha does not
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`disclose a process that etches the poly-1 and poly-2 layers proximate to the
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`memory array in one step, but rather discloses a process that etches the poly-
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`2 layer proximate to the memory array in a first step and the poly-1 layer
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`proximate to the memory array in a subsequent step. Id. at 17-19. On this
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`basis, Patent Owner contends that Yuzuriha does not anticipate claim 8. Id.
`
`at 19.
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`Based on the current record, however, we do not agree with Patent
`
`Owner’s argument that claim 8 requires etching the poly-1 and poly-2 layers
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`proximate to the memory array in one “step,” as discussed above. See id. at
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`15. Accordingly, based on the current record, we do not agree with Patent
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`Owner’s contention that Yuzuriha does not anticipate claim 8. See id. at 19.
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`In conclusion, Petitioner has demonstrated, on the current record, a
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`reasonable likelihood of prevailing on its assertion that Yuzuriha anticipates
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`claim 8.
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`
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`b. Claims 3 and 9
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`Claim 9 recites the method of claim 8, “wherein said etching said
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`poly-1 layer and said poly-2 layer proximate to said memory array is
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`accomplished by performing a stacked gate etch.” Claim 3 similarly
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`requires “performing a stacked gate etch.” As discussed above, we interpret
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`“stacked gate etch” to mean “a process that etches poly-1 and poly-2 layers.”
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`With respect to the “stacked gate etch” limitation, Petitioner again relies on
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`Yuzuriha’s disclosed flash-memory-manufacturing method as depicted in
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`Figures 8, 9, and 10, and Mr. Brahmbhatt’s testimony regarding the same.
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`16
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`Pet. 15-16, 18-19 (citing Ex. 1003, 11:43-45, 12:56-59, figs. 5 & 8-10;
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`Ex. 1002 ¶ 59); see supra Section II.A.2.a (analysis of claim 8).
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` In response, Patent Owner argues that “like Claim 8, Claims 3 and 9
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`require that both the poly-1 and poly-2 layer be etched in one step.” Prelim.
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`Resp. 15 (footnotes omitted). Patent Owner asserts Yuzuriha does not
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`anticipate claims 3 and 9, because the reference does not disclose etching the
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`poly-1 and poly-2 layers proximate to the memory array in one step. Id. at
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`19.
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`As discussed above, we are not persuaded, on this record, by Patent
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`Owner’s arguments that the recited “stacked gate etch” must be
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`accomplished in a single step. The “stacked gate etch” limitation of claims 3
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`and 9 requires only a process that etches poly-1 and poly-2 layers.
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`Accordingly, on the current record, we do not agree with Patent Owner’s
`
`arguments that Yuzuriha does not anticipate claims 3 and 9.
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`In conclusion, Petitioner has demonstrated, on the current record, a
`
`reasonable likelihood of prevailing on its assertion that Yuzuriha anticipates
`
`claims 3 and 9.
`
`
`
`
`
`c. Claims 1, 2, 4, and 10
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`Claim 1 is similar to claim 8, but does not recite a poly-1 layer.
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`Claim 2 introduces the poly-1 layer. Claims 4 and 10 recite a “second gate
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`etch.” Upon review of Petitioner’s analysis and supporting declaration, we
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`are persuaded that Petitioner’s asserted ground of anticipation of claims 1, 2,
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`4, and 10 has merit. See Pet. 13-16, 19. Patent Owner, in its preliminary
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`response, does not argue specifically the asserted ground of anticipation of
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`claims 1, 2, and 4. See Prelim. Resp. 15-19. As to claim 10, Patent Owner
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`17
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`attempts to distinguish it from Yuzuriha based only on its dependency from
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`claim 8. Id. at 19. As discussed above, however, Petitioner has
`
`demonstrated a reasonable likelihood of prevailing on its assertion that
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`Yuzuriha anticipates claim 8.
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`In conclusion, Petitioner has demonstrated, on the current record, a
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`reasonable likelihood of prevailing on its assertion that Yuzuriha anticipates
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`claims 1-4 and 8-10.
`
`
`B. Claims 5, 11, and 12—Asserted Obviousness—Yuzuriha and Shukuri
`
`Petitioner contends claims 5, 11, and 12 would have been obvious
`
`over Yuzuriha and Shukuri under 35 U.S.C. § 103(a). Pet. 19-22. We are
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`persuaded that Petitioner has established a reasonable likelihood of
`
`prevailing on its assertion that claims 5, 11, and 12 would have been obvious
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`over Yuzuriha and Shukuri for the reasons explained below.
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`
`
`1. Shukuri
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`Shukuri discloses a method for manufacturing a semiconductor
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`integrated circuit device having a built-in flash memory. Ex. 1005, 16:58-
`
`61. Figure 24 of Shukuri, reproduced in pertinent part below, depicts side
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`wall spacers 74, gate electrode 68 (on the left), dummy wiring 67 (in the
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`middle), and nonvolatile memory element QF1 (on the right). Id. at 20:37-
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`43, 21:4-10, 18-19.
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`18
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`This portion of Figure 24 depicts spacers 74
`covering side faces of gate electrode 68, dummy
`wiring 67, and nonvolatile memory element QF1.
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`
`
`As shown in Figure 24, side wall spacers 74 cover side faces of gate
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`electrode 68, dummy wiring 67, and nonvolatile memory element QF1. See
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`id. at 21:4-6. Shukuri discloses fabricating side wall spacers 74 by forming
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`an insulating film of silicon nitride and, subsequently, subjecting the
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`insulating film to anisotropic etching treatment. Id. at 21:4-10.
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`
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`2. Obviousness Analysis
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`Claims 5 and 11 each require both “forming spacers proximate to said
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`memory array” and “forming spacers proximate to said periphery.”
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`Claim 12 recites the method of claim 11 “wherein said spacers are nitride
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`spacers.”
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`Petitioner contends it would have been obvious to modify the process
`
`of fabricating a semiconductor structure as taught by Yuzuriha to form
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`nitride spacers proximate to the memory array and spacers proximate to the
`
`
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`19
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`periphery as taught by Shukuri, because “such spacers were well known in
`
`the art to be used, for example, as masks for implanting ions in the creation
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`of source and drain regions around semiconductor gates.” Pet. 21-22
`
`(citations omitted); see Ex. 1002 ¶¶ 121 (“[T]he benefit of nitride sidewall
`
`spacers in the formation of source and drain regions of memory regions was
`
`also known in the art at the time.”), 122 (“[A] person of skill in the art . . .
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`would have been motivated to combine the teachings of Yuzuriha and
`
`Shukuri in order to add the known benefits of utilizing sidewall spacers,
`
`such as for the self-aligned formation of lightly doped source and drain
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`regions, to the teachings of Yuzuriha.”).
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`Patent Owner argues, unpersuasively, “Petitioner has failed to
`
`describe how one of ordinary skill in the art would modify Yuzuriha to
`
`disclose the claimed invention, or why the claimed invention would be
`
`obvious in any of these references.” Prelim. Resp. 23. Patent Owner’s
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`argument fails to address either (1) Petitioner’s assertion that nitride spacers
`
`were well known in the art and that a person of skill in the art would have
`
`used such spacers for their known benefits in Yuzuriha’s process, or (2)
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`Mr. Brahmbhatt’s testimony on the issue. See KSR Int’l Co. v. Teleflex Inc.,
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`550 U.S. 398, 417 (2007) (“[I]f a technique has been used to improve one
`
`device, and a person of ordinary skill in the art would recognize that it would
`
`improve similar devices in the same way, using the technique is obvious
`
`unless its actual application is beyond his or her skill.”).
`
`Upon review of Petitioner’s analysis and supporting declaration, we
`
`are persuaded based on the current record that Petitioner’s asserted ground
`
`of obviousness of claims 5, 11, and 12 over Yuzuriha and Sukuri has merit.
`
`See Pet. 20-22. In conclusion, Petitioner has demonstrated, on the current
`
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`record, a reasonable likelihood of prevailing on its assertion that claims 5,
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`11, and 12 would have been obvious over Yuzuriha and Shukuri.
`
`
`C. Claims 6 and 13—Asserted Obviousness—Yuzuriha and Nakagawa
`
`Petitioner contends claims 6 and 13 would have been obvious over
`
`Yuzuriha and Nakagawa under 35 U.S.C. § 103(a). Pet. 22-24. We are
`
`persuaded that Petitioner has established a reasonable likelihood of
`
`prevailing on its assertion that claims 6 and 13 would have been obvious
`
`over Yuzuriha and Nakagawa for the reasons explained below.
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`Each of claims 6 and 13 requires “forming an ONO [oxide-nitride-
`
`oxide] layer above said poly-l layer such that said ONO layer is above said
`
`poly-l layer and beneath said poly-2 layer.”
`
`Yuzuriha discloses forming poly-poly insulation layer 11 above first
`
`polysilicon layer 10 (which serves as a floating gate) such that poly-poly
`
`insulation layer 11 is above first polysilicon layer 10 and beneath second
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`polysilicon layer 13 (which serves as a control gate). Ex. 1003, 11:52-12:6,
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`12:28-30, fig. 5. As Petitioner recognizes, however, Yuzuriha is “silent”
`
`regarding the material used to form poly-poly insulation layer 11. See
`
`Pet. 25.
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`We are persuaded by the Petition and Petitioner’s supporting
`
`evidence, including the declaration of Mr. Brahmbhatt, that Nakagawa
`
`discloses using an ONO film as the insulation layer between a floating gate
`
`and a control gate. Id. (citing Ex. 1006, 6:50-55); see Ex. 1002 ¶ 125. We
`
`also are persuaded that it would have been obvious to use an ONO insulation
`
`film, such as disclosed by Nakagawa, as the poly-poly insulation layer
`
`between the poly-1 and poly-2 layers of Yuzuriha. See id. (citing Ex. 1002
`
`
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`21
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`¶ 126). Patent Owner, in its preliminary response, does not argue
`
`specifically Petitioner’s asserted ground with respect to claims 6 and 13.
`
`In conclusion, Petitioner has demonstrated, on the current record, a
`
`reasonable likelihood of prevailing on its assertion that claims 6 and 13
`
`would have been obvious over Yuzuriha and Nakagawa.
`
`
`
`D. Claims 7 and 14—Asserted Obviousness—Nakagawa
`Alone, or in Combination with Either Yuzuriha or Shukuri
`
`Petitioner contends claims 7 and 14 would have been obvious over
`
`Nakagawa alone, or in combination with either Yuzuriha or Shukuri, under
`
`35 U.S.C. § 103(a). Pet. 22-28, 41-56. We are not persuaded that Petitioner
`
`has established a reasonable likelihood of prevailing on its assertion that
`
`claims 7 and 14 would have bee