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`
`US 20030042520A1
`
`(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2003/0042520 A1
`Tsukamoto et al.
`(43) Pub. Date:
`Mar. 6, 2003
`
`(54) SEMICONDUCTOR INTEGRATED CIRCUIT
`DEVICE AND A METHOD OF
`MANUFACTURING THE SAME
`
`(75) Inventors: Keisuke Tsukamoto, Ome (JP);
`Yoshihiro Ikeda, Hamura (JP);
`Tsutomu ()kazaki, Ome (JP); Daisuke
`()kada, Kunitachi (JP); Hiroshi
`
`Yanagita, Hamura Correspondence Address:
`
`MILES & STOCKBRIDGE PC
`1751 PINNACLE DRIVE
`SUITE 500
`MCLEAN, VA 22102_3833 (Us)
`
`(73) Assignee; Hitachi, Ltd_
`
`(21) Appl, No;
`
`10/196,166
`
`(22) Filed:
`
`Jul. 17, 2002
`
`(30)
`
`Foreign Application Priority Data
`
`Aug. 31, 2001 (JP) .................................... .. 2001-263736
`
`Publication Classi?cation
`
`(51) Int. Cl.7 ................................................ .. H01L 27/108
`(52) US. Cl. ............................................................ .. 257/296
`
`Defects in element forming regions on Which memory cells
`of a non-volatile memory are formed are to be diminished to
`reduce leakage current. End portions of element forming
`regions With non-volatile memory cells formed thereon are
`extended a length D by utilizing the region Which underlies
`a dummy conductive ?lm, Whereby a stress induced from an
`insulating ?lm Which surrounds the element forming regions
`is concentrated on the extended region. As a result, defects
`do not extend up to the regions Where memory cells are
`formed and therefore it is possible to reduce leakage current
`in the memory cells.
`
`PERIPHERAL CIRCUIT
`FORMING REGION (PCFR)
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`IPR2014-00898
`Exhibit MX027II-1004, p. 1
`
`

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`|PR2014-00898
`Exhibit MX027II-1004, p. 2
`
`IPR2014-00898
`Exhibit MX027II-1004, p. 2
`
`
`
`
`

`

`Patent Application Publication
`
`Mar. 6, 2003 Sheet 2 0f 17
`
`US 2003/0042520 A1
`
`FIG. 2
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`IPR2014-00898
`Exhibit MX027II-1004, p. 3
`
`

`

`Patent Application Publication
`
`Mar. 6, 2003 Sheet 3 0f 17
`
`US 2003/0042520 A1
`
`FIG. 4
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`IPR2014-00898
`Exhibit MX027II-1004, p. 4
`
`

`

`Patent Application Publication
`
`Mar. 6, 2003 Sheet 4 0f 17
`
`US 2003/0042520 A1
`
`FIG. 7
`
`IPR2014-00898
`Exhibit MX027II-1004, p. 5
`
`

`

`Patent Application Publication
`
`Mar. 6, 2003 Sheet 5 0f 17
`
`US 2003/0042520 A1
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`IPR2014-00898
`Exhibit MX027II-1004, p. 6
`
`

`

`Patent Application Publication
`
`Mar. 6, 2003 Sheet 6 0f 17
`
`US 2003/0042520 A1
`
`IPR2014-00898
`Exhibit MX027II-1004, p. 7
`
`

`

`Patent Application Publication
`
`Mar. 6, 2003 Sheet 7 0f 17
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`US 2003/0042520 A1
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`IPR2014-00898
`Exhibit MX027II-1004, p. 8
`
`

`

`Patent Application Publication
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`Mar. 6, 2003 Sheet 8 0f 17
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`

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`Patent Application Publication
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`Mar. 6, 2003 Sheet 9 0f 17
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`US 2003/0042520 A1
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`IPR2014-00898
`Exhibit MX027II-1004, p. 10
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`Patent Application Publication
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`Mar. 6, 2003 Sheet 10 0f 17 US 2003/0042520 A1
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`Patent Application Publication
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`Mar. 6, 2003 Sheet 11 0f 17 US 2003/0042520 A1
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`IPR2014-00898
`Exhibit MX027II-1004, p. 12
`
`

`

`Patent Application Publication
`
`Mar. 6, 2003 Sheet 12 0f 17 US 2003/0042520 A1
`
`FIG. 17
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`IPR2014-00898
`Exhibit MX027II-1004, p. 13
`
`

`

`Patent Application Publication
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`Mar. 6, 2003 Sheet 13 0f 17 US 2003/0042520 A1
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`IPR2014-00898
`Exhibit MX027II-1004, p. 14
`
`

`

`Patent Application Publication
`
`Mar. 6, 2003 Sheet 14 0f 17 US 2003/0042520 A1
`
`FIG. 19
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`IPR2014-00898
`Exhibit MX027II-1004, p. 15
`
`

`

`Patent Application Publication
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`Mar. 6, 2003 Sheet 15 0f 17 US 2003/0042520 A1
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`IPR2014-00898
`Exhibit MX027II-1004, p. 16
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`

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`Patent Application Publication
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`Mar. 6, 2003 Sheet 16 0f 17
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`IPR2014-00898
`Exhibit MX027II-1004, p. 17
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`
`

`

`Patent Application Publication
`
`Mar. 6, 2003 Sheet 17 0f 17 US 2003/0042520 A1
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`IPR2014-00898
`Exhibit MX027II-1004, p. 18
`
`

`

`US 2003/0042520 A1
`
`Mar. 6, 2003
`
`SEMICONDUCTOR INTEGRATED CIRCUIT
`DEVICE AND A METHOD OF MANUFACTURING
`THE SAME
`
`BACKGROUND OF THE INVENTION
`
`[0001] The present invention relates to a semiconductor
`integrated circuit device and a method of manufacturing the
`same. Particularly, the present invention is concerned With a
`technique applicable effectively to a semiconductor inte
`grated circuit device in Which elongated element forming
`regions are formed side by side.
`
`[0002] A semiconductor integrated circuit device com
`prises elements and Wiring lines formed on main surfaces of
`element forming regions (active) each de?ned by an insu
`lating ?lm. For example, the element forming regions are
`isolated from each other by an element isolation region. The
`element isolation region is formed for example by an
`element isolating ?lm. For example, the element isolating
`?lm is formed With use of STI (ShalloW Trench Isolation)
`technique. According to this STI technique, an insulating
`?lm such as silicon oxide ?lm is deposited on a trench
`formed in a semiconductor substrate, then the silicon oxide
`?lm present outside the trench is removed, for example, by
`CMP (Chemical Mechanical Polishing), alloWing the silicon
`oxide ?lm to be buried in the interior of the trench, and the
`trench With the silicon oxide ?lm thus buried therein is used
`for the isolation betWeen elements.
`
`[0003] For example, a memory LSI (Large Scale Inte
`grated Circuit) such as an Electrically Erasable Program
`mable Read Only Memory (EEPROM) is formed on each of
`elongated element forming regions arranged side by side at
`a certain pitch.
`[0004] With microstructuriZation and high integration of
`memory cell, there is a tendency that such element forming
`regions become smaller in Width and are arranged at a
`narroWer pitch.
`
`[0005] As to a ?ash memory of NOR type With a drain
`contact formed using What is called SAC (Self-Aligned
`Contact) technique for coping With the tendency to micro
`structuriZation of memory cell, it is described, for example,
`in IEDM (International Electron Devices Meeting), 1998,
`pp.979-982, “A Novel 4.6F2NOR Cell Technology With
`Lightly Doped Source (LDS) Junction For High Density
`Flash Memories.”
`
`SUMMARY OF THE INVENTION
`
`[0006] Having made studies about semiconductor memo
`ries, especially such a non-volatile memory as mentioned
`above, the present inventors found out the folloWing prob
`lem not publicly knoWn.
`
`[0007] Defects of memory cells increase With miniatur
`iZation of elements. Through our studies about the cause of
`such an increase of defects We suspect that a crystal defect
`Which occurs at an end portion of an element forming region
`may be the cause.
`
`[0008] More particularly, in an outer periphery portion of
`memory cell forming regions Within a semiconductor inte
`grated circuit device there exists a peripheral circuit forming
`region in Which are formed a logic circuit, etc. (“peripheral
`circuits” hereinafter) necessary for driving memory cells.
`
`Thus, elongated element forming regions With memory cells
`formed thereon are arranged at a narroW pitch, and around
`those regions is disposed another element forming region
`With peripheral circuits formed thereon. These element
`forming regions are isolated using a Wide insulating ?lm.
`
`[0009] Therefore, as Will be fully described later in
`embodiments of the invention, there easily occur stress
`concentration and crystal defects at end portions of elon
`gated element forming regions With memory cells formed
`thereon.
`
`[0010] Once such a defect occurs, leakage current
`increases betWeen a drain region of each memory cell and a
`semiconductor substrate and also betWeen source and drain
`regions. Moreover, When the leakage current increases larger
`than the operating current of a sense ampli?er, a defect
`results.
`
`[0011] Further, as noted earlier, since plural memory cells
`are formed on an elongated element forming region, the
`occurrence of a defect even in one memory cell Will lead to
`defect of all memory cells connected to the same data line
`as that of the defective memory cell.
`
`[0012] It is an object of the present invention to diminish
`defects of a semiconductor substrate in element forming
`regions.
`[0013] It is another object of the present invention to
`diminish defects of a semiconductor substrate in element
`forming regions and thereby diminish leakage current.
`
`[0014] It is a further object of the present invention to
`diminish leakage current and thereby improve product yield
`and reliability.
`[0015] The above and other objects and novel features of
`the present invention Will become apparent from the fol
`loWing description and the accompanying draWings.
`[0016] Typical inventions disclosed herein Will be out
`lined beloW.
`[0017] (1) A semiconductor integrated circuit device
`comprising tWo or more element forming regions
`each having memory cells formed thereon and
`de?ned by an insulating ?lm, the element forming
`regions each extending in a ?rst direction and being
`arranged in a second direction perpendicular to t the
`?rst direction, end portions of the element forming
`regions being extended up to beloW a conductive
`?lm Which is formed so as to surround the memory
`cells.
`[0018] (2) A semiconductor integrated circuit device
`comprising tWo or more element forming regions
`each de?ned by an insulating ?lm and extending in
`a ?rst direction, the element forming regions being
`arranged in a second direction perpendicular to the
`?rst direction, end portions of the element forming
`regions being connected by a connecting portion
`Which extends in the second direction.
`
`[0019] (3) A semiconductor integrated circuit device
`comprising plural element forming regions each hav
`ing memory cells formed thereon and de?ned by an
`insulating ?lm, the element forming regions extend
`ing in a ?rst direction and being arranged in a second
`direction perpendicular to the ?rst direction, Wherein
`
`IPR2014-00898
`Exhibit MX027II-1004, p. 19
`
`

`

`US 2003/0042520 Al
`
`Mar. 6, 2003
`
`the Width in the second direction of an outmost
`element forming region out of the plural element
`forming regions is made larger than the Width of each
`of the other element forming region(s).
`
`[0020] (4) A semiconductor integrated circuit device
`comprising plural element forming regions each hav
`ing memory cells formed thereon and de?ned by an
`insulating ?lm, the element forming regions extend
`ing in a ?rst direction and being arranged in a second
`direction perpendicular to the ?rst direction, Wherein
`no cell functioning as a memory cell is formed on an
`outermost element forming region out of the plural
`element forming regions.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0021] FIG. 1 is a plan vieW of a principal portion of a
`substrate, shoWing a semiconductor integrated circuit device
`according to a ?rst embodiment of the present invention;
`
`[0022] FIG. 2 is a sectional vieW of a principal portion of
`the substrate in the semiconductor integrated circuit device
`of the ?rst embodiment;
`[0023] FIG. 3 is a sectional vieW of a principal portion of
`the substrate in the semiconductor integrated circuit device
`of the ?rst embodiment;
`[0024] FIG. 4 is a plan vieW of a principal portion of the
`substrate in the semiconductor integrated circuit device of
`the ?rst embodiment;
`
`[0025] FIG. 5 is a plan vieW of the principal portion;
`
`[0026] FIG. 6 is a sectional vieW of a principal portion of
`the substrate, shoWing a method of manufacturing the semi
`conductor integrated circuit device of the ?rst embodiment;
`
`[0027] FIG. 7 is a sectional vieW of the substrate principal
`portion in the manufacturing method;
`
`[0028] FIG. 8 is a sectional vieW of the substrate principal
`portion in the manufacturing method;
`
`[0029] FIG. 9 is a sectional vieW of the substrate principal
`portion in the manufacturing method;
`
`[0030] FIG. 10 is a sectional vieW of the substrate prin
`cipal portion in the manufacturing method;
`[0031] FIG. 11 is a sectional vieW of the substrate prin
`cipal portion in the manufacturing method;
`[0032] FIG. 12 is a sectional vieW of the substrate prin
`cipal portion in the manufacturing method;
`
`[0033] FIG. 13 is a plan vieW of a principal portion of a
`substrate, shoWing a semiconductor integrated circuit device
`according to a second embodiment of the present invention;
`
`[0034] FIG. 14 is a plan vieW of a principal portion of the
`substrate in the semiconductor integrated circuit device of
`the second embodiment;
`[0035] FIG. 15 is a plan vieW of a principal portion of the
`substrate in the semiconductor integrated circuit device of
`the second embodiment;
`
`[0036] FIG. 16 is a plan vieW of a principal portion of a
`substrate, shoWing a semiconductor integrated circuit device
`according to a third embodiment of the present invention;
`
`[0037] FIG. 17 is a plan vieW of a principal portion of the
`substrate in the semiconductor integrated circuit device of
`the third embodiment;
`[0038] FIG. 18 is a plan vieW of a principal portion of a
`substrate, shoWing a semiconductor integrated circuit device
`according to a fourth embodiment of the present invention;
`
`[0039] FIG. 19 is a sectional vieW of a principal portion
`of the substrate in the semiconductor integrated circuit
`device of the fourth embodiment;
`
`[0040] FIG. 20 is a sectional vieW of a principal portion
`of the substrate in the semiconductor integrated circuit
`device of the fourth embodiment;
`
`[0041] FIG. 21 is a plan vieW of a principal portion of the
`substrate in the semiconductor integrated circuit device of
`the fourth embodiment;
`[0042] FIG. 22 is a circuit diagram corresponding to the
`semiconductor integrated circuit device of the fourth
`embodiment; and
`[0043] FIG. 23 is a diagram shoWing a computer system
`using a semiconductor integrated circuit device according to
`the present invention.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`[0044] Embodiments of the present invention Will be
`described in detail hereinunder With reference to the accom
`panying drawings. In all of the drawings for illustrating the
`embodiments, portions Which exhibit the same functions are
`identi?ed by the same reference numerals and repeated
`explanations thereof Will be omitted.
`
`First Embodiment
`
`[0045] FIG. 1 is a plan vieW of a principal portion of a
`semiconductor integrated circuit device according to a ?rst
`embodiment of the present invention. In the same ?gure, the
`right-hand portion represents a memory cell forming region
`MCFR and the left-hand portion represents a peripheral
`circuit forming region PCFR. In the memory cell forming
`region MCFR, non-volatile memory cells of NOR type are
`arranged in the form of an array MCAR, While in the
`peripheral circuit forming region there are formed MISFETs
`S for selection as an example of peripheral circuits. FIG. 2
`is a schematic sectional vieW taken on line A-A in FIG. 1
`and FIG. 3 is a schematic sectional vieW taken on line B-B
`in FIG. 1.
`
`[0046] As shoWn in FIG. 1, in the memory cell forming
`region, element forming regions (active) Ac each extending
`in X direction are arranged at predetermined certain pitches
`in Y direction. The element forming regions Ac are each
`de?ned by an insulating ?lm 6, e.g., silicon oxide ?lm. That
`is, adjacent element forming regions Ac are isolated from
`each other through the insulating ?lm 6 Which is an element
`isolating ?lm. For example, as shoWn in FIGS. 2 and 3, the
`insulating ?lm 6 is formed by STI structure buried in a
`trench formed in a semiconductor substrate. In the element
`forming regions Ac, p-type Wells 8 are exposed to a surface
`of a semiconductor substrate 1.
`
`[0047] The Width W in Y direction of each element
`forming region is about 0.3 pm for example, the spacing SW
`
`IPR2014-00898
`Exhibit MX027II-1004, p. 20
`
`

`

`US 2003/0042520 A1
`
`Mar. 6, 2003
`
`between adjacent element forming regions Ac is about 0.4
`pm for example, and the length (width in X direction) of
`each element forming region is about 80 pm in correspon-
`dence to, for example, a 128-bit memory cell MC. In each
`element forming region there are formed plural memory
`cells MC in X direction.
`
`are
`forming regions Ac
`the element
`[0048] Above
`arranged control gates (second electrodes) CG at predeter-
`mined certain pitches, the control gates CG extending in Y
`direction. The width L in X direction of each control gate CG
`is about 0.3 pm for example and the spacing LS between
`adjacent control gates CG is about 0.35 pm for example. The
`control gates CG are formed integrally with control gates
`CG of memory cells MC arranged in Y direction and serve
`as word lines WL extending in Y direction.
`
`[0049] Between the control gates CG and the element
`forming regions Ac, as shown in FIGS. 2 and 3, are formed
`an insulating film comprising a laminate film (“ONO film”
`hereinafter) 21 of silicon oxide film, silicon nitride film and
`silicon oxide film laminated in this order, floating gates (first
`electrodes) FG, and a gate insulating film 9 formed by a
`thermal oxide film. The floating gates FG are each formed
`independently for each memory cell (see FIG. 3).
`
`In each of the element forming regions Ac located
`[0050]
`at both ends of the control gates CG there are formed n+-type
`semiconductor regions 17 (source and drain regions). On the
`drain region 17 is formed a plug (drain contact) DC (P1),
`while on the source region 17 is formed a plug (source
`contact) SC (P1). The plug DC (P1) is formed independently
`for each memory cell, while the plug SC (P1) is connected
`electrically to each of source regions 17 of memory cells MC
`connected to one and same word line and constitutes a
`
`source line SL extending in Y direction. That is, the plug
`(source contact) SC (P1) is a wiring line extending in Y
`direction and constitutes a source line SL. As will be
`
`described later, the plugs DC (P1) and SC (P1) are formed
`in the same manufacturing step.
`
`[0051] On the drain region 17 is formed a two-layer
`structure comprising plugs DC (P1) and DC (P2). On the
`plug DC (P2) is formed a sub bit line SBL which extends in
`X direction.
`
`[0052] As shown in FIG. 1, the plug SC (P1) is connected
`to a common source line CSL through the plug SC (P2). The
`common source line CSL also extends in X direction and is
`
`formed by the same wiring layer as the sub bit line SBL. The
`plugs DC (P2) and SC (P2) are formed in the same manu-
`facturing step.
`
`[0053] Thus, each memory cell MC is composed princi-
`pally of a pair of n+-type semiconductor regions 17 which
`are source and drain regions, a channel forming region
`(p-type well)8 (Ac) formed between those semiconductor
`regions, a gate insulating film 9 formed on the channel
`forming region, a floating gate FG formed on the gate
`insulating film 9, an insulating film 21 formed on the floating
`gate FG, and a control gate CG formed on the insulating film
`21. The source and drain regions 17 of memory cells MC
`adjacent to each other in Y direction are isolated by the
`insulating film 6 and the control gates CG of memory cells
`MC arranged in Y direction are formed integrally with the
`word lines WL. The drain regions 17 of memory cells MC
`arranged in Y direction are electrically connected to different
`
`sub bit lines SBL, and the source regions 17 of memory cells
`MC arranged in Y direction are electrically connected
`together through source lines SL. The drain regions of
`memory cells MC adjacent in X direction are constituted in
`common and are electrically connected to sub bit lines SBL.
`Likewise,
`the source regions 17 of memory cells MC
`adjacent in X direction are constituted in common and are
`electrically connected to source lines SL.
`
`[0054] The following description is now provided about
`write, read and erasing operations for each memory cell.
`
`[0055] Reference will first be made to a write operation.
`For writing data to a memory cell, a voltage of 9V for
`example is applied to the control gate CG (word line WL) of
`the memory cell, a voltage of 4V for example is applied to
`the drain region (sub bit line SBL) of the memory cell, a
`voltage of 3V for example is applied to the element forming
`region Ac (p-type well 8), and the source region (source line
`SL) of the memory cell is maintained at, for example, 0V
`(earth potential). As a result, hot electrons are generated in
`a channel region (source-to-drain region) of the memory cell
`and are injected into the floating gate FG.
`
`[0056] Next, a description will be given of a read opera-
`tion. For reading data from the memory cell, a voltage of
`2.7V for example is applied to the control gate CG (word
`line WL) of the memory cell, a voltage of 0.8V for example
`is applied to the drain region (sub bit line SBL) of the
`memory cell, and the element forming region Ac (p-type
`well 8) and the source region (source line SL) of the memory
`cell are maintained at 0V for example. At this time, data (“1”
`or “0”) of the memory cell is read out in accordance with
`whether an electric current flows or not between the source
`
`and drain regions of the memory cell. If the answer is
`affirmative, it is seen that electrons are not injected into the
`floating gate FG of the memory cell (the voltage level is
`below a threshold voltage) and that, for example, “0” data
`has been stored. On the other hand, if no current flows, it is
`seen that electrons are injected into the floating gate FG of
`the memory cell (the voltage level is above the threshold
`voltage) and that, for example, “1” data has been stored.
`
`[0057] A description will not be directed to an erasing
`operation. For erasing data stored in the memory cell, a
`voltage of 10.5V for example is applied to the control gate
`CG (word line WL) of the memory cell, a voltage of 10.5V
`for example is applied to the element forming region Ac
`(p-type well 8) and the drain region (sub bit line SBL) of the
`memory cell, and the source region (source line SL) of the
`memory cell is maintained in a floating state (open state). As
`a result, by FN (Fowler-Nordheim) tunneling, electrons are
`released from the control gate CG to the channel region
`(source-to-drain region) of the memory cell.
`
`[0058] A dummy conductive film DSG is formed in an
`outer periphery portion of the memory cell array by the same
`layer as the control gates CG. The dummy conductive film
`DSG is formed for diminishing the influence of dust par-
`ticles developed during the formation of memory cells and
`for eliminating the difference in height between the memory
`cell forming region and the peripheral circuit
`forming
`region.
`
`[0059] The dummy conductive film DSG is also formed
`on the element forming regions (p-type wells 8), and also
`between the dummy conductive film DSG and each element
`
`|PR2014-00898
`Exhibit MX027II-1004, p. 21
`
`IPR2014-00898
`Exhibit MX027II-1004, p. 21
`
`

`

`US 2003/0042520 A1
`
`Mar. 6, 2003
`
`forming region Ac are formed an insulating film, e.g., ONO
`film 21, a floating gate (first electrode) FG, and a gate
`insulating film 9, e.g., a thermal oxide film, (see FIGS. 2
`and 3).
`
`[0060] Also in the peripheral circuit forming region are
`formed element forming regions LAc for peripheral circuits.
`On the element forming regions LAc is formed a conductive
`film which constitutes gate electrodes G in MISFETs S for
`selection. As shown in FIG. 2, the gate electrodes G are
`formed by the same layer as the control gates CG and a gate
`insulating film 9b is formed under the gate electrodes G. In
`the element forming region LAc at both ends of each gate G
`are formed n+-type semiconductor regions 27 (source and
`drain regions).
`
`[0061] As shown in FIG. 1, the element forming regions
`Ac in the memory cell forming region each extend a length
`D in X direction from the drain region end of the memory
`cell located at an endmost position. In the length D, the
`distance d1 is a distance taking into account a displacement
`of a mask which is used in forming the element forming
`region Ac, while the distance d2 is a distance taking into
`account a crystal defect developing region. In this embodi-
`ment, d1 is about 0.2 pm and d2 is about 0.3 pm. This
`magnitude of d2 was set on the basis of the fact that the
`length of a crystal defect developed in an element forming
`region Ac during formation of memory cells in accordance
`with the foregoing rule was about 0.3 pm.
`
`[0062] Thus, in this embodiment, since an end portion of
`each element forming region Ac is extended, it is possible to
`avoid the influence of a crystal defect developed in the
`element forming region Ac. Consequently, it is possible to
`diminish the generation of leakage current and hence pos-
`sible to decrease the rate of occurrence of memory cell
`defects.
`
`[0063] More particularly, as shown in FIG. 4, the insu-
`lating film 6 is present between adjacent element forming
`regions Ac and a stress induced by the insulating film 6
`present along the outer peripheries of element forming
`regions Ac is imposed on the regions Ac. Particularly, since
`the insulating film 6 is formed over a wide range in the outer
`periphery portion of the memory cell forming region for the
`purpose of isolation form the peripheral circuit, there occurs
`a stress concentration at end portions of the element forming
`regions Ac. With such a large stress, there occur defects
`(Del, De2) such as dislocation within crystals which con-
`stitute the element forming regions Ac. Leakage current
`occurs through the defects, and if the leakage current
`becomes larger than the operating current of the sense
`amplifier, a defect results as noted earlier.
`
`In this embodiment, however, since end portions of
`[0064]
`the element forming regions Ac are extended, the defect De1
`does not extend to the region (memory cell array MCAR)
`where substantial memory cells are formed, so that it is
`possible to diminish the leakage current in each memory
`cell.
`
`[0065] On the extended portion of each element forming
`region Ac is formed a dummy conductive film DSG, and
`below the DSG are formed an insulating film, e. g., ONO film
`21, a floating gate (first electrode) FG, and a gate insulating
`film 9, e.g., thermal oxide film. Thus, this structure is a
`pseudo memory cell structure, provided a source region is
`
`not present. However, the dummy conductive film DSG is
`not applied with any potential and is in a floating state, so
`that no channel is formed, with no generation of leakage
`current.
`
`In this embodiment, since each element forming
`[0066]
`region Ac is extended by utilizing the space which underlies
`the dummy conductive film DSG, it is possible to take the
`measure against defects without enlarging the memory cell
`forming region.
`
`[0067] Next, an example of a method for manufacturing
`the semiconductor integrated circuit device of this embodi-
`ment will be described below. FIGS. 6 to 12 are sectional
`
`views of a principal portion of a substrate, showing how to
`manufacture the semiconductor integrated circuit device of
`this embodiment, of which FIGS. 6 to 8 correspond to C-C
`section in FIG. 1 and FIGS. 9 to 12 correspond to D-D
`section in FIG. 1.
`
`[0068] First, as shown in FIG. 6, a semiconductor sub-
`strate 1, which is formed by a p-type single crystal silicon
`having a resistivity of 1 to 10 Qcm or so,
`is thermally
`oxidized to form a pad oxide film (not shown) on the surface
`of the semiconductor substrate 1. Next, an insulating film,
`e.g., silicon nitride film (not shown), is deposited on the pad
`oxide film, and the silicon nitride film present on an element
`isolation region is removed using a photoresist film (simply
`“resist film” hereinafter) as mask.
`
`[0069] Next, the resist film is removed and the semicon-
`ductor substrate 1 is etched using the silicon nitride film as
`mask to form element isolation trenches 4 having a depth of
`about 250 nm.
`
`[0070] Thereafter, the semiconductor substrate 1 is sub-
`jected to dry oxidation at about 1150° C. to form a thermal
`oxide film such as a silicon oxide film 5 having a thickness
`of about 30 nm on inner walls of the trenches. The silicon
`
`oxide film 5 is formed for remedying damages caused by dry
`etching on the inner walls of the trenches and for relieving
`stress induced at the interface between a silicon oxide film
`
`6 to be buried within the trenches in the next step and the
`semiconductor substrate 1.
`
`[0071] Next, an insulating film constituted by a silicon
`oxide film 6 having a thickness of about 600 nm for example
`is deposited on the semiconductor substrate 1 including the
`interiors of the element isolation trenches 4 by CVD, fol-
`lowed by heat-treatment (annealing) at 1150° C. for 60
`minutes to densify the silicon oxide film 6. Then, the silicon
`oxide film 6 present on the trenches is polished by CMP to
`flatten the film surface and thereafter the silicon nitride film
`is removed. At this time, the surface of the silicon oxide film
`6 projects from the surface of the semiconductor substrate 1
`by an amount corresponding to the thickness of the silicon
`nitride film, but the surface of the silicon oxide film 6 will
`retract gradually by subsequent washing step for the semi-
`conductor substrate 1 and surface oxidation and oxide film
`
`removing step.
`
`[0072] Through the above steps there is formed an element
`isolation region with silicon oxide film 6 buried within the
`element isolation trenches 4.
`
`the surface of the
`[0073] Next, as shown in FIG. 7,
`semiconductor substrate 1 is subjected to wet washi