(12) United States Patent
`YuZuriha et al.
`
`US006458655B1
`US 6,458,655 B1
`Oct. 1, 2002
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`(54) METHOD OF MANUFACTURING
`SEMICONDUCTOR DEVICE AND FLASH
`MEMORY
`
`(75) Inventors: Kojiro Yuzuriha, Hyogo (JP); Shu
`Shimizu, Hyogo (JP); Tamotsu
`Tanaka, Hyogo (JP); Takashi Yano,
`Hyogo (JP)
`
`(73) Assignees: Mitsubishi Denki Kabushiki Kaisha,
`Tokyo (JP); Ryoden Semiconductor
`System Engineering, Hyogo (JP)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 09/588,475
`(22) Filed:
`Jun. 7, 2000
`(30)
`Foreign Application Priority Data
`
`Jan. 17, 2000
`
`(JP) . . . . . .
`
`. . . . .. 2000-007585
`
`(51) Int. C1.7 ........................... .. H01L21/336
`
`(52) U.S.Cl. ..................... .. 438/257;438/264;438/266;
`438/593; 438/594; 438/763; 438/689; 438/695;
`438/706; 438/725
`(58) Field of Search ............................... .. 438/257, 266,
`438/264, 593, 594, 763, 689, 695, 706,
`725
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,210,047 A * 5/1993 W00 et a1. .................. .. 437/43
`5,460,991 A * 10/1995 HOng ........................ .. 437/43
`5,631,178 A * 5/1997 Vogel et 211.
`5,789,293 A * 8/1998 ChO et al. ................. .. 438/257
`6,040,216 A * 3/2000
`6,117,732 A * 9/2000 Chu et al. ................. .. 438/264
`
`* cited by examiner
`
`Primary Examiner—Michael Sherry
`Assistant Examiner—Lisa Kilday
`(74) Attorney, Agent, or Firm—McDermott, Will & Emery
`(57)
`ABSTRACT
`
`A semiconductor manufacturing method is mainly
`contemplated, improved to prevent an altered surface layer
`of a resist from being removed When a single patterned resist
`is used to provide dry-etch and Wet-etch successively. On a
`semiconductor substrate an insulation ?lm and a conductive
`layer are formed successively. On the conductive layer a
`patterned resist is formed. With the patterned resist used as
`a mask, the conductive layer is dry-etched. A surface layer
`of the patterned resist is partially removed. With the pat
`terned resist used as a mask, the insulation ?lm is Wet
`etched.
`
`5 Claims, 12 Drawing Sheets
`
`lLMEMORY CELL REGION
`
`,\
`
`DUMMY GATE PERIPHERAL
`REG/ION
`\QCIRCUITRLI REGION
`16 1011131161108 14
`/
`
`16
`
`13
`
`16
`13
`11
`10
`
`911910 9
`
`16
`13
`
`IPR2014-00898
`Exhibit MX027II-1003, p. 1
`
`

`

`U.S. Patent
`US. Patent
`
`0a. 1, 2002
`Oct. 1, 2002
`
`Sheet 1 0f 12
`Sheet 1 0f 12
`
`US 6,458,655 B1
`US 6,458,655 B1
`
`FIG. 1
`FIG. 1
`
`1 I I l i l l | I I II
`
`
`
`FIG. 2
`
`
`
`|PR2014-00898
`Exhibit MX027II-1003, p. 2
`
`IPR2014-00898
`Exhibit MX027II-1003, p. 2
`
`

`

`U.S. Patent
`
`0a. 1, 2002
`
`Sheet 2 0f 12
`
`US 6,458,655 B1
`
`FIG. 3
`
`DUV/7///////
`
`2*’b1/
`1
`
`11/1/1111
`
`2W1! III/11111113
`1
`
`IPR2014-00898
`Exhibit MX027II-1003, p. 3
`
`

`

`U.S. Patent
`
`0a. 1, 2002
`
`Sheet 3 0f 12
`
`US 6,458,655 B1
`
`FIG. 5
`
`DUMMY GATE PERIPHERAL
`léMEMORY CELL REGION I REGiION
`\JCIRCUITRII REGION
`
`1
`
`16
`
`13
`11
`10
`
`16
`
`13
`
`l
`l
`16 1011131181061 14
`/
`
`71
`
`16
`13
`
`911910 9
`
`8
`
`12
`
`IPR2014-00898
`Exhibit MX027II-1003, p. 4
`
`

`

`U.S. Patent
`US. Patent
`
`0a. 1, 2002
`Oct. 1, 2002
`
`Sheet 4 0f 12
`Sheet 4 0f 12
`
`US 6,458,655 B1
`US 6,458,655 B1
`
`FIG. 7
`FIG. 7
`
`
`
`
`
`.-
`
`Il/.........
`
`FIG. 8
`
`
`
`
`
`
`
`11 {II/IIIIIIIIIIIIIII 1” ‘
`
`
`
`
`
`IPR2014-00898
`Exhibit MX027II-1003, p. 5
`
`

`

`U.S. Patent
`
`0a. 1, 2002
`
`Sheet 5 0f 12
`
`US 6,458,655 B1
`
`“Wk/4
`
`m m
`
`a
`
`Mm/
`
`m 8
`
`M 2
`
`w m
`
`FIG. 10
`
`16 1316
`
`16101113113108 14
`/
`z
`16
`
`6 4|
`
`3 1091
`
`11
`
`63
`
`911910
`
`9
`
`12
`
`IPR2014-00898
`Exhibit MX027II-1003, p. 6
`
`

`

`U.S. Patent
`
`061. 1, 2002
`
`Sheet 6 6f 12
`
`US 6,458,655 B1
`
`FIG. 11
`
`PRIOR ART
`
`13312
`
`FIG. 12
`
`PRIOR ART
`
`IIIIIIIIIIIIIIRS
`
`1a
`
`FIG. 13
`
`PRIOR ART
`
`\év
`\
`\ \\\
`9
`(/////////////AL 8
`I\
`\\ \ ‘k4
`
`V‘MMTZ
`
`IPR2014-00898
`Exhibit MX027II-1003, p. 7
`
`

`

`U.S. Patent
`
`0a. 1, 2002
`
`Sheet 7 0f 12
`
`US 6,458,655 B1
`
`FIG. 14 PRIOR ART
`
`~14
`
`W2
`igggwg
`
`1W8
`
`A“
`
`3
`
`4
`
`8
`
`FIG. 15
`
`PRIOHIART
`
`9 ¢ ,¢
`
`¥\\\\
`
`I
`
`LIV
`
`7 I
`T4
`\8
`
`15
`
`2b
`1a
`
`IPR2014-00898
`Exhibit MX027II-1003, p. 8
`
`

`

`US. Patent
`
`Oct. 1 2002
`
`Sheet 8 0f 12
`
`FIG. 16
`
`PRIOR ART
`
`
`
`IPR2014-00898
`Exhibit MX027II-1003, p. 9
`
`

`

`U.S. Patent
`US. Patent
`
`0a. 1, 2002
`Oct. 1, 2002
`
`Sheet 9 0f 12
`Sheet 9 0f 12
`
`US 6,458,655 B1
`US 6,458,655 B1
`
`FIG. 18
`FIG. 18
`
`_ _ _ _ _ _ _ _ - - _ _ _ - ~ _ _ _ _ - _ _ _ _.‘
`
`
`
`IPR2014-00898
`Exhibit MX027II-1003, p. 10
`
`

`

`U.S. Patent
`
`0a. 1, 2002
`
`Sheet 10 0f 12
`
`US 6,458,655 B1
`
`FIG.2O
`
`“N7 ///////
`
`FIG. 21
`
`1%\\\\\\
`
`WIIII/IIIIIIIIIL
`
`IPR2014-00898
`Exhibit MX027II-1003, p. 11
`
`

`

`U.S. Patent
`
`0a. 1, 2002
`
`Sheet 11 0f 12
`
`US 6,458,655 B1
`
`H6. 22
`
`VCC
`
`ACCESS
`TRANS'STOR 1
`
`BIT \
`
`TRANSISTORZ
`
`77
`GND
`
`WL
`ACCESS
`TRANSISTOR 2
`
`/ BIT
`
`|__|
`STORAGE
`NODE2
`
`I:
`
`DRIVER
`TRANsIsToRI
`
`L
`
`P WELL
`
`N SUBSTRATE
`
`52
`
`i151
`
`IPR2014-00898
`Exhibit MX027II-1003, p. 12
`
`

`

`U.S. Patent
`US. Patent
`
`0a. 1, 2002
`Oct. 1, 2002
`
`Sheet 12 0f 12
`Sheet 12 0f 12
`
`US 6,458,655 B1
`US 6,458,655 B1
`
`FIG. 24
`FIG. 24
`
`56
`
`Wk V ::
`
`
`
`FIG. 25
`FIG. 25
`
`
`m/y»;
`
`
`
`
`|PR2014-00898
`Exhibit MX027II-1003, p. 13
`
`IPR2014-00898
`Exhibit MX027II-1003, p. 13
`
`

`

`US 6,458,655 B1
`
`1
`METHOD OF MANUFACTURING
`SEMICONDUCTOR DEVICE AND FLASH
`MEMORY
`
`BACKGROUND OF THE INVENTION
`
`2
`A ?ash memory con?gured as described above is manu
`factured by a method as described beloW.
`Initially, as shoWn in FIG. 12, an element isolating oxide
`?lm is formed on a semiconductor substrate 1 of monoc
`rystalline silicon to isolate memory cells from each other,
`isolate transistors in peripheral circuitry from each other,
`and isolate the cells and the peripheral transistors from each
`other. Then p doped region 1a in Which memory cells are to
`be formed is formed. Then the substrate’s upper surface is
`oxidiZed to provide a tunnel insulation ?lm 3 of silicon
`dioxide (SiOZ).
`Referring to FIG. 13, chemical vapor deposition (CVD) is
`employed to deposit polycrystalline silicon on tunnel insu
`lation ?lm 3. The polycrystalline silicon only in the memory
`cell region is etched in an x direction (a direction horiZontal
`relative to the plane of the ?gure, not shoWn) to form a
`?oating gate 4. Then, chemical vapor deposition is similarly
`employed to form an insulation ?lm 8, such as a silicon
`nitride (SiN) ?lm, a silicon oxide ?lm. Then, insulation ?lm
`8, the polycrystalline silicon and tunnel insulation ?lm 3 are
`removed in the peripheral-circuitry region. Then, as in
`forming polycrystalline silicon (?oating gate) 4, chemical
`vapor deposition is employed to deposit polycrystalline
`silicon serving as control gate 9.
`Then, as shoWn in FIG. 14, on a region With polycrys
`talline silicon that is desired as a gate electrode a patterned
`photoresist 14 is provided in a y direction (a direction
`vertical relative to the plane of the ?gure). With patterned
`photoresist 14 used as a mask, the region is anisotropically
`etched to expose a surface of tunnel insulation ?lm 3.
`Then, patterned resist 14 is for example plasma-ashed and
`thus removed.
`As shoWn in FIG. 15, dopant ions are introduced in a
`direction indicated by an arroW 15 to form at an upper
`portion of p doped region 1a heavily n doped regions
`(source/drain regions) 2a and 2b higher in dopant concen
`tration than p doped region 1a. Then, as shoWn in FIG. 11,
`chemical vapor deposition or the like is employed to provide
`insulation layers 10 and 11 formed of silicon oxide ?lm and
`serving as a passivation ?lm to complete a ?ash memory.
`The semiconductor device manufacturing method as
`above has a disadvantage described beloW With reference to
`simpli?ed draWings.
`As shoWn in FIG. 16, on a silicon substrate 1 a SiO2 ?lm
`2 is formed. On SiO2 ?lm 2 a polysilicon ?lm 3 is deposited.
`On polysilicon ?lm 3 a patterned photoresist 4 is provided
`by photolithography. With patterned resist 4 used as a mask,
`polysilicon ?lm 3 is dry-etched and then successively SiO2
`?lm 2 is etched With a hydro?uoric acid solution.
`In the hydro?ouric acid solution process, hoWever, When
`polysilicon ?lm 3 is dry-etched an altered surface layer 5 of
`patterned photoresist 4 is removed, as shoWn in FIG. 17.
`Removed surface layer 5 of the resist adheres onto silicon
`substrate 1 and thus disadvantageously prevents the under
`lying SiO2 ?lm 2 from being etched. Furthermore, removed
`surface layer 5 of the resist disadvantageously ?oWs into the
`hydro?uoric acid treatment bath and as a foreign matter
`contaminates the bath.
`Furthermore, such problem tends to occur particularly
`When polysilicon is etched With chloride type gas.
`Furthermore, such problem also tends to occur When With
`a polysilicon ?lm having an insulation ?lm such as SiO2
`?lm, SiN ?lm deposited thereon the SiOZ/SiN ?lm is dry
`etched, the polysilicon ?lm is dry-etched and the SiO2 ?lm
`is then Wet-etched With hydro?uoric acid solution succes
`sively.
`
`15
`
`25
`
`1. Field of the Invention
`The present invention relates generally to methods of
`manufacturing semiconductor devices and particularly to
`methods of manufacturing semiconductor devices including
`a step of dry etch and Wet etch provided successively. The
`present invention also relates to methods of manufacturing
`?ash memories including a step of dry etch and Wet etch
`provided successively. The present invention also relates to
`?ash memories manufactured by such manufacturing meth
`ods. The present invention also relates to methods of manu
`facturing static random access memories (SRAMs).
`2. Description of the Background Art
`FIG. 11 shoWs a cross section of a memory cell of a
`conventional ?ash memory.
`Referring to FIG. 11, in a surface of a semiconductor
`substrate containing a p dopant a p doped region 1a is
`formed. On semiconductor substrate 1 a ?oating gate 4 is
`formed With a tunnel oxide ?lm 3 posed therebetWeen. In a
`surface of p doped region 1a on opposite sides of ?oating
`gate 4, source/drain regions 2a and 2b are formed. On
`?oating gate 4 an insulation ?lm 8 is formed. On insulation
`?lm 8 a control gate 9 is formed. On semiconductor sub
`strate 1, insulation layers 10 and 11 are formed such that they
`cover control gate 9.
`The ?ash memory operates as described beloW.
`In Write operation, drain region 2b receives a drain
`voltage of approximately 6 to 8V and control gate 9 receives
`a gate voltage of approximately 10 to 15V. Source region 2a
`and semiconductor substrate 1 have a voltage held at a
`35
`ground voltage. As such a current of several hundreds pA
`?oWs through a channel region 2c. Of the electrons ?oWing
`from source region 2a to drain region 2b, the electrons
`accelerated in a vicinity of drain region 2b becomes those
`With high energy (i.e., hot electrons). Such electrons ?oW in
`a direction indicated by an arroW 12 due to an electric ?eld
`resulting from the gate voltage applied to control gate 9, and
`are thus introduced into ?oating gate 4. As such electrons
`accumulate in ?oating gate 4, the transistor’s threshold
`voltage is increased. Such threshold voltage higher than a
`predetermined value corresponds to a state. referred to as
`“0”.
`In data erase operation, initially source region 2a receives
`a source voltage of approximately 10 to 15V and control
`gate 9 and semiconductor substrate 1 are held at a ground
`potential. Then, drain region 2b is ?oated, and an electric
`?eld resulting from the source voltage applied to source
`region 2a alloWs the electrons accumulated in ?oating gate
`4 to ?oW in a direction indicated by an arroW 13, passing
`through tunnel insulation ?lm 3 into semiconductor sub
`strate 1. When the electrons accumulated internal to ?oating
`gate 4 are extracted, the transistor’s threshold is increased.
`Such threshold voltage loWer than a predetermined value
`corresponds to a state With data erased, referred to as “1”.
`Such erasure alloWs collective erasure of memory cells
`formed in a single semiconductor device. In read operation,
`control gate 9 receives a gate voltage of approximately 5V
`and drain region 2b receives a drain voltage of approxi
`mately 1 to 2V, and then if channel region 2c passes current
`or the transistor is ON then data is determined to be “1” and
`if channel region 2c does not pass current or the transistor is
`OFF then data is determined to be “0”.
`
`45
`
`55
`
`65
`
`IPR2014-00898
`Exhibit MX027II-1003, p. 14
`
`

`

`US 6,458,655 B1
`
`3
`SUMMARY OF THE INVENTION
`The present invention has been made to solve such
`disadvantages as described above.
`The present invention contemplates an improved semi
`conductor manufacturing method capable of preventing
`removal of an altered surface layer of a patterned photore
`sist.
`The present invention also contemplates an improved
`?ash memory manufacturing method preventing removal of
`an altered surface layer of a patterned photoresist.
`The present invention also contemplates an improved
`static random access memory manufacturing method pre
`venting removal of an altered surface layer of a patterned
`photoresist.
`In accordance With the present invention in one aspect a
`semiconductor device manufacturing method includes the
`steps of: initially forming on a semiconductor substrate an
`insulation ?lm and a conductive layer successively by either
`deposition or deposition folloWed by patterning (step 1);
`forming a patterned resist on the conductive layer (step 2);
`With the patterned resist used as a mask, dry-etching the
`conductive layer (step 3); partially removing a surface layer
`of the patterned resist (step 4); and With the patterned resist
`used as a mask, etching the insulation ?lm.
`In accordance With the present invention, partially remov
`ing a surface layer of the patterned resist alloWs removal of
`an altered surface of the patterned resist.
`In accordance With the present invention in a second
`aspect a semiconductor device manufacturing method pro
`vides step 4 using an O2 plasma etch to partially remove a
`surface layer of the patterned resist.
`In accordance With the present invention in a third aspect
`a semiconductor device manufacturing method includes
`using an O2 mixed gas to dry-etch the conductive layer in
`step 3 and thus providing step 4 in the sequence of dry
`etching the conductive layer.
`In accordance With the present invention in a fourth aspect
`a semiconductor device manufacturing method includes the
`steps of: forming on a semiconductor substrate an insulation
`?lm and a conductive layer successively by either deposition
`or deposition folloWed by patterning (step 1); forming a
`patterned resist on the conductive layer (step 2); With the
`patterned resist used as a mask, dry-etching the conductive
`layer (step 3); joining together an altered surface layer of the
`patterned resist and a normal layer of the patterned resist
`underlying the surface thereof, and thus preventing the
`altered layer and the normal layer from being removed (step
`4); and With the patterned resist used as a mask, etching the
`insulation ?lm (step 5).
`In accordance With the present invention, an altered
`surface layer of a patterned resist and a normal layer of the
`patterned resist underlying the surface thereof can be joined
`together and thus prevented from being removed.
`In accordance With the present invention in a ?fth aspect
`a semiconductor device manufacturing method includes in
`step 4 the step of illuminating a surface of the patterned
`resist in a N2 ambient With a deep ultraviolet light and
`subsequently thermally processing the same.
`In accordance With the present invention in a siXth aspect
`a semiconductor device manufacturing method includes in
`step 4 the step of illuminating a surface of the patterned
`resist in a dry air With a deep ultraviolet light and subse
`quently thermally processing the patterned resist.
`In accordance With the present invention in a seventh
`aspect a semiconductor device manufacturing method pro
`vides step 4 by thermally processing the patterned resist in
`a dry air.
`
`10
`
`15
`
`25
`
`35
`
`45
`
`55
`
`65
`
`4
`In accordance With the present invention in an eighth
`aspect a ?ash memory manufacturing method includes the
`steps of: forming on a surface of a semiconductor substrate
`an isolating oXide ?lm isolating a memory cell region and a
`peripheral circuitry region from each other (step 1); forming
`a tunnel oXide ?lm on a surface of the semiconductor
`substrate (step 2); forming a ?rst polysilicon layer on the
`tunnel oXide ?lm (step 3); patterning the tunnel oXide ?lm
`and the ?rst polysilicon layer as desired (step 4); forming an
`insulation ?lm on the ?rst polysilicon layer (step 5); forming
`on the insulation ?lm a patterned resist having an end
`positioned on the isolating oXide ?lm and covering only the
`memory cell region (step 6); With the patterned resist used
`as a mask, dry-etching and thus removing the insulation ?lm
`and the ?rst polysilicon layer that overlie the peripheral
`circuitry region (step 7); partially removing a surface of the
`patterned resist (step 8); With the patterned resist used as a
`mask, removing the tunnel oXide ?lm overlying the periph
`eral circuitry region (step 9); removing the patterned resist
`(step 10); forming on the semiconductor substrate and on the
`peripheral circuitry region a gate oXide ?lm for a peripheral
`transistor (step 11); forming a second polysilicon layer on
`the semiconductor substrate (step 12); forming on the sec
`ond polysilicon layer an oXide ?lm used as an etching mask
`(step 13); forming a control gate in the memory cell region
`and forming a transistor gate for the peripheral circuitry
`(step 14); and patterning the insulation ?lm and the ?rst
`polysilicon layer and forming a ?oating gate (step 15).
`In accordance With the present invention, partially remov
`ing a surface layer of a patterned resist alloWs removal of an
`altered surface layer of the patterned resist.
`In accordance With the present invention in a ninth aspect
`a ?ash memory includes a semiconductor substrate. On the
`semiconductor substrate a dummy gate region is provided.
`On the semiconductor substrate a memory cell region and a
`peripheral circuitry region are provided to sandWich the
`dummy gate region. The dummy gate region includes an
`isolating oXide ?lm formed on the semiconductor substrate.
`On the isolating oXide ?lm a ?rst conductive layer is
`provided having an end closer to the peripheral circuitry
`region that recedes toWards the memory cell region. On the
`?rst conductive layer an insulation layer is provided having
`an end closer to the peripheral circuitry region that recedes
`toWards the memory cell region. On the isolating oXide ?lm
`a second conductive layer is provided covering the ?rst
`conductive layer and the insulation layer.
`In accordance With the present invention in a tenth aspect
`a semiconductor device manufacturing method in the ?rst or
`fourth aspect uses a polysilicon ?lm as the conductive layer
`and dry-etches the conductive layer With a chloride-type gas.
`In accordance With the present invention in an eleventh
`aspect, a ?ash memory manufacturing method in the eighth
`aspect at step 6 uses a chlorine gas to dry-etch the patterned
`resist.
`In accordance With the present invention in a tWelfth
`aspect a semiconductor device manufacturing method
`include the steps of: initially forming on a semiconductor
`substrate an insulation ?lm and a conductive layer succes
`sively (step 1); forming a second insulation ?lm (step 2);
`forming a patterned resist on the second insulation ?lm (step
`3); With the patterned resist used as a mask, dry-etching the
`second insulation ?lm and the conductive layer (step 4);
`partially removing a surface layer of the patterned resist
`(step 5); and With the patterned resist used as a mask, etching
`the insulation ?lm (step 6).
`In accordance With the present invention in a thirteenth
`aspect a semiconductor manufacturing method provides step
`
`IPR2014-00898
`Exhibit MX027II-1003, p. 15
`
`

`

`US 6,458,655 B1
`
`5
`5 using an 02 plasma etch to partially remove a surface of
`the patterned resist.
`In accordance With the present invention in a fourteenth
`aspect a semiconductor device manufacturing method
`includes step 4 using an 02 mixed gas to dry-etch the second
`insulation ?lm and the conductive layer and thus provides
`step 5 in the sequence of dry-etching the conductive layer.
`In accordance With the present invention in a ?fteenth
`aspect a semiconductor device manufacturing method
`includes the steps of: initially forming on a semiconductor
`substrate an insulation ?lm and a conductive layer succes
`sively (step 1); forming a second insulation ?lm (step 2);
`forming a patterned resist on the conductive layer (step 3);
`With the patterned resist used as a mask, dry-etching the
`conductive layer (step 4); joining together an altered surface
`layer of the patterned resist and a normal layer of the
`patterned resist underlying the surface layer thereof and thus
`preventing the altered surface layer and the normal layer
`from being removed (step 5); and With the patterned resist
`used as a mask, etching the insulation ?lm (step 6).
`In accordance With the present invention in a siXteenth
`aspect a semiconductor device manufacturing method
`includes in step 5 the step of illuminating a surface of the
`patterned resist in a N2 ambient With a deep ultraviolet light
`and subsequently thermally processing the patterned resist.
`In accordance With the present invention in a seventeenth
`aspect a semiconductor device manufacturing method
`includes in step 5 the step of illuminating a surface of the
`patterned resist in dry air With a deep ultraviolet light and
`subsequently thermally processing the patterned resist.
`In accordance With the present invention in an eighteenth
`aspect a semiconductor manufacturing method provides step
`5 thermally processing the patterned resist in a dry air.
`In accordance With the present invention in a nineteenth
`aspect a ?ash memory manufacturing method includes the
`steps of: initially forming on a surface of a semiconductor
`substrate an isolating oXide ?lm isolating a memory cell
`region and a peripheral circuitry region from each other
`(step 1); forming a tunnel oXide ?lm on a surface of the
`semiconductor substrate (step 2); forming a ?rst polysilicon
`layer on the tunnel oXide ?lm (step 3); patterning the tunnel
`oXide ?lm and the ?rst polysilicon layer as desired (step 4);
`forming an insulation ?lm on the ?rst polysilicon layer (step
`5); forming on the insulation ?lm a patterned resist having
`an end positioned on the isolating oXide ?lm and covering
`only the memory cell region (step 6); With the patterned
`resist used as a mask, dry-etching and thus removing the
`insulation ?lm and the ?rst polysilicon layer that overlie the
`peripheral circuitry region (step 7); using 02 plasma to etch
`and thus partially remove a surface layer of the patterned
`resist (step 8); With the patterned resist used as a mask,
`removing the tunnel oXide ?lm overlying the peripheral
`circuitry region (step 9); removing the patterned resist (step
`10); forming on the semiconductor substrate and on the
`peripheral circuitry region a gate oXide ?lm for a peripheral
`transistor (step 11); forming a second polysilicon layer on
`the semiconductor substrate (step 12); forming on the sec
`ond polysilicon layer an oXide ?lm used as an etching mask
`(step 13); forming a control gate. in the memory cell region
`and forming a transistor gate for the peripheral circuitry
`(step 14); and patterning the insulation ?lm and the ?rst
`polysilicon layer and forming a ?oating gate (step 15).
`In accordance With the present invention in a tWentieth
`aspect a ?ash memory manufacturing method is character
`iZed in that in step 7 the insulation ?lm and the ?rst
`polysilicon layer are dry-etched With an 02 mixed gas and
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`that in step 8 the patterned resist’s surface layer is partially
`removed in the dry-etching sequence.
`In accordance With the present invention in a tWenty-?rst
`aspect a ?ash memory manufacturing method includes the
`steps of: initially forming on a surface of a semiconductor
`substrate an isolating oXide ?lm isolating a memory cell
`region and a peripheral circuitry region from each other
`(step 1); forming a tunnel oXide ?lm on a surface of the
`semiconductor substrate (step 2); forming a ?rst polysilicon
`on the tunnel oXide ?lm (step 3); patterning the tunnel oXide
`?lm and the ?rst polysilicon layer, as desired (step 4);
`forming an insulation ?lm on the ?rst polysilicon layer (step
`5); forming on the isolation ?lm a patterned resist having an
`end positioned on the isolating oXide ?lm and covering only
`the memory cell region (step 6); With the patterned resist
`used as a mask, dry-etching and thus removing the insulation
`?lm and the ?rst polysilicon layer that overlie on the
`peripheral circuitry region (step 7); joining together an
`altered surface layer of the patterned resist and a normal
`portion of the patterned resist underlying the surface layer
`thereof and thus preventing the altered surface layer and the
`underlying normal portion from being removed (step 8);
`With the patterned resist used as a mask, removing the tunnel
`oXide ?lm overlying the peripheral circuitry region (step 9);
`removing the patterned resist (step 10); forming on the
`semiconductor substrate and on the peripheral circuitry
`region a gate oXide ?lm for a peripheral transistor (step 11);
`forming a second polysilicon layer on the semiconductor
`substrate (step 12); forming on the second polysilicon layer
`an oXide ?lm used as an etching mask (step 13); forming a
`control gate in the memory cell region and forming a
`transistor gate for the peripheral circuitry (step 14); and
`patterning the insulation ?lm and the ?rst polysilicon layer
`and forming a ?oating gate (step 15).
`In accordance With the present invention in a tWenty
`second aspect a ?ash memory manufacturing method
`includes step 8 illuminating a surface of the patterned resist
`in a N2 ambient With a deep ultraviolet light and thermally
`processing the patterned resist.
`In accordance With the present invention in a tWenty-third
`aspect a ?ash memory manufacturing method includes step
`8 illuminating a surface of the patterned resist in a dry air
`With a deep ultraviolet light and thermally processing the
`patterned resist.
`In accordance With the present invention in a tWenty
`fourth aspect a ?ash memory manufacturing method
`includes step 8 thermally processing the patterned resist in
`a dry air.
`In accordance With the present invention in a tWenty-?fth
`aspect an SRAM manufacturing method includes the steps
`of: initially forming an isolating oXide ?lm on a surface of
`a semiconductor substrate (step 1); depositing a gate oXide
`?lm on the semiconductor substrate (step 2); depositing a
`?rst polysilicon layer on the gate oXide ?lm (step 3); forming
`a patterned resist having an opening extending from an
`active region to the isolating oXide ?lm (step 4); With the
`patterned resist used as a mask, dryetching and thus remov
`ing the ?rst polysilicon layer (step 5); partially removing a
`surface layer of the patterned resist (step 6); again With the
`patterned resist used as a mask, removing the gate oXide ?lm
`at a bottom of the patterned resist (step 7); removing the
`patterned resist (step 8); forming a second polysilicon layer
`(step 9); forming of resist a pattern providing a gate elec
`trode of an access transistor, a pattern providing a gate
`electrode of a driver transistor and a pattern providing a gate
`electrode of a transistor for peripheral circuitry (step 10);
`
`IPR2014-00898
`Exhibit MX027II-1003, p. 16
`
`

`

`US 6,458,655 B1
`
`7
`With the patterned resist used as a mask, dry-etching the ?rst
`and second polysilicon layers (step 11); removing the pat
`terned resist (step 12); doping only an n region With an n
`dopant (step 13); and thermally processing a resultant prod
`uct (step 14).
`In accordance With the present invention in a tWenty-siXth
`aspect an SRAM manufacturing method includes step 6
`using an O2 plasma etch and thus partially remove a surface
`of the patterned resist.
`In accordance With the present invention in a tWenty
`seventh aspect an SRAM manufacturing method includes in
`step 5 using an O2 miXed gas to dry-etch the ?rst polysilicon
`layer and in step 6 partially removing a surface layer of the
`patterned resist in the dry-etching sequence.
`In accordance With the present invention in a tWenty
`eighth aspect an SRAM manufacturing method includes the
`steps of: initially forming an isolating oXide ?lm on a surface
`of a semiconductor substrate (step 1); depositing a gate
`oXide ?lm on the semiconductor substrate (step 2); depos
`iting a ?rst polysilicon layer on the gate oXide ?lm (step 3);
`forming a patterned resist having an opening extending from
`an active region to the isolating oXide ?lm (step 4); With the
`patterned resist used as a mask, dryetching and thus remov
`ing the ?rst polysilicon layer (step 5); joining together an
`altered surface layer of the patterned resist and a normal
`portion of the patterned resist underlying the altered surface
`layer thereof and thus preventing the altered surface layer
`and the normal portion from being removed (step 6); again
`With the patterned resist used as a mask, removing the gate
`oXide ?lm at a bottom of the pattern (step 7); removing the
`patterned resist (step 8); forming a second polysilicon layer
`(step 9); forming of resist a pattern providing a gate elec
`trode of an access transistor, a pattern providing a gate
`electrode of a driver transistor and a pattern providing a gate
`electrode of a transistor for peripheral circuitry (step 10);
`With the patterned resist used as a mask, dry-etching the ?rst
`and second polysilicon layers (step 11); removing the pat
`terned resist (step 12); doping only an n region With an n
`dopant (step 13); and thermally processing a resultant prod
`uct (step 14).
`In accordance With the present invention in a tWenty-ninth
`aspect an SRAM manufacturing method includes in step 6
`the step of illuminating a surface of the patterned resist in a
`N2 ambient With a deep ultraviolet light and successively
`thermally processing the patterned resist.
`In accordance With the present invention in a thirtieth
`aspect an SRAM manufacturing method includes in step 6
`the step of illuminating a surface of the patterned resist in a
`dry air With a deep ultraviolet light and successively ther
`mally processing the patterned resist.
`In accordance With the present invention in a thirty-?rst
`aspect an SRAM manufacturing method includes step 6
`thermally processing the patterned resist in a dry air.
`The foregoing and other objects, features, aspects and
`advantages of the present invention Will become more
`apparent from the folloWing detailed description of the
`present invention When taken in conjunction With the
`accompanying draWings.
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`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a cross section of a semiconductor device for
`illustrating a manufacturing method according to a ?rst
`embodiment of the present invention.
`FIGS. 2—4 are cross sections of a semiconductor device
`manufactured by a semiconductor device manufacturing
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`method according to a ?fth embodiment of the present
`invention, as shoWn at ?rst to third steps thereof, respec
`tively.
`FIG. 5 is a cross section of a semiconductor device
`manufactured by a ?ash memory manufacturing method
`according to a tenth embodiment of the present invention.
`FIGS. 6—10 are cross sections of a semiconductor device
`manufactured by a ?ash memory manufacturing method
`according to the tenth embodiment of the present invention,
`as shoWn at ?rst to ?fth steps thereof, respectively.
`FIG. 11 is a cross section of a conventional ?ash memo
`ry’s memory cell.
`FIGS. 12—15 are cross sections of a semiconductor device
`manufactured by a conventional ?ash memory manufactur
`ing method, as shoWn at ?rst to fourth steps thereof, respec
`tively.
`FIGS. 16 and 17 are cross sections of a semiconductor
`device manufactured by a conventional semiconductor
`device manufacturing method, shoWing a disadvantage
`thereof, as shoWn at ?rst and second steps thereof, respec
`tively.
`FIG. 18 is a cross section of a semiconductor device for
`illustrating a method according to a third embodiment of the
`present invention
`FIGS. 19—21 are cross sections of a semiconductor device
`manufactured by a method according to a seventh embodi
`ment of the present invention, as sho