UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`MACRONIX INTERNATIONAL CO., LTD., MACRONIX ASIA LIMITED,
`MACRONIX (HONG KONG) CO., LTD., and MACRONIX AMERICA, INC.
`Petitioners
`
`v.
`
`SPANSION LLC
`Patent Owner
`
`
`
`Case: Unassigned
`
`
`
`DECLARATION OF DHAVAL J. BRAHMBHATT
`
`
`
`
`
`
`
`
`Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`United States Patent and Trademark Office
`PO Box 1450
`Alexandria, Virginia 22313–1450
`Submitted Electronically via the Patent Review Processing System
`
`
`
`
`IPR2014-00898
`Exhibit MX027II-1002, p. 1
`
`
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`MACRONIX INTERNATIONAL CO., LTD., MACRONIX ASIA LIMITED,
`MACRONIX (HONG KONG) CO., LTD., and MACRONIX AMERICA, INC.
`Petitioners
`
`v.
`
`SPANSION LLC
`Patent Owner
`
`
`
`Case: Unassigned
`
`
`
`DECLARATION OF DHAVAL J. BRAHMBHATT
`
`
`
`
`
`
`
`
`Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`United States Patent and Trademark Office
`PO Box 1450
`Alexandria, Virginia 22313–1450
`Submitted Electronically via the Patent Review Processing System
`
`
`
`
`IPR2014-00898
`Exhibit MX027II-1002, p. 1
`
`
`
`I, Dhaval J. Brahmbhatt, hereby declare as follows:
`
`
`I.
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`Introduction and Qualifications
`
`1.
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`I am the founder and am currently the president and CEO of PHYchip
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`Corporation (“PHYchip”). Among other things, PHYchip provides expert services
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`in the design of high-speed analog and mixed-signal integrated circuit (“IC”)
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`memory devices, with a particular focus on non-volatile memory devices such as
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`Flash memory modules.
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`2.
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`I have prepared this Declaration on behalf of Macronix International
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`Co., Ltd., Macronix Asia Limited, Macronix (Hong Kong) Co., Ltd., and Macronix
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`America, Inc. (collectively, “Macronix”) in connection with a petition for Inter
`
`Partes Review of U.S. Patent No. 7,151,027 (“the ’027 Patent”) (MX027II-1001).
`
`3.
`
`I have summarized in this section relevant aspects of my educational
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`background and career history. My full CV has been filed herewith as Exhibit
`
`MX027II-1009.
`
`A. Educational Background
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`4.
`
`In 1977, I received a Master of Science Degree in Solid State
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`Electronics from Gujarat University in India. In 1978, I received a second Master
`
`of Science Degree, this one in Electrical Engineering, from the University of
`
`Cincinnati in Ohio. I also hold certificates in management from Stanford
`
`IPR2014-00898
`Exhibit MX027II-1002, p. 2
`
`
`
`University, and a certificate in nanotechnology from the California Institute of
`
`Nanotechnology.
`
`B. Career History
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`5.
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`I have over 30 years of substantive experience in the field of IC
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`memory device design and manufacture. I began my career in 1978 at a Fairchild
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`Semiconductor, working on
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`the design and development of Erasable
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`Programmable Read-Only Memory (“EPROM”) products. I later worked on the
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`design and production of Electronically Erasable Programmable Read-Only
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`Memory (“EEPROM”) products for Synertek, which is a subsidiary of Honeywell
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`International, Inc., and then for National Semiconductor on high density single
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`power supply EEPROM memory project. In 1983, I cofounded International
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`CMOS Technology, Inc., this company developed programmable memory and
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`programmable logic IC products. From 1989 to 1996, I was Product Line Director
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`of EPROM memory products groups at National Semiconductor with annual
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`revenues reaching $145 million.
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`6.
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`In 1996, I was named Vice President of Technology and Business
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`Development for the Smart Module Corporation. In that position, I oversaw the
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`design, development, and marketing of advanced IC memory-based modules such
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`as Flash memory cards for portable devices produced by major multinational
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`technology companies.
`
`IPR2014-00898
`Exhibit MX027II-1002, p. 3
`
`
`
`7.
`
`I later consulted in the Flash memory card industry and served as a
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`chief officer in several start-up companies that developed IC devices prior to
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`founding PHYchip Corporation in 2002.
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`8.
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`I am the sole inventor on ten patents and the lead inventor on an
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`eleventh. Majority of these patents relate to EPROM, EEPROM, and/or Flash
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`memory IC design, memory cell design, supporting circuits, etc.
`
`II.
`
`Scope of Assignment
`
`9.
`
`I have been asked to provide my opinion on the validity of the ’027
`
`Patent. In particular, I have been asked to consider whether the inventions recited
`
`in claims 7 and 14 of the ’027 Patent are unpatentable over certain published prior
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`art references. I have previously rendered a declaration in connection with an
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`earlier petition for inter partes review addressing certain other references. This
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`Declaration sets forth my opinion with respect to claims 7 and 14. Because claims
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`7 and 14 depend from claims 1 and 8, respectively, I have reproduced those
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`sections from my earlier declaration. Moreover, for the sake of completeness, I
`
`have also set forth my summary of relevant aspects of the ’027 Patent herein.
`
`10.
`
`In my analysis, I considered the ’027 Patent and its file history, as
`
`well as the prior art references and related documentation discussed below, as well
`
`as the prior art discussed in my declaration submitted with IPR2014-00108. I have
`
`considered these documents in light of the general knowledge in the art at the time
`
`IPR2014-00898
`Exhibit MX027II-1002, p. 4
`
`
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`of the alleged inventions. In formulating my opinion, I have relied upon my
`
`experience, education, and knowledge in the relevant art. I also helped prepare and
`
`reviewed in detail the claim charts included with the earlier petition for Inter
`
`Partes Review of the ’027 Patent, and which are included with this Petition with
`
`respect to claims 1 and 8 of the ’027 Patent.
`
`11. Additional information may become available which would further
`
`support or modify the conclusions that I have reached to date. Accordingly, I
`
`reserve the right to modify and/or enlarge this opinion or the bases thereof upon
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`consideration of any further discovery, testimony, or other evidence, or based upon
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`the interpretations of or conclusions about any claim term by the Patent Office
`
`different than those proposed in this declaration.
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`III. The ’027 Patent
`
`12.
`
`It appears from the face of the ’027 Patent that it issued from U.S.
`
`patent application number 10/859,369, which was filed on June 1, 2004. It does
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`not appear the patent claims an earlier filing date.
`
`13. The ’027 Patent generally relates to a method for manufacturing a
`
`semiconductor memory device. More particularly, the ’027 Patent is intended to
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`reduce the interface area of a memory device, by forming an interface structure in
`
`the area between the memory core and the periphery.
`
`IPR2014-00898
`Exhibit MX027II-1002, p. 5
`
`
`
`14. The ’027 Patent discloses an embodiment of the steps required to
`
`form this interface structure in Figures 3A through 3G, along with the
`
`accompanying text. In the following discussion, each of Figures 3A through 3G
`
`have been annotated to help distinguish the various layers.
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`15. First, as shown in Figure 3A, a first layer of polysilicon, or “poly-1,”
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`(green) is formed over an isolation area (light blue) over a silicon substrate (darker
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`blue). See MX027II-1001 at 3:50-67.
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`
`
`16. Next, as shown in Figure 3B, a dielectric material (red) is formed over
`
`the entire surface. The ’027 Patent describes an embodiment in which this
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`dielectric consists of “ONO,” a well known dielectric material that consists of
`
`layers of Silicon Oxide, Silicon Nitride, and Silicon Oxide. See MX027II-1001 at
`
`4:1-9.
`
`IPR2014-00898
`Exhibit MX027II-1002, p. 6
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`
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`17. Next, as shown in Figure 3C, a known etching process is used to
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`remove some of the dielectric and polysilicon layers.
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`
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`18. Next, as shown in Figure 3D, a second poly silicon layer, or “poly-2,”
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`(yellow) is formed over the entire structure. MX027II-1001 at 3:10-21
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`
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`19. Next, a known etch process, such as a “stacked gate etch,” is used to
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`etch the structure on the side nearest the memory core. This etch removes the
`
`
`
`IPR2014-00898
`Exhibit MX027II-1002, p. 7
`
`
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`poly-2 layer, the dielectric layer, and the poly-1 layer in the unmasked region. The
`
`resulting structure is illustrated in Figure 3E. MX027II-1001 at 4:27-37.
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`
`
`20. Next, a second etching process, such as a “second gate etch,” is used
`
`to etch the structure on the side nearest the periphery. This etch removes only the
`
`poly-2 layer (as that is the only layer in the unmasked region). After the
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`completion of these two etch steps, the interface structure remains in the interface
`
`area between the memory core and periphery. The resulting structure is illustrated
`
`in Figure 3F. MX027II-1001 at 4:38-49.
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`21. Finally, as illustrated in Figure 3G, dielectric material (purple) is
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`deposited on the entire structure, and selectively etched to form dielectric film 345
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`over the top of the core, interface structure, and periphery. This dielectric deposit
`
`
`
`IPR2014-00898
`Exhibit MX027II-1002, p. 8
`
`
`
`and etch process also creates spacers 350 on the side walls of the core, interface
`
`structure, and periphery. MX027II-1001 at 4:55 – 5:4.
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`
`
`IV. Summary of My Opinions
`
`Based on my investigation and analysis, and for the reasons set forth below,
`
`it is my opinion that claims 7 and 14 of the ’027 Patent would have been obvious
`
`over U.S. Patent No. 6,458,655 to Yuzuriha (“Yuzuriha”) (MX027II-1003), U.S.
`
`Patent Application Publication No. 2003/0042520
`
`to Tsukamoto et al.
`
`(“Tsukamoto”) and C.-F. Lin et al., A ULSI shallow trench isolation process
`
`through
`
`the
`
`integration of multilayered dielectric process and chemical-
`
`mechanical planarization, Thin Solid Films, pp. 248-252 (1999) (“the C.-F. Lin
`
`Article”).
`
`22.
`
`I have read and understood the claim charts for claims 1 and 8
`
`included in the Petition, and agree with the technical analysis set forth therein.
`
`IPR2014-00898
`Exhibit MX027II-1002, p. 9
`
`
`
`V. Background of Relevant Technology
`
`A.
`
`“Floating Gate” Memory Cells: EPROM, EEPROM and Flash
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`23. The ’027 Patent states that “[t]he present invention relates to the field
`
`of floating gate devices.” MX027II-1001 at 1:6-7. A “floating gate” is a well-
`
`known configuration that is used to create non-volatile memory, a class of
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`semiconductor memory that retains storage of data even after a power supply is
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`removed from the memory. Examples of technologies that can be implemented
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`using a floating gate include EPROM, EEPROM, and Flash – all of which are
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`types of non-volatile memory.
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`24. The floating gate structure has been in use since at least 1972, when
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`Dov Frohman of Intel was awarded U.S. Patent number 3,660,819. In this kind of
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`device, each storage location consists of a single Field Effect Transistor (FET) that
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`is different from other transistors because it also has over the transistor channel
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`gate oxide, an additional gate which is called the “floating gate” because it is not
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`connected to any node. Above the floating gate will be formed another insulating
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`layer, over which a second conducting gate called “control gate” will be deposited.
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`A cross section of a memory cell utilizing a floating gate can be illustrated as
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`follows:
`
`IPR2014-00898
`Exhibit MX027II-1002, p. 10
`
`
`
`
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`B.
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`25.
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`Etching
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`In semiconductor processing, “etching” generally refers to process of
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`applying a temporary layer commonly known as a “photoresist,” patterning the
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`photoresist into a “mask,” and then using chemicals to remove portions of the
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`semiconductor structure not covered by the mask. Once the intended removal is
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`complete, the photoresist is removed.
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`26. Etching is one of the fundamental techniques in semiconductor device
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`manufacture; the manufacture of a semiconductor device will typically include
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`many repetitions of the process of growing or depositing a layer of material, and
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`selectively etching the material in areas uncovered by the mask for that layer. The
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`’027 Patent does not utilize any novel etch processes, but describes the use of
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`known etch processes such as a “stacked gate etch.” See, e.g., MX027II-1001 at
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`4:27-30.
`
`IPR2014-00898
`Exhibit MX027II-1002, p. 11
`
`
`
`VI. Legal Principles Used in Analysis
`
`27.
`
`I am not a patent attorney, nor have I independently researched the
`
`law of patent validity. Attorneys have explained certain legal principles to me that
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`I have relied on in forming my opinions set forth in this Declaration.
`
`A.
`
`28.
`
`Person of Ordinary Skill in the Art
`
`I understand that assessment of the validity of claims 1-14 of the ’027
`
`Patent must be undertaken from the perspective of what would have been known or
`
`understood by someone of ordinary skill in the art as of the earliest claimed
`
`priority date of the ’027 Patent – June 1, 2004. From analyzing the ’027 Patent
`
`and the prior art, it is my opinion that a person of ordinary skill in the art would
`
`have a bachelor’s degree in Electrical Engineering and 2-3 years of experience in
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`design or fabrication of semiconductor memories. An individual with additional
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`education or industry experience could also be one of ordinary skill in the art if that
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`additional experience compensated for a deficit in the other aspect stated above.
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`Unless otherwise stated, when I state that something would be known or
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`understood by one skilled in the art, or having ordinary skill in the art, I am
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`referring to a person with this level of education and experience.
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`29. A person of ordinary skill in the art of semiconductor memory design
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`and fabrication would have looked to various sources of available information in
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`order to address the purported problem of the ’027 Patent – improving the
`
`IPR2014-00898
`Exhibit MX027II-1002, p. 12
`
`
`
`fabrication of memory devices at the interface between memory array and
`
`periphery. Identification of this problem, along with various solutions, can be
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`found in numerous references including Yuzuriha (MX027II-1003).
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`B.
`
`30.
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`Prior Art
`
`I have been informed that the law provides certain categories of
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`information (known as prior art) that may be used to anticipate or render obvious
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`patent claims. I have been asked to presume that the reference materials I opine on
`
`below are prior art, and have not formed an opinion whether these references are,
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`in fact, prior art as applied against the ’027 Patent.
`
`C. Anticipation
`
`31.
`
`I have been informed that a claim is not patentable when a single prior
`
`art reference describes every element of the claim, either expressly or inherently to
`
`a person of ordinary skill in the art. I understand that this is referred to as
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`“anticipation.” I have also been informed that, to anticipate a patent claim, the
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`prior art reference need not use the same words as the claim, but it must describe
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`the requirements of the claim with sufficient clarity that a person of skill in the art
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`would be able to make and use the claimed invention based on the single prior art
`
`reference.
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`32.
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`In addition, I was informed and understand that, in order to establish
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`that an element of a claim is “inherent” in the disclosure of a prior art reference, it
`
`IPR2014-00898
`Exhibit MX027II-1002, p. 13
`
`
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`must be clear to one skilled in the art that the missing element is an inevitable part
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`of what is explicitly described in the prior art, and that it would be recognized as
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`necessarily present by a person of ordinary skill in the art.
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`D. Obviousness
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`33.
`
`I have been informed that, even if every element of a claim is not
`
`found explicitly or implicitly in a single prior art reference, the claim may still be
`
`unpatentable if the differences between the claimed elements and the prior art are
`
`such that the subject matter as a whole would have been obvious at the time the
`
`invention was made to a person of ordinary skill in the art. That is, the invention
`
`may be obvious to a person having ordinary skill in the art when seen in light of
`
`one or more prior art references. I understand that a patent is obvious when it is
`
`only a combination of old and known elements, with no change in their respective
`
`functions, and that these familiar elements are combined according to known
`
`methods to obtain predictable results.
`
`34.
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`I have been informed that the following four factors are considered
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`when determining whether a patent claim is obvious: (1) the scope and content of
`
`the prior art; (2) the differences between the prior art and the claim; (3) the level of
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`ordinary skill in the art; and (4) secondary considerations tending to prove
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`obviousness or nonobviousness. I have also been informed that the courts have
`
`established a collection of secondary factors of nonobviousness, which include:
`
`IPR2014-00898
`Exhibit MX027II-1002, p. 14
`
`
`
`unexpected, surprising, or unusual results; non-analogous art; teachings away from
`
`the invention; substantially superior results; synergistic results; long-standing need;
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`commercial success; and copying by others. I have also been informed that there
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`must be a connection between these secondary factors and the scope of the claim
`
`language.
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`35.
`
`I have also been informed that some examples of rationales that may
`
`support a conclusion of obviousness include: (A) combining prior art elements
`
`according to known methods to yield predictable results; (B) simply substituting
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`one known element for another to obtain predictable results; (C) using known
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`techniques to improve similar devices (methods, or products) in the same way; (D)
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`applying a known technique to a known device (method, or product) ready for
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`improvement to yield predictable results; (E) choosing from a finite number of
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`identified, predictable solutions, with a reasonable expectation of success—in other
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`words, whether something is “obvious to try”; (F) using work in one field of
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`endeavor to prompt variations of that work for use in either the same field or a
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`different one based on design incentives or other market forces if the variations are
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`predictable to one of ordinary skill in the art; and (G) arriving at a claimed
`
`invention as a result of some teaching, suggestion, or motivation in the prior art
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`that would have led one of ordinary skill to modify the prior art reference or to
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`combine prior art reference teachings.
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`IPR2014-00898
`Exhibit MX027II-1002, p. 15
`
`
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`36.
`
`I have also been informed that other rationales to support a conclusion
`
`of obviousness may be relied upon, for instance, that the common sense (where
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`substantiated) of the person of skill in the art may be a reason to combine or
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`modify prior art to achieve the claimed invention.
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`VII. Claim Construction
`
`37. Attorneys have provided me with constructions of various terms
`
`within the ’027 Patent’s claims and I have read the Board’s prior claim
`
`constructions included in Decision: Institution of Inter Partes Review in IPR2014-
`
`00108, Paper No. 16 (May 8, 2014) (Ex. MX027II-1005). I have not been asked
`
`to form, and I have not formed, an opinion regarding these claim constructions
`
`except to note that the Board’s rejection of Patent Owner’s position that “etching
`
`said poly-1 layer and said poly-2 layer proximate to said memory array” does not
`
`require etching to be performed in a single step appears to be consistent with
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`principles of etching that were well known in the art by June 1, 2004. Specifically,
`
`it was well known that the composition of the etching gases used in connection
`
`with plasma etching processes used to etch poly-1, poly-2 and ONO were generally
`
`introduced in different steps. See, e.g., Ex. MX027II-1010 at 4:11-21 (discussing a
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`sequence of etching poly-2, ONO, and poly-1 layers and the selectivity during the
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`etching steps as part of a stacked gate etch). Below is a list of the constructions I
`
`have applied when rendering the opinions set forth herein:
`
`IPR2014-00898
`Exhibit MX027II-1002, p. 16
`
`
`
`Claim Term
`
`Broadest Reasonable Interpretation
`
`“interface between a memory array
`
`an area between an array of memory
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`and a periphery”
`
`cells and a periphery
`
`“etching said poly-1 layer and said
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`does not require the etching to be
`
`poly-2 layer proximate to said
`
`performed in a single step
`
`memory array”
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`“such that step size is smoothed out,
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`not a limitation
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`reducing an occurrence of stringers
`
`from spacer etching”
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`“poly-1 layer”
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`“poly-2 layer”
`
`
`
`VIII. Invalidity Analysis
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`a first polysilicon layer
`
`a polysilicon layer deposited later in time
`
`than a first polysilicon layer
`
`A. Claims 1 and 8 are anticipated by Yuzuriha
`
`38.
`
`I understand from Exhibit MX027II-1005 that the Board has instituted
`
`trial of claims 1 and 8 of the ’027 Patent based on Yuzuriha. However, since
`
`claims 7 and 14 of the ’027 Patent depend from claims 1 and 8, respectively, I
`
`provide the analysis of Yuzuriha as to claims 1 and 8 for the sake of completeness.
`
`i. Description of the reference
`
`IPR2014-00898
`Exhibit MX027II-1002, p. 17
`
`
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`39. Yuzuriha is entitled “Method of Manufacturing Semiconductor
`
`Device and Flash Memory.” I understand that Yuzuriha will be designated as
`
`Exhibit MX027-1003 to the Petition for Inter Partes Review. Based on the face of
`
`the patent, Yuzuriha was issued on October 1, 2002.
`
`40. Like the ‘’027 Patent, Yuzuriha is directed to a method for
`
`manufacturing a semiconductor memory that includes forming a structure between
`
`a memory array (referred to in Yuzuriha as a “memory cell region”) and a
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`periphery (“peripheral circuit region”).
`
`41. As shown in Figure 5 of Yuzuriha, a structure composed of poly-1
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`layer 10 (green), inter-layer dielectric 11 (red), poly-2 layer 13 (yellow), and top
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`layer of oxide 16 is formed in the “dummy gate region” between the memory array
`
`and the periphery.
`
`
`
`IPR2014-00898
`Exhibit MX027II-1002, p. 18
`
`
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`42. As discussed in more detail below, Yuzuriha discloses every element
`
`of (among other claims) claims 1 and 8 of the ’027 patent. It is therefore my
`
`opinion that these claims are unpatentable as anticipated by Yuzuhira.
`
`ii. Application to claims 1 and 8 of the ’027 Patent
`
`43. Claim 1 of the ’027 patent claims a method for fabricating a memory
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`device, comprising forming a poly-2 layer above a substrate at an interface
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`between a memory array and a periphery; etching the poly-2 layer proximate to the
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`memory array, and etching the poly-2 layer proximate to the periphery, such that a
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`portion of the poly-2 layer remains at the interface.
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`44.
`
`Independent claim 8 claims a method for fabricating a memory
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`device, comprising forming a poly-1 layer above a substrate at an interface
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`between a memory array and a periphery; forming a poly-2 layer above the poly-1
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`layer at the interface, etching the poly-1 and poly-2 layers proximate to the
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`memory array, and etching the poly-2 layer proximate to the periphery, such that a
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`portion of the poly 1 and poly-2 layers remain at the interface.
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`45. Yuzuriha discloses forming such a structure in its description of a
`
`tenth embodiment, which is illustrated in Figures 5-10. MX027II-1003 at 11:39-
`
`62. As described in Yuzuriha, Figure 5 is a cross section of a memory device, and
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`Figures 6-10 are cross sections of the device at various stages of its manufacture.
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`MX027II-1003 at 8:4-10.
`
`IPR2014-00898
`Exhibit MX027II-1002, p. 19
`
`
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`46. Figure 5 of Yuzuriha shows that a “dummy gate region” is located
`
`between a “memory cell region” and a “peripheral circuit region.”
`
`
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`47. To a person of skill in the art, the “memory cell region” of Yuzuriha is
`
`the same as the “memory array” of the ’027 Patent. Similarly, the “peripheral
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`circuit region” is the same as the “periphery” of the ’027 patent. The “dummy gate
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`region” of Yuzuriha is therefore the “interface between a memory array and a
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`periphery” claimed in the ’027 patent.
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`48. As part of the process of forming the structure in the interface of
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`Figure 5, Yuzuriha discloses that a “first polysilicon layer 10” is deposited across
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`the surface of the memory array, the interface, and the periphery. On top of the
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`polysilicon 10, a layer of dielectric, referred to as “poly-poly insulation film 11” is
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`also formed. Finally, a layer of photoresist 15 is added and patterned, so that it is
`
`covering the memory cell region and part of the interface, which are not to be
`
`IPR2014-00898
`Exhibit MX027II-1002, p. 20
`
`
`
`etched. Figure 6 shows the cross section of the device after these steps have been
`
`performed.
`
`
`
`49.
`
`It is common in the art to refer to layers of polysilicon by a number
`
`that indicates the position of the layer relative to the substrate (which will typically
`
`correspond to the order of manufacture). Because the “first polysilicon layer 10”
`
`of Figures 5-10 is the polysilicon layer closest to the substrate, one of skill in the
`
`art would refer to polysilicon layer 10 as “the poly-1 layer” (or more simply,
`
`“poly-1”).
`
`50.
`
`In the next step, Yuzuriha discloses etching the poly-1 layer
`
`proximate to the periphery (using the photoresist shown in Figure 6 as a mask), so
`
`that some of the poly-1 remains over the interface area. MX027II-1003 at 12:6-13.
`
`Figure 7 shows the structure after the unmasked area of poly-1 has been etched.
`
`IPR2014-00898
`Exhibit MX027II-1002, p. 21
`
`
`
`
`
`51. After removal of the photoresist, a second layer of polysilicon (13) is
`
`formed over the surface of the device, and a layer of oxide 16 is formed on top.
`
`MX027II-1003 at 12:28-30. Because this is the second layer of polysilicon
`
`deposited, a person of skill in the art would refer to this as the poly-2 layer. Figure
`
`8 shows the structure after these steps have been performed.
`
`
`
`IPR2014-00898
`Exhibit MX027II-1002, p. 22
`
`
`
`52. Although the text of Yuzuriha at column 12, lines 28 through 55
`
`makes reference to Figure 7, it is clear from the context that this text is actually
`
`describing Figure 8. First, Figure 7 was already described at lines 10 through 22.
`
`Second, the arrows A, B, and C that are described in this text appear only in Figure
`
`8. A person of skill in the art would easily recognize this typographical error, and
`
`would understand that this description applies to Figure 8.
`
`53. After formation of the poly-2 layer and oxide 16, the oxide and poly-2
`
`are etched, and “a memory cell’s control gate 13 and a peripheral circuitry’s
`
`transistor gate 13 are patterned.” MX027II-1003 at 12:56-59. As can be seen from
`
`Figure 9, this involves etching the poly-2 in the interface structure proximate to
`
`memory, and etching the poly-2 proximate to the periphery. After these etch steps,
`
`a portion of poly-2 remains in the interface area.
`
`
`
`IPR2014-00898
`Exhibit MX027II-1002, p. 23
`
`
`
`54. Finally, Yuzuriha describes using the remaining oxide film 16 as an
`
`etching mask, and etching the poly-poly insulation mask 11 and the poly-1.
`
`MX027II-1003 at 12:60-63. As such, the poly-1 in the interface area is etched
`
`proximate to the memory array. Figure 10 shows the result of this etch.
`
`55. Thus, it is my opinion that Yuzuriha discloses each and every aspect
`
`
`
`of claims 1 and 8.
`
`B. Claims 7 and 14 Would Have Been Obvious to One of Ordinary
`
`Skill in the Art Over Tsukamoto in view of the C.-F. Lin Article
`
`56. Claims 7 and 14 each state that “said portion of said poly-2 layer
`
`remaining at said interface is a same height as said memory array proximate to said
`
`memory array a same height as said periphery proximate to said periphery, such
`
`that step size is smoothed out reducing an occurrence of stringers from spacer
`
`IPR2014-00898
`Exhibit MX027II-1002, p. 24
`
`
`
`etching.”1 Yuzuriha discloses that the goal of fabricating the dummy gate region is
`
`to reduce “any abrupt step variation,” and that the interface structure is designed to
`
`result in “a gentle step” resulting in improvements in further photolithographic
`
`steps. MX027II-1003 at 12:37-55. It is my opinion that the decrease in “abrupt
`
`step variation is describing an increase in the planarization of the resulting
`
`structure, which has distinct advantages that would have been understood by a
`
`person of ordinary skill well before June 1, 2004 including improving
`
`photolithographic capabilities, reduction of stringers from etching processes, and
`
`improving metal step coverage for higher layers such as a metal-1 layer. See, e.g.,
`
`MX027II-1008 at 728-730.
`
`57. As discussed above, Yuzuriha discloses the formation of an interface
`
`structure (“dummy gate”) at the interface between a memory and a periphery. The
`
`“memory cell region” and a “peripheral circuit region” “sandwich” an interface.
`
`1 To the extent that the “such that” clause is construed to be a limitation, reduction
`
`of stringers is the necessary result of eliminating steps as would have been
`
`appreciated by a person of ordinary skill in the art reading the ’027 Patent. See Ex.
`
`MX027II-1001 at 2:62-66 (describing eliminating stringers by smoothing out steps
`
`created during etching); see also Ex. MX027II-1008 at 730 (discussing, in an
`
`analogous context, how metal stringers can be left behind from etching at sides of
`
`“steep steps”).
`
`IPR2014-00898
`Exhibit MX027II-1002, p. 25
`
`
`
`MX027II-1003 at 11:50-52. An “isolating oxide film” is formed “on” the substrate
`
`and is used to isolate the memory cell region from the peripheral circuit region. Id.
`
`at 11:52-54, 12:1-2. Yuzuriha specifically discloses that that the interface structure
`
`results in a “gentle step” rather than an “abrupt step variation.” MX027-1003 at
`
`12:37-52. Yuzuriha further discloses that this reduction results in subsequent
`
`photolithography, processing and the like [being] advantageously facilitated.” Id.
`
`at 12:53-55. As seen in Figure 5, Yuzuriha’s dummy gate is approximately equal
`
`in height to the memory cells proximate to the memory, and approximately equal
`
`in height to the periphery proximate to the periphery. Any differences in height in
`
`the dummy gate of Figure 5 result from the fact that the surrounding structures are
`
`on gate oxides 9 and 12, rather than “isolating oxide film 8.”
`
`58. Yuzuriha further discloses that a “gentle step” is formed between the
`
`memory array and the periphery, suggesting to a person of ordinary skill in the art,
`
`when taken in combination with, for example, Yuzuriha’s Figure 10, that the
`
`
`
`IPR2014-00898
`Exhibit MX027II-1002, p. 26
`
`
`
`“isolating oxide film,” may be formed using a process such as “local oxidation of
`
`silicon,” or LOCOS. This process was known to cause issues with planarization in
`
`that it tended to be elevated slightly from the substrate. Ex. MX027II-1006 at 248.
`
`The ’027 Patent’s only example shows the entire structure on the field oxide as
`
`shown in Figure 3G. A person of ordinary skill in the art could imagine a variety
`
`of different layout situations, such as the different layout example shown by
`
`Yuzuriha in FIG. 5 above. Yuzuriha’s FIG. 5 shows the dummy gate region on the
`
`thick isolation oxide based on the then prevalent LOCOS technology while the
`
`regions on either side are on the thin gate oxide. This may then result in a higher
`
`elevation of the middle “DUMMY GATE REGION.” Therefore due to this and a
`
`few other reasons such as the need for tighter layout, the industry was, by the late
`
`1990’s time frame, moving towards STI technology as explained by Tsukamoto,
`
`and, as I will discuss more below, the C.-F. Lin Article. Additionally, a person of
`
`ordinary skill in the art would understand that if Yuzhriha’s cross section were
`
`taken differently, all three sides would be on the thick field oxide to match the
`
`Figure 3G of the ’027 Patent. That the cross-sections may be different taken along
`
`different “slices” of the resulting chip is shown by, for example, Tsukamoto, which
`
`shows two cross-sections along A - A and along B - B in FIG. 19 and FIG. 20
`
`respectively.
`
`IPR2014-00898
`Exhibit MX027II-1002, p. 27
`
`
`
`59. As I mention above, a person of ordinary skill in the art would have
`
`also been aware of the teachings of the C.-F. Lin, et al. Article. In explaining the
`
`technological background of a new isolation process, the C.-F. Lin Article explains
`
`that isolation oxides such as those made by LOCOS had been used “[f]or a long
`
`time.” Id. As recognized by the C.-F. Lin Article, LOCOS was “the standard
`
`technology to provide electrical isolation between active devices for integrated
`
`circuits.” Ex. MX027II-1007 at 248. However, as was the prevailing trend for
`
`decades in the semiconductor industry, as device geometries were becoming
`
`smaller and densities were increasing, “even more stringent requirements were
`
`being placed upon isolation performance, and problems with LOCOS began to
`
`surface.” Id. One such problem was “poor planarity.” Id. “In light of these
`
`limitations, an alternative process called shallow trench isolation (STI) has been
`
`pursued actively be IC manufacturers as the substitute to LOCOS for device
`
`isolation.” Id. As recognized by th
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